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reset relay cleanup

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This commit is contained in:
Blaise Tine 2024-08-15 20:35:07 -07:00
parent 49738672ec
commit 65bd9afabb
20 changed files with 50 additions and 105 deletions
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5
hw/rtl/cache/VX_cache.sv vendored
View file

@ -136,17 +136,14 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
wire [NUM_REQS-1:0] core_rsp_ready_s;
`RESET_RELAY_EX (core_rsp_reset, reset, NUM_REQS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_elastic_buffer #(
.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
.SIZE (CORE_REQ_BUF_ENABLE ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0),
.OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF))
) core_rsp_buf (
.clk (clk),
.reset (core_rsp_reset[i]),
.reset (reset),
.valid_in (core_rsp_valid_s[i]),
.ready_in (core_rsp_ready_s[i]),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),

4
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -102,8 +102,6 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_bus_if[NUM_CACHES * NUM_REQS]();
`RESET_RELAY_EX (cache_arb_reset, reset, NUM_REQS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_mem_bus_if #(
.DATA_SIZE (WORD_SIZE),
@ -130,7 +128,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.RSP_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? 2 : 0)
) cache_arb (
.clk (clk),
.reset (cache_arb_reset[i]),
.reset (reset),
.bus_in_if (core_bus_tmp_if),
.bus_out_if (arb_core_bus_tmp_if)
);

10
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -110,8 +110,6 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
if (NC_OR_BYPASS) begin : bypass_if
`RESET_RELAY (nc_bypass_reset, reset);
VX_cache_bypass #(
.NUM_REQS (NUM_REQS),
.TAG_SEL_IDX (TAG_SEL_IDX),
@ -135,7 +133,7 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.MEM_OUT_BUF (MEM_OUT_BUF)
) cache_bypass (
.clk (clk),
.reset (nc_bypass_reset),
.reset (reset),
.core_bus_in_if (core_bus_if),
.core_bus_out_if(core_bus_cache_if),
@ -160,9 +158,7 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
end
if (PASSTHRU == 0) begin : cache_if
`RESET_RELAY (cache_reset, reset);
VX_cache #(
.INSTANCE_ID (INSTANCE_ID),
.CACHE_SIZE (CACHE_SIZE),
@ -184,7 +180,7 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.MEM_OUT_BUF (NC_OR_BYPASS ? 1 : MEM_OUT_BUF)
) cache (
.clk (clk),
.reset (cache_reset),
.reset (reset),
`ifdef PERF_ENABLE
.cache_perf (cache_perf),
`endif

2
hw/rtl/core/VX_alu_unit.sv
View file

@ -57,7 +57,7 @@ module VX_alu_unit #(
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alu_blocks
`RESET_RELAY_EN (block_reset, reset,(BLOCK_SIZE > 1));
`RESET_RELAY_EN (block_reset, reset, (BLOCK_SIZE > 1));
wire is_muldiv_op = `EXT_M_ENABLED && (per_block_execute_if[block_idx].data.op_args.alu.xtype == `ALU_TYPE_MULDIV);

4
hw/rtl/core/VX_commit.sv
View file

@ -53,8 +53,6 @@ module VX_commit import VX_gpu_pkg::*, VX_trace_pkg::*; #(
assign commit_if[j * `ISSUE_WIDTH + i].ready = ready_in[j];
end
`RESET_RELAY (arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (`NUM_EX_UNITS),
.DATAW (DATAW),
@ -62,7 +60,7 @@ module VX_commit import VX_gpu_pkg::*, VX_trace_pkg::*; #(
.OUT_BUF (1)
) commit_arb (
.clk (clk),
.reset (arb_reset),
.reset (reset),
.valid_in (valid_in),
.ready_in (ready_in),
.data_in (data_in),

4
hw/rtl/core/VX_core.sv
View file

@ -306,8 +306,6 @@ module VX_core import VX_gpu_pkg::*; #(
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) dcache_bus_tmp_if[DCACHE_CHANNELS]();
`RESET_RELAY (lsu_adapter_reset, reset);
VX_lsu_adapter #(
.NUM_LANES (DCACHE_CHANNELS),
.DATA_SIZE (DCACHE_WORD_SIZE),
@ -318,7 +316,7 @@ module VX_core import VX_gpu_pkg::*; #(
.RSP_OUT_BUF (0)
) lsu_adapter (
.clk (clk),
.reset (lsu_adapter_reset),
.reset (reset),
.lsu_mem_if (dcache_coalesced_if),
.mem_bus_if (dcache_bus_tmp_if)
);

5
hw/rtl/core/VX_dispatch.sv
View file

@ -54,16 +54,13 @@ module VX_dispatch import VX_gpu_pkg::*; #(
assign operands_if.ready = operands_reset[operands_if.data.ex_type];
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
`RESET_RELAY (buffer_reset, reset);
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (2),
.OUT_REG (1)
) buffer (
.clk (clk),
.reset (buffer_reset),
.reset (reset),
.valid_in (operands_if.valid && (operands_if.data.ex_type == `EX_BITS'(i))),
.ready_in (operands_reset[i]),
.data_in ({

6
hw/rtl/core/VX_dispatch_unit.sv
View file

@ -85,8 +85,6 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
wire [ISSUE_W-1:0] issue_idx = ISSUE_W'(batch_idx * BLOCK_SIZE) + ISSUE_W'(block_idx);
assign issue_indices[block_idx] = issue_idx;
`RESET_RELAY_EN (block_reset, reset, (BLOCK_SIZE > 1));
wire valid_p, ready_p;
if (`NUM_THREADS != NUM_LANES) begin
@ -102,7 +100,7 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
wire fire_eop = fire_p && is_last_p;
always @(posedge clk) begin
if (block_reset) begin
if (reset) begin
sent_mask_p <= '0;
is_first_p <= 1;
end else begin
@ -225,7 +223,7 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) buf_out (
.clk (clk),
.reset (block_reset),
.reset (reset),
.valid_in (valid_p),
.ready_in (ready_p),
.data_in ({

2
hw/rtl/core/VX_issue.sv
View file

@ -77,7 +77,7 @@ module VX_issue import VX_gpu_pkg::*; #(
assign decode_if.ibuf_pop[issue_id * PER_ISSUE_WARPS +: PER_ISSUE_WARPS] = per_issue_decode_if.ibuf_pop;
`endif
`RESET_RELAY (slice_reset, reset);
`RESET_RELAY_EN (slice_reset, reset, (`ISSUE_WIDTH > 1));
VX_issue_slice #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, issue_id)),

10
hw/rtl/core/VX_lmem_unit.sv
View file

@ -39,8 +39,6 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (LSU_TAG_WIDTH)
) lsu_lmem_if[`NUM_LSU_BLOCKS]();
`RESET_RELAY_EX (block_reset, reset, `NUM_LSU_BLOCKS, 1);
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : demux_slices
wire [`NUM_LSU_LANES-1:0] is_addr_local_mask;
@ -60,7 +58,7 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.OUT_REG (3)
) req_global_buf (
.clk (clk),
.reset (block_reset[i]),
.reset (reset),
.valid_in (lsu_mem_in_if[i].req_valid && is_addr_global),
.data_in ({
lsu_mem_in_if[i].req_data.mask & ~is_addr_local_mask,
@ -91,7 +89,7 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.OUT_REG (0)
) req_local_buf (
.clk (clk),
.reset (block_reset[i]),
.reset (reset),
.valid_in (lsu_mem_in_if[i].req_valid && is_addr_local),
.data_in ({
lsu_mem_in_if[i].req_data.mask & is_addr_local_mask,
@ -126,7 +124,7 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.OUT_BUF (1)
) rsp_arb (
.clk (clk),
.reset (block_reset[i]),
.reset (reset),
.valid_in ({
lsu_lmem_if[i].rsp_valid,
lsu_mem_out_if[i].rsp_valid
@ -167,7 +165,7 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.RSP_OUT_BUF (0)
) lsu_adapter (
.clk (clk),
.reset (block_reset[i]),
.reset (reset),
.lsu_mem_if (lsu_lmem_if[i]),
.mem_bus_if (lmem_bus_tmp_if)
);

2
hw/rtl/core/VX_lsu_unit.sv
View file

@ -56,7 +56,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsu_blocks
`RESET_RELAY (slice_reset, reset);
`RESET_RELAY_EN (slice_reset, reset, (BLOCK_SIZE > 1));
VX_lsu_slice #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, block_idx))

20
hw/rtl/core/VX_operands.sv
View file

@ -99,6 +99,8 @@ module VX_operands import VX_gpu_pkg::*; #(
assign req_in_valid = {NUM_SRC_OPDS{scoreboard_if.valid}} & src_valid;
`RESET_RELAY (req_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_SRC_OPDS),
.NUM_OUTPUTS (NUM_BANKS),
@ -108,7 +110,7 @@ module VX_operands import VX_gpu_pkg::*; #(
.OUT_BUF (0) // no output buffering
) req_xbar (
.clk (clk),
.reset (reset),
.reset (req_xbar_reset),
`UNUSED_PIN(collisions),
.valid_in (req_in_valid),
.data_in (req_in_data),
@ -247,25 +249,13 @@ module VX_operands import VX_gpu_pkg::*; #(
assign gpr_wr_bank_idx = '0;
end
`ifdef GPR_RESET
reg wr_enabled = 0;
always @(posedge clk) begin
if (reset) begin
wr_enabled <= 1;
end
end
`else
wire wr_enabled = 1;
`endif
for (genvar b = 0; b < NUM_BANKS; ++b) begin
wire gpr_wr_enabled;
if (BANK_SEL_BITS != 0) begin
assign gpr_wr_enabled = wr_enabled
&& writeback_if.valid
assign gpr_wr_enabled = writeback_if.valid
&& (gpr_wr_bank_idx == BANK_SEL_BITS'(b));
end else begin
assign gpr_wr_enabled = wr_enabled && writeback_if.valid;
assign gpr_wr_enabled = writeback_if.valid;
end
wire [BYTEENW-1:0] wren;

4
hw/rtl/core/VX_schedule.sv
View file

@ -377,7 +377,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
wire [`NUM_WARPS-1:0] pending_warp_empty;
wire [`NUM_WARPS-1:0] pending_warp_alm_empty;
`RESET_RELAY_EX (pending_instr_reset, reset, `NUM_WARPS, `MAX_FANOUT);
`RESET_RELAY (pending_instr_reset, reset);
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
VX_pending_size #(
@ -385,7 +385,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
.ALM_EMPTY (1)
) counter (
.clk (clk),
.reset (pending_instr_reset[i]),
.reset (pending_instr_reset),
.incr (schedule_if_fire && (schedule_if.data.wid == `NW_WIDTH'(i))),
.decr (commit_sched_if.committed_warps[i]),
.empty (pending_warp_empty[i]),

4
hw/rtl/core/VX_scoreboard.sv
View file

@ -239,8 +239,6 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
assign staging_if[w].ready = arb_ready_in[w] && operands_ready[w];
end
`RESET_RELAY (arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (PER_ISSUE_WARPS),
.DATAW (DATAW),
@ -248,7 +246,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
.OUT_BUF (3)
) out_arb (
.clk (clk),
.reset (arb_reset),
.reset (reset),
.valid_in (arb_valid_in),
.ready_in (arb_ready_in),
.data_in (arb_data_in),

5
hw/rtl/core/VX_split_join.sv
View file

@ -46,15 +46,12 @@ module VX_split_join import VX_gpu_pkg::*; #(
wire ipdom_pop = valid && sjoin.valid && sjoin_is_dvg;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : ipdom_slices
`RESET_RELAY (ipdom_reset, reset);
VX_ipdom_stack #(
.WIDTH (`NUM_THREADS+`PC_BITS),
.DEPTH (`DV_STACK_SIZE)
) ipdom_stack (
.clk (clk),
.reset (ipdom_reset),
.reset (reset),
.q0 (ipdom_q0),
.q1 (ipdom_q1),
.d (ipdom_data[i]),

10
hw/rtl/libs/VX_avs_adapter.sv
View file

@ -81,15 +81,13 @@ module VX_avs_adapter #(
assign req_queue_push[i] = mem_req_valid && ~mem_req_rw && bank_req_ready[i] && (req_bank_sel == i);
end
`RESET_RELAY_EX (bank_reset, reset, NUM_BANKS, 1);
for (genvar i = 0; i < NUM_BANKS; ++i) begin
VX_pending_size #(
.SIZE (RD_QUEUE_SIZE)
) pending_size (
.clk (clk),
.reset (bank_reset[i]),
.reset (reset),
.incr (req_queue_push[i]),
.decr (req_queue_pop[i]),
`UNUSED_PIN (empty),
@ -105,7 +103,7 @@ module VX_avs_adapter #(
.DEPTH (RD_QUEUE_SIZE)
) rd_req_queue (
.clk (clk),
.reset (bank_reset[i]),
.reset (reset),
.push (req_queue_push[i]),
.pop (req_queue_pop[i]),
.data_in (mem_req_tag),
@ -135,7 +133,7 @@ module VX_avs_adapter #(
.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF))
) req_out_buf (
.clk (clk),
.reset (bank_reset[i]),
.reset (reset),
.valid_in (valid_out_w),
.ready_in (ready_out_w),
.data_in ({mem_req_rw, mem_req_byteen, req_bank_off, mem_req_data}),
@ -177,7 +175,7 @@ module VX_avs_adapter #(
.DEPTH (RD_QUEUE_SIZE)
) rd_rsp_queue (
.clk (clk),
.reset (bank_reset[i]),
.reset (reset),
.push (avs_readdatavalid[i]),
.pop (req_queue_pop[i]),
.data_in (avs_readdata[i]),

20
hw/rtl/libs/VX_stream_arb.sv
View file

@ -49,8 +49,6 @@ module VX_stream_arb #(
localparam SLICE_END = `MIN(SLICE_BEGIN + NUM_REQS, NUM_INPUTS);
localparam SLICE_SIZE = SLICE_END - SLICE_BEGIN;
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (SLICE_SIZE),
.NUM_OUTPUTS (1),
@ -60,7 +58,7 @@ module VX_stream_arb #(
.OUT_BUF (OUT_BUF)
) arb_slice (
.clk (clk),
.reset (slice_reset),
.reset (reset),
.valid_in (valid_in[SLICE_END-1: SLICE_BEGIN]),
.ready_in (ready_in[SLICE_END-1: SLICE_BEGIN]),
.data_in (data_in[SLICE_END-1: SLICE_BEGIN]),
@ -92,8 +90,6 @@ module VX_stream_arb #(
wire [DATAW-1:0] data_tmp_u;
wire [`LOG2UP(SLICE_SIZE)-1:0] sel_tmp_u;
`RESET_RELAY (slice_reset, reset);
if (MAX_FANOUT != 1) begin
VX_stream_arb #(
.NUM_INPUTS (SLICE_SIZE),
@ -104,7 +100,7 @@ module VX_stream_arb #(
.OUT_BUF (`TO_OUT_RBUF(OUT_BUF)) // to registered output
) fanout_slice_arb (
.clk (clk),
.reset (slice_reset),
.reset (reset),
.valid_in (valid_in[SLICE_END-1: SLICE_BEGIN]),
.data_in (data_in[SLICE_END-1: SLICE_BEGIN]),
.ready_in (ready_in[SLICE_END-1: SLICE_BEGIN]),
@ -206,8 +202,6 @@ module VX_stream_arb #(
localparam SLICE_END = `MIN(SLICE_BEGIN + NUM_REQS, NUM_OUTPUTS);
localparam SLICE_SIZE = SLICE_END - SLICE_BEGIN;
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (1),
.NUM_OUTPUTS (SLICE_SIZE),
@ -217,7 +211,7 @@ module VX_stream_arb #(
.OUT_BUF (OUT_BUF)
) arb_slice (
.clk (clk),
.reset (slice_reset),
.reset (reset),
.valid_in (valid_in[i]),
.ready_in (ready_in[i]),
.data_in (data_in[i]),
@ -267,8 +261,6 @@ module VX_stream_arb #(
localparam SLICE_END = `MIN(SLICE_BEGIN + MAX_FANOUT, NUM_OUTPUTS);
localparam SLICE_SIZE = SLICE_END - SLICE_BEGIN;
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (1),
.NUM_OUTPUTS (SLICE_SIZE),
@ -278,7 +270,7 @@ module VX_stream_arb #(
.OUT_BUF (OUT_BUF)
) fanout_slice_arb (
.clk (clk),
.reset (slice_reset),
.reset (reset),
.valid_in (valid_tmp[i]),
.ready_in (ready_tmp[i]),
.data_in (data_tmp[i]),
@ -342,8 +334,6 @@ module VX_stream_arb #(
// #Inputs == #Outputs
`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
VX_elastic_buffer #(
@ -353,7 +343,7 @@ module VX_stream_arb #(
.LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset[i]),
.reset (reset),
.valid_in (valid_in[i]),
.ready_in (ready_in[i]),
.data_in (data_in[i]),

14
hw/rtl/libs/VX_stream_switch.sv
View file

@ -72,8 +72,6 @@ module VX_stream_switch #(
end
end
`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
VX_elastic_buffer #(
.DATAW (DATAW),
@ -81,7 +79,7 @@ module VX_stream_switch #(
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset[i]),
.reset (reset),
.valid_in (valid_out_r[i]),
.ready_in (ready_out_r[i]),
.data_in (data_out_r[i]),
@ -103,8 +101,6 @@ module VX_stream_switch #(
assign ready_in[i] = ready_out_r[i][sel_in[i]];
end
`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
localparam ii = i * NUM_REQS + j;
@ -115,7 +111,7 @@ module VX_stream_switch #(
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset[ii]),
.reset (reset),
.valid_in (valid_out_r[i][j]),
.ready_in (ready_out_r[i][j]),
.data_in (data_in[i]),
@ -124,7 +120,7 @@ module VX_stream_switch #(
.ready_out (ready_out[ii])
);
end else begin
`UNUSED_VAR (out_buf_reset[ii])
`UNUSED_VAR (reset)
`UNUSED_VAR (valid_out_r[i][j])
assign ready_out_r[i][j] = '0;
end
@ -137,8 +133,6 @@ module VX_stream_switch #(
`UNUSED_VAR (sel_in)
`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
VX_elastic_buffer #(
.DATAW (DATAW),
@ -146,7 +140,7 @@ module VX_stream_switch #(
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset[i]),
.reset (reset),
.valid_in (valid_in[i]),
.ready_in (ready_in[i]),
.data_in (data_in[i]),

8
hw/rtl/libs/VX_stream_xbar.sv
View file

@ -58,8 +58,6 @@ module VX_stream_xbar #(
assign valid_in_q[j] = valid_in[j] && (sel_in[j] == i);
end
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (NUM_INPUTS),
.NUM_OUTPUTS (1),
@ -69,7 +67,7 @@ module VX_stream_xbar #(
.OUT_BUF (OUT_BUF)
) xbar_arb (
.clk (clk),
.reset (slice_reset),
.reset (reset),
.valid_in (valid_in_q),
.data_in (data_in),
.ready_in (per_output_ready_in[i]),
@ -123,8 +121,6 @@ module VX_stream_xbar #(
assign data_out_r = {NUM_OUTPUTS{data_in}};
assign ready_in = ready_out_r[sel_in];
`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, `MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
VX_elastic_buffer #(
.DATAW (DATAW),
@ -133,7 +129,7 @@ module VX_stream_xbar #(
.LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset[i]),
.reset (reset),
.valid_in (valid_out_r[i]),
.ready_in (ready_out_r[i]),
.data_in (data_out_r[i]),

16
hw/rtl/mem/VX_local_mem.sv
View file

@ -116,6 +116,8 @@ module VX_local_mem import VX_gpu_pkg::*; #(
assign mem_bus_if[i].req_ready = req_ready_in[i];
end
`RESET_RELAY (req_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_REQS),
.NUM_OUTPUTS (NUM_BANKS),
@ -125,7 +127,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.OUT_BUF (3) // output should be registered for the data_store addressing
) req_xbar (
.clk (clk),
.reset (reset),
.reset (req_xbar_reset),
`ifdef PERF_ENABLE
.collisions (perf_collisions),
`else
@ -163,8 +165,6 @@ module VX_local_mem import VX_gpu_pkg::*; #(
wire bank_rsp_valid, bank_rsp_ready;
wire [WORD_WIDTH-1:0] bank_rsp_data;
`RESET_RELAY_EN (bram_reset, reset, (NUM_BANKS > 1));
VX_sp_ram #(
.DATAW (WORD_WIDTH),
.SIZE (WORDS_PER_BANK),
@ -172,7 +172,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.reset (bram_reset),
.reset (reset),
.read (per_bank_req_valid[i] && per_bank_req_ready[i] && ~per_bank_req_rw[i]),
.write (per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]),
.wren (per_bank_req_byteen[i]),
@ -185,7 +185,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
reg [BANK_ADDR_WIDTH-1:0] last_wr_addr;
reg last_wr_valid;
always @(posedge clk) begin
if (bram_reset) begin
if (reset) begin
last_wr_valid <= 0;
end else begin
last_wr_valid <= per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i];
@ -203,7 +203,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.DATAW (REQ_SEL_WIDTH + WORD_WIDTH + TAG_WIDTH)
) bram_buf (
.clk (clk),
.reset (bram_reset),
.reset (reset),
.valid_in (bank_rsp_valid),
.ready_in (bank_rsp_ready),
.data_in ({per_bank_req_idx[i], bank_rsp_data, per_bank_req_tag[i]}),
@ -225,6 +225,8 @@ module VX_local_mem import VX_gpu_pkg::*; #(
wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out;
wire [NUM_REQS-1:0] rsp_ready_out;
`RESET_RELAY (rsp_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_BANKS),
.NUM_OUTPUTS (NUM_REQS),
@ -233,7 +235,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.OUT_BUF (OUT_BUF)
) rsp_xbar (
.clk (clk),
.reset (reset),
.reset (rsp_xbar_reset),
`UNUSED_PIN (collisions),
.sel_in (per_bank_rsp_idx),
.valid_in (per_bank_rsp_valid),