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minor update

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This commit is contained in:
Blaise Tine 2021-04-05 11:57:46 -07:00
parent 0f05efbcf4
commit 66ff74eb97
3 changed files with 11 additions and 19 deletions
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18
hw/rtl/tex_unit/VX_tex_memory.v
View file

@ -26,7 +26,6 @@ module VX_tex_memory #(
output wire [`NW_BITS-1:0] rsp_wid,
output wire [`NUM_THREADS-1:0] rsp_tmask,
output wire [31:0] rsp_PC,
output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
output wire [`NUM_THREADS-1:0][3:0][31:0] rsp_data,
output wire [REQ_INFO_WIDTH-1:0] rsp_info,
input wire rsp_ready
@ -169,8 +168,7 @@ module VX_tex_memory #(
wire [`NUM_THREADS-1:0][3:0][31:0] rsp_texels_qual;
reg [`NUM_THREADS-1:0][31:0] rsp_data_qual;
reg [RSP_CTR_W-1:0] rsp_rem_ctr;
wire [`NUM_THREADS-1:0] rsp_cur_tmask;
wire [RSP_CTR_W-1:0] rsp_max_cnt;
wire [`NUM_THREADS-1:0] rsp_cur_tmask;
wire [$clog2(`NUM_THREADS + 1)-1:0] rsp_cur_cnt;
wire dcache_rsp_fire;
wire [1:0] rsp_texel_idx;
@ -186,8 +184,6 @@ module VX_tex_memory #(
assign rsp_cur_cnt = $countones(rsp_cur_tmask);
assign rsp_max_cnt = $countones(q_req_tmask) * (q_req_filter ? 4 : 1);
for (genvar i = 0; i < `NUM_THREADS; i++) begin
wire [31:0] src_mask = {32{dcache_rsp_if.valid[i]}};
wire [31:0] src_data = ((i == 0 || rsp_texel_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i]) & src_mask;
@ -226,7 +222,7 @@ module VX_tex_memory #(
rsp_rem_ctr <= 0;
end else begin
if ((| dcache_req_fire) && 0 == rsp_rem_ctr) begin
rsp_rem_ctr <= rsp_max_cnt;
rsp_rem_ctr <= q_req_filter ? {$countones(q_req_tmask), 2'b0} : {2'b0, $countones(q_req_tmask)};
end else if (dcache_rsp_fire) begin
rsp_rem_ctr <= rsp_rem_ctr - RSP_CTR_W'(rsp_cur_cnt);
end
@ -246,14 +242,14 @@ module VX_tex_memory #(
assign reqq_pop = rsp_texels_done && ~stall_out;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + (4 * `NUM_THREADS * 32) + REQ_INFO_WIDTH),
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + (4 * `NUM_THREADS * 32) + REQ_INFO_WIDTH),
.RESETW (1)
) rsp_pipe_reg (
.clk (clk),
.reset (reset),
.enable (~stall_out),
.data_in ({rsp_texels_done, q_req_wid, q_req_tmask, q_req_PC, q_req_filter, rsp_texels_qual, q_req_info}),
.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_filter, rsp_data, rsp_info})
.data_in ({rsp_texels_done, q_req_wid, q_req_tmask, q_req_PC, rsp_texels_qual, q_req_info}),
.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_data, rsp_info})
);
// Can accept new cache response?
@ -280,8 +276,8 @@ module VX_tex_memory #(
$write("\n");
end
if (rsp_valid && rsp_ready) begin
$write("%t: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, filter=%0d, data=",
$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter);
$write("%t: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask);
`PRINT_ARRAY2D(rsp_data, 4, `NUM_THREADS);
$write("\n");
end

5
hw/rtl/tex_unit/VX_tex_sampler.v
View file

@ -13,7 +13,6 @@ module VX_tex_sampler #(
input wire [31:0] req_PC,
input wire [`NR_BITS-1:0] req_rd,
input wire req_wb,
input wire [`TEX_FILTER_BITS-1:0] req_filter,
input wire [`TEX_FORMAT_BITS-1:0] req_format,
input wire [`NUM_THREADS-1:0][3:0][31:0] req_data,
input wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] req_blend_u,
@ -118,8 +117,8 @@ module VX_tex_sampler #(
`ifdef DBG_PRINT_TEX
always @(posedge clk) begin
if (req_valid && req_ready) begin
$write("%t: core%0d-tex-sampler-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, format=%0d, data=",
$time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_format);
$write("%t: core%0d-tex-sampler-req: wid=%0d, PC=%0h, tmask=%b, format=%0d, data=",
$time, CORE_ID, req_wid, req_PC, req_tmask, req_format);
`PRINT_ARRAY2D(req_data, 4, `NUM_THREADS);
$write(", u0=");
`PRINT_ARRAY1D(req_blend_u, `NUM_THREADS);

7
hw/rtl/tex_unit/VX_tex_unit.v
View file

@ -103,7 +103,6 @@ module VX_tex_unit #(
wire [`NW_BITS-1:0] mem_rsp_wid;
wire [`NUM_THREADS-1:0] mem_rsp_tmask;
wire [31:0] mem_rsp_PC;
wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
wire [REQ_INFO_WIDTH_M-1:0] mem_rsp_info;
wire mem_rsp_ready;
@ -175,8 +174,7 @@ module VX_tex_unit #(
.rsp_valid (mem_rsp_valid),
.rsp_wid (mem_rsp_wid),
.rsp_tmask (mem_rsp_tmask),
.rsp_PC (mem_rsp_PC),
.rsp_filter(mem_rsp_filter),
.rsp_PC (mem_rsp_PC),
.rsp_data (mem_rsp_data),
.rsp_info (mem_rsp_info),
.rsp_ready (mem_rsp_ready)
@ -202,8 +200,7 @@ module VX_tex_unit #(
.req_wid (mem_rsp_wid),
.req_tmask (mem_rsp_tmask),
.req_PC (mem_rsp_PC),
.req_data (mem_rsp_data),
.req_filter (mem_rsp_filter),
.req_data (mem_rsp_data),
.req_format (rsp_format),
.req_blend_u(rsp_blend_u),
.req_blend_v(rsp_blend_v),