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Fix load/store

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This commit is contained in:
Shashank Holla 2023-04-21 23:08:11 -04:00 • committed by Blaise Tine
parent 0887db4e05
commit 68f69b6c72
2 changed files with 13 additions and 13 deletions
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4
hw/rtl/core/VX_alu_unit.sv
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@ -84,12 +84,12 @@ module VX_alu_unit #(
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire [`XLEN:0] shr_in1 = {alu_signed & alu_in1[i][`XLEN-1], alu_in1[i]};
wire [`XLEN-1:0] temp_shr_result = `XLEN'($signed(shr_in1) >>> alu_B[i][SHIFT_IMM_BITS:0]);
wire [31:0] temp_shr_result_w = 32'($signed(shr_in1) >>> alu_B[i][4:0]);
wire [31:0] temp_shr_result_w = 32'($signed(shr_in1[31:0]) >>> alu_B[i][4:0]);
always @(*) begin
case(alu_op)
`INST_ALU_SRA, `INST_ALU_SRL: shr_result[i] = temp_shr_result;
`INST_ALU_SRA_W: shr_result[i] = `XLEN'($unsigned(temp_shr_result_w[31:0])); // is this needed or is it already 0 extended?
`INST_ALU_SRA_W: shr_result[i] = `XLEN'($signed(temp_shr_result_w[31:0])); // is this needed or is it already 0 extended?
`INST_ALU_SRL_W: shr_result[i] = `XLEN'($signed(temp_shr_result_w[31:0]));
default: shr_result[i] = temp_shr_result;
endcase

22
hw/rtl/core/VX_lsu_unit.sv
View file

@ -139,29 +139,29 @@ module VX_lsu_unit #(
end
// data formatting
wire[`NUM_THREADS-1:0][REQ_ASHIFT-1:0] req_align_X1;
// wire[`NUM_THREADS-1:0][REQ_ASHIFT-1:0] req_align_X1;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
`ifdef MODE_32_BIT
assign req_align_X1[i] = {req_align[i][1], 1'b1};
`endif
`ifdef MODE_64_BIT
// `ifdef MODE_32_BIT
// assign req_align_X1[i] = {req_align[i][1], 1'b1};
// `endif
// `ifdef MODE_64_BIT
// TODO: VARUN TO CHECK
assign req_align_X1[i] = {req_align[i][1:0], 1'b1};
`endif
// assign req_align_X1[i] = {req_align[i][1:0], 1'b1};
// `endif
always @(*) begin
mem_req_byteen[i] = {DCACHE_WORD_SIZE{lsu_req_if.wb}};
case (`INST_LSU_WSIZE(lsu_req_if.op_type))
0: mem_req_byteen[i][req_align[i]] = 1;
1: begin // half (16 bit)
mem_req_byteen[i][req_align[i]] = 1;
mem_req_byteen[i][req_align_X1[i]] = 1;
mem_req_byteen[i][req_align[i]+1] = 1;
end
2: begin // word (32 bit)
mem_req_byteen[i][req_align[i]] = 1;
mem_req_byteen[i][req_align_X1[i]] = 1;
mem_req_byteen[i][req_align_X1[i]+1] = 1;
mem_req_byteen[i][req_align_X1[i]+2] = 1;
mem_req_byteen[i][req_align[i]+1] = 1;
mem_req_byteen[i][req_align[i]+2] = 1;
mem_req_byteen[i][req_align[i]+3] = 1;
end
default : mem_req_byteen[i] = {DCACHE_WORD_SIZE{1'b1}}; // double (64 bit)
endcase