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mino rupdate

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This commit is contained in:
Blaise Tine 2024-04-15 19:23:20 -07:00
parent ac669a30ca
commit 69fdb4bd04
3 changed files with 3 additions and 1 deletions
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2
hw/rtl/core/VX_csr_data.sv
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@ -23,7 +23,7 @@
`else
`define CSR_READ_64(addr, dst, src) \
addr : dst = src[31:0]; \
(addr + (`VX_CSR_MPM_BASE_H-`VX_CSR_MPM_BASE)) : dst = 32'(src[$bits(src)-1:32])
addr+12'h80 : dst = 32'(src[$bits(src)-1:32])
`endif

1
hw/scripts/sv2v.sh
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@ -70,4 +70,5 @@ do
done
# system-verilog to verilog conversion
echo "sv2v $top $macro_args $inc_args $file_args -v -w $output_file"
sv2v $top $macro_args $inc_args $file_args -v -w $output_file

1
hw/syn/yosys/Makefile
View file

@ -80,6 +80,7 @@ gen-sources: $(BUILD_DIR)/sources.txt
$(BUILD_DIR)/sources.txt:
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt
sv2v: $(BUILD_DIR)/project.v
$(BUILD_DIR)/project.v: gen-sources
cd $(BUILD_DIR); $(SCRIPT_DIR)/sv2v.sh -t$(TOP_LEVEL_ENTITY) -Isrc -oproject.v