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fixed generate labels lint warnings to improve hardware debugging

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This commit is contained in:
Blaise Tine 2024-09-12 20:00:50 -07:00
parent 5c72685356
commit 6cf0d9f7b4
106 changed files with 939 additions and 901 deletions
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2
hw/rtl/VX_cluster.sv
View file

@ -128,7 +128,7 @@ module VX_cluster import VX_gpu_pkg::*; #(
`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1));
// Generate all sockets
for (genvar socket_id = 0; socket_id < `NUM_SOCKETS; ++socket_id) begin : sockets
for (genvar socket_id = 0; socket_id < `NUM_SOCKETS; ++socket_id) begin : g_sockets
`RESET_RELAY (socket_reset, reset);

19
hw/rtl/VX_define.vh
View file

@ -377,10 +377,13 @@
assign dst.req_data.data = src.req_data.data; \
assign dst.req_data.byteen = src.req_data.byteen; \
assign dst.req_data.flags = src.req_data.flags; \
if (TD != TS) \
/* verilator lint_off GENUNNAMED */ \
if (TD != TS) begin \
assign dst.req_data.tag = {src.req_data.tag, {(TD-TS){1'b0}}}; \
else \
end else begin \
assign dst.req_data.tag = src.req_data.tag; \
end \
/* verilator lint_on GENUNNAMED */ \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data.data = dst.rsp_data.data; \
@ -388,6 +391,7 @@
assign dst.rsp_ready = src.rsp_ready
`define BUFFER_DCR_BUS_IF(dst, src, enable) \
/* verilator lint_off GENUNNAMED */ \
if (enable) begin \
reg [(1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH)-1:0] __dst; \
always @(posedge clk) begin \
@ -396,9 +400,11 @@
assign {dst.write_valid, dst.write_addr, dst.write_data} = __dst; \
end else begin \
assign {dst.write_valid, dst.write_addr, dst.write_data} = {src.write_valid, src.write_addr, src.write_data}; \
end
end \
/* verilator lint_on GENUNNAMED */
`define PERF_COUNTER_ADD(dst, src, field, width, count, reg_enable) \
/* verilator lint_off GENUNNAMED */ \
if (count > 1) begin \
wire [count-1:0][width-1:0] __reduce_add_i_field; \
wire [width-1:0] __reduce_add_o_field; \
@ -424,9 +430,11 @@
end \
end else begin \
assign dst.``field = src[0].``field; \
end
end \
/* verilator lint_on GENUNNAMED */
`define ASSIGN_BLOCKED_WID(dst, src, block_idx, block_size) \
/* verilator lint_off GENUNNAMED */ \
if (block_size != 1) begin \
if (block_size != `NUM_WARPS) begin \
assign dst = {src[`NW_WIDTH-1:`CLOG2(block_size)], `CLOG2(block_size)'(block_idx)}; \
@ -435,6 +443,7 @@
end \
end else begin \
assign dst = src; \
end
end \
/* verilator lint_on GENUNNAMED */
`endif // VX_DEFINE_VH

11
hw/rtl/VX_platform.vh
View file

@ -116,15 +116,18 @@
localparam `STRING __``x = x; \
/* verilator lint_on UNUSED */
`define UNUSED_VAR(x) if (1) begin \
`define UNUSED_VAR(x) /* verilator lint_off GENUNNAMED */ \
if (1) begin \
/* verilator lint_off UNUSED */ \
wire [$bits(x)-1:0] __x = x; \
/* verilator lint_on UNUSED */ \
end
end \
/* verilator lint_on GENUNNAMED */
`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \
. x () \
/* verilator lint_on PINCONNECTEMPTY */
`define UNUSED_ARG(x) /* verilator lint_off UNUSED */ \
x \
/* verilator lint_on UNUSED */
@ -143,8 +146,10 @@
`ifdef SIMULATION
`define STATIC_ASSERT(cond, msg) \
generate \
generate \
/* verilator lint_off GENUNNAMED */ \
if (!(cond)) $error msg; \
/* verilator lint_on GENUNNAMED */ \
endgenerate
`define ERROR(msg) \

2
hw/rtl/VX_socket.sv
View file

@ -202,7 +202,7 @@ module VX_socket import VX_gpu_pkg::*; #(
`BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, (`SOCKET_SIZE > 1));
// Generate all cores
for (genvar core_id = 0; core_id < `SOCKET_SIZE; ++core_id) begin : cores
for (genvar core_id = 0; core_id < `SOCKET_SIZE; ++core_id) begin : g_cores
`RESET_RELAY (core_reset, reset);

2
hw/rtl/Vortex.sv
View file

@ -129,7 +129,7 @@ module Vortex import VX_gpu_pkg::*; (
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
// Generate all clusters
for (genvar cluster_id = 0; cluster_id < `NUM_CLUSTERS; ++cluster_id) begin : clusters
for (genvar cluster_id = 0; cluster_id < `NUM_CLUSTERS; ++cluster_id) begin : g_clusters
`RESET_RELAY (cluster_reset, reset);

2
hw/rtl/Vortex_axi.sv
View file

@ -110,7 +110,7 @@ module Vortex_axi import VX_gpu_pkg::*; #(
wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_bid_unqual [AXI_NUM_BANKS];
wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_rid_unqual [AXI_NUM_BANKS];
for (genvar i = 0; i < AXI_NUM_BANKS; ++i) begin
for (genvar i = 0; i < AXI_NUM_BANKS; ++i) begin : g_padding
assign m_axi_awaddr[i] = `MEM_ADDR_WIDTH'(m_axi_awaddr_unqual[i]);
assign m_axi_araddr[i] = `MEM_ADDR_WIDTH'(m_axi_araddr_unqual[i]);

2
hw/rtl/afu/xrt/VX_afu_ctrl.sv
View file

@ -235,7 +235,7 @@ module VX_afu_ctrl #(
assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready;
assign s_axi_w_fire = s_axi_wvalid && s_axi_wready;
for (genvar i = 0; i < 4; ++i) begin
for (genvar i = 0; i < 4; ++i) begin : g_wmask
assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}};
end

2
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -230,7 +230,7 @@ module VX_afu_wrap #(
wire [`MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_u [C_M_AXI_MEM_NUM_BANKS];
wire [`MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_u [C_M_AXI_MEM_NUM_BANKS];
for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_addressing
assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
end

4
hw/rtl/cache/VX_bank_flush.sv vendored
View file

@ -113,7 +113,7 @@ module VX_bank_flush #(
assign flush_valid = (state_r == STATE_FLUSH);
assign flush_line = counter_r[`CS_LINE_SEL_BITS-1:0];
if (WRITEBACK && `CS_WAY_SEL_BITS > 0) begin
if (WRITEBACK && `CS_WAY_SEL_BITS > 0) begin : g_flush_way
VX_decoder #(
.N (`CS_WAY_SEL_BITS)
) ctr_decoder (
@ -121,7 +121,7 @@ module VX_bank_flush #(
.valid_in (1'b1),
.data_out (flush_way)
);
end else begin
end else begin : g_flush_way_all
assign flush_way = {NUM_WAYS{1'b1}};
end

51
hw/rtl/cache/VX_cache.sv vendored
View file

@ -141,7 +141,7 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
wire [NUM_REQS-1:0] core_rsp_ready_s;
for (genvar i = 0; i < NUM_REQS; ++i) begin : core_rsp_bufs
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_buf
VX_elastic_buffer #(
.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
.SIZE (CORE_RSP_REG_DISABLE ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0),
@ -190,10 +190,10 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [BANK_MEM_TAG_WIDTH-1:0] bank_mem_rsp_tag;
wire [`UP(`CS_BANK_SEL_BITS)-1:0] mem_rsp_bank_id;
if (NUM_BANKS > 1) begin
if (NUM_BANKS > 1) begin : g_mem_rsp_tag_s_with_banks
assign bank_mem_rsp_tag = mem_rsp_tag_s[MEM_TAG_WIDTH-1:`CS_BANK_SEL_BITS];
assign mem_rsp_bank_id = mem_rsp_tag_s[`CS_BANK_SEL_BITS-1:0];
end else begin
end else begin : g_mem_rsp_tag_s_no_bank
assign bank_mem_rsp_tag = mem_rsp_tag_s;
assign mem_rsp_bank_id = 0;
end
@ -228,9 +228,9 @@ module VX_cache import VX_gpu_pkg::*; #(
assign mem_bus_tmp_if.req_data.flags = mem_req_flush_b ? `MEM_REQ_FLAGS_WIDTH'(1 << `MEM_REQ_FLAG_FLUSH) : '0;
if (WRITE_ENABLE) begin
if (WRITE_ENABLE) begin : g_mem_bus_if
`ASSIGN_VX_MEM_BUS_IF (mem_bus_if, mem_bus_tmp_if);
end else begin
end else begin : g_mem_bus_if_ro
`ASSIGN_VX_MEM_BUS_RO_IF (mem_bus_if, mem_bus_tmp_if);
end
@ -286,7 +286,7 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [NUM_REQS-1:0][CORE_REQ_DATAW-1:0] core_req_data_in;
wire [NUM_BANKS-1:0][CORE_REQ_DATAW-1:0] core_req_data_out;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req
assign core_req_valid[i] = core_bus2_if[i].req_valid;
assign core_req_rw[i] = core_bus2_if[i].req_data.rw;
assign core_req_byteen[i] = core_bus2_if[i].req_data.byteen;
@ -297,24 +297,27 @@ module VX_cache import VX_gpu_pkg::*; #(
assign core_bus2_if[i].req_ready = core_req_ready[i];
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (WORDS_PER_LINE > 1) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_wsel
if (WORDS_PER_LINE > 1) begin : g_wsel
assign core_req_wsel[i] = core_req_addr[i][0 +: WORD_SEL_BITS];
end else begin
end else begin : g_no_wsel
assign core_req_wsel[i] = '0;
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_line_addr
assign core_req_line_addr[i] = core_req_addr[i][(BANK_SEL_BITS + WORD_SEL_BITS) +: LINE_ADDR_WIDTH];
end
if (NUM_BANKS > 1) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_bid
if (NUM_BANKS > 1) begin : g_multibank
assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS];
end else begin : g_singlebank
assign core_req_bid[i] = '0;
end
end else begin
assign core_req_bid = '0;
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_data_in
assign core_req_data_in[i] = {
core_req_line_addr[i],
core_req_rw[i],
@ -355,7 +358,7 @@ module VX_cache import VX_gpu_pkg::*; #(
.ready_out (per_bank_core_req_ready)
);
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_core_req_data_out
assign {
per_bank_core_req_addr[i],
per_bank_core_req_rw[i],
@ -368,7 +371,7 @@ module VX_cache import VX_gpu_pkg::*; #(
end
// Banks access
for (genvar bank_id = 0; bank_id < NUM_BANKS; ++bank_id) begin : banks
for (genvar bank_id = 0; bank_id < NUM_BANKS; ++bank_id) begin : g_banks
wire [`CS_LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr;
wire curr_bank_mem_rsp_valid = mem_rsp_valid_s && (mem_rsp_bank_id == bank_id);
@ -443,9 +446,9 @@ module VX_cache import VX_gpu_pkg::*; #(
.flush_end (per_bank_flush_end[bank_id])
);
if (NUM_BANKS == 1) begin
if (NUM_BANKS == 1) begin : g_per_bank_mem_req_addr_multibanks
assign per_bank_mem_req_addr[bank_id] = curr_bank_mem_req_addr;
end else begin
end else begin : g_per_bank_mem_req_addr_one_bank
assign per_bank_mem_req_addr[bank_id] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, bank_id);
end
end
@ -455,7 +458,7 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [NUM_BANKS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_in;
wire [NUM_REQS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_out;
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_core_rsp_data_in
assign core_rsp_data_in[i] = {per_bank_core_rsp_data[i], per_bank_core_rsp_tag[i]};
end
@ -478,7 +481,7 @@ module VX_cache import VX_gpu_pkg::*; #(
`UNUSED_PIN (sel_out)
);
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_data_s
assign {core_rsp_data_s[i], core_rsp_tag_s[i]} = core_rsp_data_out[i];
end
@ -486,7 +489,7 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [NUM_BANKS-1:0][(`CS_MEM_ADDR_WIDTH + 1 + LINE_SIZE + `CS_LINE_WIDTH + BANK_MEM_TAG_WIDTH + 1)-1:0] data_in;
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_data_in
assign data_in[i] = {
per_bank_mem_req_addr[i],
per_bank_mem_req_rw[i],
@ -515,10 +518,10 @@ module VX_cache import VX_gpu_pkg::*; #(
`UNUSED_PIN (sel_out)
);
if (NUM_BANKS > 1) begin
if (NUM_BANKS > 1) begin : g_mem_req_tag_multibanks
wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id = `CS_MEM_ADDR_TO_BANK_ID(mem_req_addr);
assign mem_req_tag = MEM_TAG_WIDTH'({bank_mem_req_tag, mem_req_bank_id});
end else begin
end else begin : g_mem_req_tag_one_bank
assign mem_req_tag = MEM_TAG_WIDTH'(bank_mem_req_tag);
end
@ -546,7 +549,7 @@ module VX_cache import VX_gpu_pkg::*; #(
`POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank);
wire [NUM_REQS-1:0] perf_crsp_stall_per_req;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_perf_crsp_stall_per_req
assign perf_crsp_stall_per_req[i] = core_bus2_if[i].rsp_valid && ~core_bus2_if[i].rsp_ready;
end

55
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -246,17 +246,17 @@ module VX_cache_bank #(
wire [MSHR_ADDR_WIDTH-1:0] mem_rsp_id = mem_rsp_tag[MSHR_ADDR_WIDTH-1:0];
wire [TAG_WIDTH-1:0] mem_rsp_tag_s;
if (TAG_WIDTH > MEM_TAG_WIDTH) begin
if (TAG_WIDTH > MEM_TAG_WIDTH) begin : g_mem_rsp_tag_s_pad
assign mem_rsp_tag_s = {mem_rsp_tag, (TAG_WIDTH-MEM_TAG_WIDTH)'(1'b0)};
end else begin
end else begin : g_mem_rsp_tag_s_cut
assign mem_rsp_tag_s = mem_rsp_tag[MEM_TAG_WIDTH-1 -: TAG_WIDTH];
`UNUSED_VAR (mem_rsp_tag)
end
wire [TAG_WIDTH-1:0] flush_tag;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_flush_tag_uuid
assign flush_tag = {flush_uuid, (TAG_WIDTH-UUID_WIDTH)'(1'b0)};
end else begin
end else begin : g_flush_tag_0
`UNUSED_VAR (flush_uuid)
assign flush_tag = '0;
end
@ -273,20 +273,21 @@ module VX_cache_bank #(
assign addr_sel = (init_valid | flush_valid) ? `CS_LINE_ADDR_WIDTH'(flush_sel) :
(replay_valid ? replay_addr : (mem_rsp_valid ? mem_rsp_addr : core_req_addr));
if (WRITE_ENABLE) begin
if (WRITE_ENABLE) begin : g_data_sel
assign data_sel[`CS_WORD_WIDTH-1:0] = replay_valid ? replay_data : (mem_rsp_valid ? mem_rsp_data[`CS_WORD_WIDTH-1:0] : core_req_data);
end else begin
end else begin : g_data_sel_ro
assign data_sel[`CS_WORD_WIDTH-1:0] = mem_rsp_data[`CS_WORD_WIDTH-1:0];
`UNUSED_VAR (core_req_data)
`UNUSED_VAR (replay_data)
end
for (genvar i = `CS_WORD_WIDTH; i < `CS_LINE_WIDTH; ++i) begin
for (genvar i = `CS_WORD_WIDTH; i < `CS_LINE_WIDTH; ++i) begin : g_data_sel
assign data_sel[i] = mem_rsp_data[i]; // only the memory response fills the upper words of data_sel
end
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_req_uuid_sel
assign req_uuid_sel = tag_sel[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_req_uuid_sel_0
assign req_uuid_sel = '0;
end
@ -301,9 +302,9 @@ module VX_cache_bank #(
.data_out ({valid_st0, is_init_st0, is_replay_st0, is_fill_st0, is_flush_st0, is_creq_st0, creq_flush_st0, flush_way_st0, addr_st0, data_st0, rw_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, replay_id_st0})
);
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_req_uuid_st0
assign req_uuid_st0 = tag_st0[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_req_uuid_st0_0
assign req_uuid_st0 = '0;
end
@ -383,9 +384,9 @@ module VX_cache_bank #(
// we have a tag hit
wire is_hit_st1 = (| way_sel_st1);
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_req_uuid_st1
assign req_uuid_st1 = tag_st1[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_req_uuid_st1_0
assign req_uuid_st1 = '0;
end
@ -434,14 +435,14 @@ module VX_cache_bank #(
wire [`CS_LINE_WIDTH-1:0] dirty_data_st1;
wire [LINE_SIZE-1:0] dirty_byteen_st1;
if (`CS_WORDS_PER_LINE > 1) begin
if (`CS_WORDS_PER_LINE > 1) begin : g_write_byteen_st1_wsel
reg [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_byteen_w;
always @(*) begin
write_byteen_w = '0;
write_byteen_w[wsel_st1] = byteen_st1;
end
assign write_byteen_st1 = write_byteen_w;
end else begin
end else begin : g_write_byteen_st1
assign write_byteen_st1 = byteen_st1;
end
@ -489,9 +490,9 @@ module VX_cache_bank #(
// release allocated mshr entry if we had a hit
wire mshr_release_st1;
if (WRITEBACK) begin
if (WRITEBACK) begin : g_mshr_release_st1
assign mshr_release_st1 = is_hit_st1;
end else begin
end else begin : g_mshr_release_st1_ro
// we need to keep missed write requests in MSHR if there is already a pending entry to the same address
// this ensures that missed write requests are replayed locally in case a pending fill arrives without the write content
// this can happen when writes are sent late, when the fill was already in flight.
@ -566,7 +567,7 @@ module VX_cache_bank #(
// check if there are pending requests to same line in the MSHR
wire [MSHR_SIZE-1:0] lookup_matches;
for (genvar i = 0; i < MSHR_SIZE; ++i) begin
for (genvar i = 0; i < MSHR_SIZE; ++i) begin : g_lookup_matches
assign lookup_matches[i] = mshr_lookup_pending_st0[i]
&& (i != mshr_alloc_id_st0) // exclude current mshr id
&& (WRITEBACK || ~mshr_lookup_rw_st0[i]); // exclude write requests if writethrough
@ -616,8 +617,8 @@ module VX_cache_bank #(
wire do_fill_or_flush_st1 = valid_st1 && is_fill_or_flush_st1;
wire do_writeback_st1 = do_fill_or_flush_st1 && evict_dirty_st1;
if (WRITEBACK) begin
if (DIRTY_BYTES) begin
if (WRITEBACK) begin : g_mreq_queue_push
if (DIRTY_BYTES) begin : g_dirty_bytes
// ensure dirty bytes match the tag info
wire has_dirty_bytes = (| dirty_byteen_st1);
`RUNTIME_ASSERT (~do_fill_or_flush_st1 || (evict_dirty_st1 == has_dirty_bytes), ("%t: missmatch dirty bytes: dirty_line=%b, dirty_bytes=%b, addr=0x%0h", $time, evict_dirty_st1, has_dirty_bytes, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID)))
@ -625,7 +626,7 @@ module VX_cache_bank #(
assign mreq_queue_push = (((do_read_miss_st1 || do_write_miss_st1) && ~mshr_pending_st1)
|| do_writeback_st1)
&& ~rdw_hazard3_st1;
end else begin
end else begin : g_mreq_queue_push_ro
`UNUSED_VAR (do_writeback_st1)
assign mreq_queue_push = ((do_read_miss_st1 && ~mshr_pending_st1)
|| do_creq_wr_st1)
@ -636,12 +637,12 @@ module VX_cache_bank #(
assign mreq_queue_addr = addr_st1;
assign mreq_queue_flush = creq_flush_st1;
if (WRITE_ENABLE) begin
if (WRITEBACK) begin
if (WRITE_ENABLE) begin : g_mreq_queue
if (WRITEBACK) begin : g_writeback
assign mreq_queue_rw = is_fill_or_flush_st1;
assign mreq_queue_data = dirty_data_st1;
assign mreq_queue_byteen = is_fill_or_flush_st1 ? dirty_byteen_st1 : '1;
end else begin
end else begin : g_writethrough
assign mreq_queue_rw = rw_st1;
assign mreq_queue_data = write_data_st1;
assign mreq_queue_byteen = rw_st1 ? write_byteen_st1 : '1;
@ -649,7 +650,7 @@ module VX_cache_bank #(
`UNUSED_VAR (dirty_data_st1)
`UNUSED_VAR (dirty_byteen_st1)
end
end else begin
end else begin : g_mreq_queue_ro
assign mreq_queue_rw = 0;
assign mreq_queue_data = '0;
assign mreq_queue_byteen = '1;
@ -657,9 +658,9 @@ module VX_cache_bank #(
`UNUSED_VAR (dirty_byteen_st1)
end
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_mreq_queue_tag_uuid
assign mreq_queue_tag = {req_uuid_st1, mshr_id_st1};
end else begin
end else begin : g_mreq_queue_tag
assign mreq_queue_tag = mshr_id_st1;
end

108
hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -77,12 +77,12 @@ module VX_cache_bypass #(
wire [NUM_REQS-1:0] core_req_nc_sel;
wire core_req_nc_ready;
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (PASSTHRU != 0) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_nc
if (PASSTHRU != 0) begin : g_passthru
assign core_req_nc_idxs[i] = 1'b1;
end else if (NC_ENABLE) begin
end else if (NC_ENABLE) begin : g_nc
assign core_req_nc_idxs[i] = core_bus_in_if[i].req_data.flags[`MEM_REQ_FLAG_IO];
end else begin
end else begin : g_no_nc
assign core_req_nc_idxs[i] = 1'b0;
end
assign core_req_nc_valids[i] = core_bus_in_if[i].req_valid && core_req_nc_idxs[i];
@ -101,7 +101,7 @@ module VX_cache_bypass #(
.grant_ready (core_req_nc_ready)
);
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_if
assign core_bus_out_if[i].req_valid = core_bus_in_if[i].req_valid && ~core_req_nc_idxs[i];
assign core_bus_out_if[i].req_data = core_bus_in_if[i].req_data;
assign core_bus_in_if[i].req_ready = core_req_nc_valids[i] ? (core_req_nc_ready && core_req_nc_sel[i])
@ -127,7 +127,7 @@ module VX_cache_bypass #(
wire [CORE_TAG_WIDTH-1:0] core_req_nc_sel_tag;
wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_nc_mux_in
assign core_req_nc_mux_in[i] = {
core_bus_in_if[i].req_data.rw,
core_bus_in_if[i].req_data.addr,
@ -158,7 +158,7 @@ module VX_cache_bypass #(
wire [CORE_TAG_ID_BITS-1:0] core_req_in_id = core_req_nc_sel_tag[CORE_TAG_ID_BITS-1:0];
if (WORDS_PER_LINE > 1) begin
if (WORDS_PER_LINE > 1) begin : g_mem_req_multi_word_line
reg [WORDS_PER_LINE-1:0][WORD_SIZE-1:0] mem_req_byteen_in_w;
reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_w;
@ -174,46 +174,44 @@ module VX_cache_bypass #(
assign mem_req_out_byteen = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.byteen : mem_req_byteen_in_w;
assign mem_req_out_data = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.data : mem_req_data_in_w;
if (NUM_REQS > 1) begin
if (NUM_REQS > 1) begin : g_multiple_requests
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, req_wsel, core_req_in_id});
end else begin
end else begin : g_single_request
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({req_wsel, core_req_in_id});
end
end else begin
end else begin : g_mem_req_single_word_line
assign mem_req_out_byteen = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.byteen : core_req_nc_sel_byteen;
assign mem_req_out_data = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.data : core_req_nc_sel_data;
if (NUM_REQS > 1) begin
if (NUM_REQS > 1) begin : g_multiple_requests
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, core_req_in_id});
end else begin
end else begin : g_single_request
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_in_id});
end
end
wire [MEM_TAG_BYPASS_BITS-1:0] mem_req_tag_bypass;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_mem_req_tag_bypass_with_uuid
assign mem_req_tag_bypass = {core_req_nc_sel_tag[CORE_TAG_ID_BITS +: UUID_WIDTH], mem_req_tag_id_bypass};
end else begin
end else begin : g_mem_req_tag_bypass
assign mem_req_tag_bypass = mem_req_tag_id_bypass;
end
if (PASSTHRU != 0) begin
if (PASSTHRU != 0) begin : g_mem_req_out_tag_passthru
assign mem_req_out_tag = mem_req_tag_bypass;
`UNUSED_VAR (mem_bus_in_if.req_data.tag)
end else begin
if (NC_ENABLE) begin
VX_bits_insert #(
.N (MEM_TAG_OUT_WIDTH-1),
.S (1),
.POS (TAG_SEL_IDX)
) mem_req_tag_in_nc_insert (
.data_in (mem_bus_in_if.req_valid ? (MEM_TAG_OUT_WIDTH-1)'(mem_bus_in_if.req_data.tag) : (MEM_TAG_OUT_WIDTH-1)'(mem_req_tag_bypass)),
.ins_in (~mem_bus_in_if.req_valid),
.data_out (mem_req_out_tag)
);
end else begin
assign mem_req_out_tag = mem_bus_in_if.req_data.tag;
end
end else if (NC_ENABLE) begin : g_mem_req_out_tag_nc
VX_bits_insert #(
.N (MEM_TAG_OUT_WIDTH-1),
.S (1),
.POS (TAG_SEL_IDX)
) mem_req_tag_in_nc_insert (
.data_in (mem_bus_in_if.req_valid ? (MEM_TAG_OUT_WIDTH-1)'(mem_bus_in_if.req_data.tag) : (MEM_TAG_OUT_WIDTH-1)'(mem_req_tag_bypass)),
.ins_in (~mem_bus_in_if.req_valid),
.data_out (mem_req_out_tag)
);
end else begin : g_mem_req_out_tag
assign mem_req_out_tag = mem_bus_in_if.req_data.tag;
end
assign mem_bus_in_if.req_ready = mem_req_out_ready;
@ -241,14 +239,12 @@ module VX_cache_bypass #(
wire [NUM_REQS-1:0] core_rsp_in_ready;
wire is_mem_rsp_nc;
if (PASSTHRU != 0) begin
if (PASSTHRU != 0) begin : g_is_mem_rsp_nc_passthru
assign is_mem_rsp_nc = mem_bus_out_if.rsp_valid;
end else begin
if (NC_ENABLE) begin
assign is_mem_rsp_nc = mem_bus_out_if.rsp_valid && mem_bus_out_if.rsp_data.tag[TAG_SEL_IDX];
end else begin
assign is_mem_rsp_nc = 1'b0;
end
end else if (NC_ENABLE) begin : g_is_mem_rsp_nc
assign is_mem_rsp_nc = mem_bus_out_if.rsp_valid && mem_bus_out_if.rsp_data.tag[TAG_SEL_IDX];
end else begin : g_is_no_mem_rsp_nc
assign is_mem_rsp_nc = 1'b0;
end
wire [(MEM_TAG_OUT_WIDTH - NC_ENABLE)-1:0] mem_rsp_tag_id_nc;
@ -263,47 +259,47 @@ module VX_cache_bypass #(
);
wire [REQ_SEL_WIDTH-1:0] rsp_idx;
if (NUM_REQS > 1) begin
if (NUM_REQS > 1) begin : g_rsp_idx
assign rsp_idx = mem_rsp_tag_id_nc[(CORE_TAG_ID_BITS + WSEL_BITS) +: REQ_SEL_BITS];
end else begin
end else begin : g_rsp_idx_0
assign rsp_idx = 1'b0;
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_in_valid
assign core_rsp_in_valid[i] = core_bus_out_if[i].rsp_valid || (is_mem_rsp_nc && rsp_idx == REQ_SEL_WIDTH'(i));
end
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_in_ready
assign core_bus_out_if[i].rsp_ready = core_rsp_in_ready[i];
end
if (WORDS_PER_LINE > 1) begin
wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_id_nc[CORE_TAG_ID_BITS +: WSEL_BITS];
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_in_data
if (WORDS_PER_LINE > 1) begin : g_wsel
wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_id_nc[CORE_TAG_ID_BITS +: WSEL_BITS];
assign core_rsp_in_data[i] = core_bus_out_if[i].rsp_valid ?
core_bus_out_if[i].rsp_data.data : mem_bus_out_if.rsp_data.data[rsp_wsel * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
end
end else begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
end else begin : g_no_wsel
assign core_rsp_in_data[i] = core_bus_out_if[i].rsp_valid ? core_bus_out_if[i].rsp_data.data : mem_bus_out_if.rsp_data.data;
end
end
wire [(CORE_TAG_ID_BITS + UUID_WIDTH)-1:0] mem_rsp_tag_in_nc2;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_mem_rsp_tag_in_nc2_uuid
assign mem_rsp_tag_in_nc2 = {mem_rsp_tag_id_nc[(MEM_TAG_OUT_WIDTH - NC_ENABLE)-1 -: UUID_WIDTH], mem_rsp_tag_id_nc[CORE_TAG_ID_BITS-1:0]};
end else begin
end else begin : g_mem_rsp_tag_in_nc2
assign mem_rsp_tag_in_nc2 = mem_rsp_tag_id_nc[CORE_TAG_ID_BITS-1:0];
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (PASSTHRU) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_in_tag
if (PASSTHRU) begin : g_passthru
assign core_rsp_in_tag[i] = mem_rsp_tag_in_nc2;
end else if (NC_ENABLE) begin
end else if (NC_ENABLE) begin : g_nc
assign core_rsp_in_tag[i] = core_bus_out_if[i].rsp_valid ? core_bus_out_if[i].rsp_data.tag : mem_rsp_tag_in_nc2;
end else begin
end else begin : g_no_nc
assign core_rsp_in_tag[i] = core_bus_out_if[i].rsp_data.tag;
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_buf
VX_elastic_buffer #(
.DATAW (`CS_WORD_WIDTH + CORE_TAG_WIDTH),
.SIZE (DIRECT_PASSTHRU ? 0 : `TO_OUT_BUF_SIZE(CORE_OUT_BUF)),
@ -322,22 +318,22 @@ module VX_cache_bypass #(
// handle memory responses ////////////////////////////////////////////////
if (PASSTHRU != 0) begin
if (PASSTHRU != 0) begin : g_mem_bus_in_if_passthru
assign mem_bus_in_if.rsp_valid = 1'b0;
assign mem_bus_in_if.rsp_data.data = '0;
assign mem_bus_in_if.rsp_data.tag = '0;
end else if (NC_ENABLE) begin
end else if (NC_ENABLE) begin : g_mem_bus_in_if_nc
assign mem_bus_in_if.rsp_valid = mem_bus_out_if.rsp_valid && ~mem_bus_out_if.rsp_data.tag[TAG_SEL_IDX];
assign mem_bus_in_if.rsp_data.data = mem_bus_out_if.rsp_data.data;
assign mem_bus_in_if.rsp_data.tag = mem_rsp_tag_id_nc[MEM_TAG_IN_WIDTH-1:0];
end else begin
end else begin : g_mem_bus_in_if
assign mem_bus_in_if.rsp_valid = mem_bus_out_if.rsp_valid;
assign mem_bus_in_if.rsp_data.data = mem_bus_out_if.rsp_data.data;
assign mem_bus_in_if.rsp_data.tag = mem_rsp_tag_id_nc;
end
wire [NUM_REQS-1:0] core_rsp_out_valid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_out_valid
assign core_rsp_out_valid[i] = core_bus_out_if[i].rsp_valid;
end

12
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -102,7 +102,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_bus_if[NUM_CACHES * NUM_REQS]();
for (genvar i = 0; i < NUM_REQS; ++i) begin : core_arbs
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_arb
VX_mem_bus_if #(
.DATA_SIZE (WORD_SIZE),
.TAG_WIDTH (TAG_WIDTH)
@ -113,7 +113,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_bus_tmp_if[NUM_CACHES]();
for (genvar j = 0; j < NUM_INPUTS; ++j) begin
for (genvar j = 0; j < NUM_INPUTS; ++j) begin : g_core_bus_tmp_if
`ASSIGN_VX_MEM_BUS_IF (core_bus_tmp_if[j], core_bus_if[j * NUM_REQS + i]);
end
@ -133,12 +133,12 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.bus_out_if (arb_core_bus_tmp_if)
);
for (genvar k = 0; k < NUM_CACHES; ++k) begin
for (genvar k = 0; k < NUM_CACHES; ++k) begin : g_arb_core_bus_if
`ASSIGN_VX_MEM_BUS_IF (arb_core_bus_if[k * NUM_REQS + i], arb_core_bus_tmp_if[k]);
end
end
for (genvar i = 0; i < NUM_CACHES; ++i) begin : caches
for (genvar i = 0; i < NUM_CACHES; ++i) begin : g_cache_wrap
VX_cache_wrap #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, i)),
.CACHE_SIZE (CACHE_SIZE),
@ -192,9 +192,9 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.bus_out_if (mem_bus_tmp_if)
);
if (WRITE_ENABLE) begin
if (WRITE_ENABLE) begin : g_mem_bus_if
`ASSIGN_VX_MEM_BUS_IF (mem_bus_if, mem_bus_tmp_if[0]);
end else begin
end else begin : g_mem_bus_if_ro
`ASSIGN_VX_MEM_BUS_RO_IF (mem_bus_if, mem_bus_tmp_if[0]);
end

77
hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -75,64 +75,63 @@ module VX_cache_data #(
wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] line_rdata;
wire [`LOG2UP(NUM_WAYS)-1:0] way_idx;
if (WRITEBACK) begin : dirty_bytes
if (DIRTY_BYTES) begin
wire [NUM_WAYS-1:0][LINE_SIZE-1:0] bs_rdata;
wire [NUM_WAYS-1:0][LINE_SIZE-1:0] bs_wdata;
for (genvar i = 0; i < NUM_WAYS; ++i) begin
wire [LINE_SIZE-1:0] wdata = write ? (bs_rdata[i] | write_byteen) : ((fill || flush) ? '0 : bs_rdata[i]);
assign bs_wdata[i] = init ? '0 : (way_sel[i] ? wdata : bs_rdata[i]);
end
VX_sp_ram #(
.DATAW (LINE_SIZE * NUM_WAYS),
.SIZE (`CS_LINES_PER_BANK)
) byteen_store (
.clk (clk),
.reset (reset),
.read (write || fill || flush),
.write (init || write || fill || flush),
.wren (1'b1),
.addr (line_sel),
.wdata (bs_wdata),
.rdata (bs_rdata)
);
assign dirty_byteen = bs_rdata[way_idx];
end else begin
assign dirty_byteen = '1;
end
if (WRITEBACK) begin : g_dirty_data
wire [NUM_WAYS-1:0][`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] flipped_rdata;
for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin
for (genvar j = 0; j < NUM_WAYS; ++j) begin
for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin : g_flipped_rdata
for (genvar j = 0; j < NUM_WAYS; ++j) begin : g_j
assign flipped_rdata[j][i] = line_rdata[i][j];
end
end
assign dirty_data = flipped_rdata[way_idx];
end else begin
assign dirty_byteen = '1;
end else begin : g_dirty_data_0
assign dirty_data = '0;
end
if (DIRTY_BYTES) begin : g_dirty_byteen
wire [NUM_WAYS-1:0][LINE_SIZE-1:0] bs_rdata;
wire [NUM_WAYS-1:0][LINE_SIZE-1:0] bs_wdata;
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_bs_wdata
wire [LINE_SIZE-1:0] wdata = write ? (bs_rdata[i] | write_byteen) : ((fill || flush) ? '0 : bs_rdata[i]);
assign bs_wdata[i] = init ? '0 : (way_sel[i] ? wdata : bs_rdata[i]);
end
VX_sp_ram #(
.DATAW (LINE_SIZE * NUM_WAYS),
.SIZE (`CS_LINES_PER_BANK)
) byteen_store (
.clk (clk),
.reset (reset),
.read (write || fill || flush),
.write (init || write || fill || flush),
.wren (1'b1),
.addr (line_sel),
.wdata (bs_wdata),
.rdata (bs_rdata)
);
assign dirty_byteen = bs_rdata[way_idx];
end else begin : g_dirty_byteen_0
assign dirty_byteen = '1;
end
// order the data layout to perform ways multiplexing last.
// this allows converting way index to binary in parallel with BRAM readaccess and way selection.
wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] line_wdata;
wire [BYTEENW-1:0] line_wren;
if (WRITE_ENABLE != 0 || (NUM_WAYS > 1)) begin
if (WRITE_ENABLE != 0 || (NUM_WAYS > 1)) begin : g_line_wdata
wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][WORD_SIZE-1:0] wren_w;
for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin
for (genvar j = 0; j < NUM_WAYS; ++j) begin
for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin : g_i
for (genvar j = 0; j < NUM_WAYS; ++j) begin : g_j
assign line_wdata[i][j] = (fill || !WRITE_ENABLE) ? fill_data[i] : write_data[i];
assign wren_w[i][j] = ((fill || !WRITE_ENABLE) ? {WORD_SIZE{1'b1}} : write_byteen[i])
& {WORD_SIZE{(way_sel[j] || (NUM_WAYS == 1))}};
end
end
assign line_wren = wren_w;
end else begin
end else begin : g_line_wdata_ro
`UNUSED_VAR (write)
`UNUSED_VAR (write_byteen)
`UNUSED_VAR (write_data)
@ -171,9 +170,9 @@ module VX_cache_data #(
);
wire [NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] per_way_rdata;
if (`CS_WORDS_PER_LINE > 1) begin
if (`CS_WORDS_PER_LINE > 1) begin : g_per_way_rdata_wsel
assign per_way_rdata = line_rdata[wsel];
end else begin
end else begin : g_per_way_rdata
`UNUSED_VAR (wsel)
assign per_way_rdata = line_rdata;
end

21
hw/rtl/cache/VX_cache_flush.sv vendored
View file

@ -46,13 +46,13 @@ module VX_cache_flush #(
wire no_inflight_reqs;
if (BANK_SEL_LATENCY != 0) begin
if (BANK_SEL_LATENCY != 0) begin : g_bank_sel_latency
localparam NUM_REQS_W = `CLOG2(NUM_REQS+1);
localparam NUM_BANKS_W = `CLOG2(NUM_BANKS+1);
wire [NUM_REQS-1:0] core_bus_out_fire;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_fire
assign core_bus_out_fire[i] = core_bus_out_if[i].req_valid && core_bus_out_if[i].req_ready;
end
@ -79,7 +79,7 @@ module VX_cache_flush #(
`UNUSED_PIN (size)
);
end else begin
end else begin : g_no_bank_sel_latency
assign no_inflight_reqs = 0;
`UNUSED_VAR (bank_req_fire)
end
@ -87,7 +87,7 @@ module VX_cache_flush #(
reg [NUM_BANKS-1:0] flush_done, flush_done_n;
wire [NUM_REQS-1:0] flush_req_mask;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_flush_req_mask
assign flush_req_mask[i] = core_bus_in_if[i].req_valid && core_bus_in_if[i].req_data.flags[`MEM_REQ_FLAG_FLUSH];
end
wire flush_req_enable = (| flush_req_mask);
@ -95,14 +95,14 @@ module VX_cache_flush #(
reg [NUM_REQS-1:0] lock_released, lock_released_n;
reg [`UP(UUID_WIDTH)-1:0] flush_uuid_r, flush_uuid_n;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_req
wire input_enable = ~flush_req_enable || lock_released[i];
assign core_bus_out_if[i].req_valid = core_bus_in_if[i].req_valid && input_enable;
assign core_bus_out_if[i].req_data = core_bus_in_if[i].req_data;
assign core_bus_in_if[i].req_ready = core_bus_out_if[i].req_ready && input_enable;
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_in_rsp
assign core_bus_in_if[i].rsp_valid = core_bus_out_if[i].rsp_valid;
assign core_bus_in_if[i].rsp_data = core_bus_out_if[i].rsp_data;
assign core_bus_out_if[i].rsp_ready = core_bus_in_if[i].rsp_ready;
@ -110,12 +110,15 @@ module VX_cache_flush #(
reg [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] core_bus_out_uuid;
wire [NUM_REQS-1:0] core_bus_out_ready;
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (UUID_WIDTH != 0) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_uuid
if (UUID_WIDTH != 0) begin : g_uuid
assign core_bus_out_uuid[i] = core_bus_in_if[i].req_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_no_uuid
assign core_bus_out_uuid[i] = 0;
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_ready
assign core_bus_out_ready[i] = core_bus_out_if[i].req_ready;
end

2
hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -135,7 +135,7 @@ module VX_cache_mshr #(
wire dequeue_fire = dequeue_valid && dequeue_ready;
wire [MSHR_SIZE-1:0] addr_matches;
for (genvar i = 0; i < MSHR_SIZE; ++i) begin
for (genvar i = 0; i < MSHR_SIZE; ++i) begin : g_addr_matches
assign addr_matches[i] = valid_table[i] && (addr_table[i] == lookup_addr);
end

12
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -69,7 +69,7 @@ module VX_cache_tags #(
wire [NUM_WAYS-1:0] read_valid;
wire [NUM_WAYS-1:0] read_dirty;
if (NUM_WAYS > 1) begin
if (NUM_WAYS > 1) begin : g_evict_way
reg [NUM_WAYS-1:0] evict_way_r;
// cyclic assignment of replacement way
always @(posedge clk) begin
@ -90,7 +90,7 @@ module VX_cache_tags #(
.sel_in (evict_way),
.data_out (evict_tag)
);
end else begin
end else begin : g_evict_way_0
`UNUSED_VAR (stall)
assign evict_way = 1'b1;
assign evict_tag = read_tag;
@ -100,7 +100,7 @@ module VX_cache_tags #(
wire fill_s = fill && (!WRITEBACK || ~stall);
wire flush_s = flush && (!WRITEBACK || ~stall);
for (genvar i = 0; i < NUM_WAYS; ++i) begin : tag_stores
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_tag_store
wire do_fill = fill_s && evict_way[i];
wire do_flush = flush_s && (!WRITEBACK || way_sel[i]); // flush the whole line in writethrough mode
@ -113,10 +113,10 @@ module VX_cache_tags #(
wire [TAG_WIDTH-1:0] line_wdata;
wire [TAG_WIDTH-1:0] line_rdata;
if (WRITEBACK) begin
if (WRITEBACK) begin : g_writeback
assign line_wdata = {line_valid, write, line_tag};
assign {read_valid[i], read_dirty[i], read_tag[i]} = line_rdata;
end else begin
end else begin : g_writethrough
assign line_wdata = {line_valid, line_tag};
assign {read_valid[i], read_tag[i]} = line_rdata;
assign read_dirty[i] = 1'b0;
@ -139,7 +139,7 @@ module VX_cache_tags #(
);
end
for (genvar i = 0; i < NUM_WAYS; ++i) begin
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_tag_matches
assign tag_matches[i] = read_valid[i] && (line_tag == read_tag[i]);
end

27
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -107,7 +107,7 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.TAG_WIDTH (MEM_TAG_WIDTH)
) mem_bus_tmp_if();
if (NC_OR_BYPASS) begin : bypass_if
if (NC_OR_BYPASS) begin : g_bypass
VX_cache_bypass #(
.NUM_REQS (NUM_REQS),
@ -141,22 +141,22 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.mem_bus_out_if (mem_bus_tmp_if)
);
end else begin
end else begin : g_no_bypass
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_cache_if
`ASSIGN_VX_MEM_BUS_IF (core_bus_cache_if[i], core_bus_if[i]);
end
`ASSIGN_VX_MEM_BUS_IF (mem_bus_tmp_if, mem_bus_cache_if);
end
if (WRITE_ENABLE) begin
if (WRITE_ENABLE) begin : g_mem_bus_if
`ASSIGN_VX_MEM_BUS_IF (mem_bus_if, mem_bus_tmp_if);
end else begin
end else begin : g_mem_bus_if_ro
`ASSIGN_VX_MEM_BUS_RO_IF (mem_bus_if, mem_bus_tmp_if);
end
if (PASSTHRU == 0) begin : cache_if
if (PASSTHRU == 0) begin : g_cache
VX_cache #(
.INSTANCE_ID (INSTANCE_ID),
@ -187,9 +187,9 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.mem_bus_if (mem_bus_cache_if)
);
end else begin
end else begin : g_passthru
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_cache_if
`UNUSED_VAR (core_bus_cache_if[i].req_valid)
`UNUSED_VAR (core_bus_cache_if[i].req_data)
assign core_bus_cache_if[i].req_ready = 0;
@ -214,15 +214,14 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
end
`ifdef DBG_TRACE_CACHE
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_trace
wire [`UP(UUID_WIDTH)-1:0] core_req_uuid;
wire [`UP(UUID_WIDTH)-1:0] core_rsp_uuid;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_core_rsp_uuid
assign core_req_uuid = core_bus_if[i].req_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
assign core_rsp_uuid = core_bus_if[i].rsp_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_no_core_rsp_uuid
assign core_req_uuid = 0;
assign core_rsp_uuid = 0;
end
@ -247,10 +246,10 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
wire [`UP(UUID_WIDTH)-1:0] mem_req_uuid;
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_uuid;
if ((UUID_WIDTH != 0) && (NC_OR_BYPASS != 0)) begin
if ((UUID_WIDTH != 0) && (NC_OR_BYPASS != 0)) begin : g_mem_req_uuid
assign mem_req_uuid = mem_bus_if.req_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
assign mem_rsp_uuid = mem_bus_if.rsp_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_no_mem_req_uuid
assign mem_req_uuid = 0;
assign mem_rsp_uuid = 0;
end

16
hw/rtl/core/VX_alu_int.sv
View file

@ -71,19 +71,19 @@ module VX_alu_int #(
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_imm = execute_if.data.op_args.alu.use_imm ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_args.alu.imm)}} : alu_in2;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_br = (execute_if.data.op_args.alu.use_imm && ~is_br_op) ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_args.alu.imm)}} : alu_in2;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_add_result
assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];
assign add_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] + alu_in2_imm[i][31:0]));
end
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_sub_result
wire [`XLEN:0] sub_in1 = {is_signed & alu_in1[i][`XLEN-1], alu_in1[i]};
wire [`XLEN:0] sub_in2 = {is_signed & alu_in2_br[i][`XLEN-1], alu_in2_br[i]};
assign sub_result[i] = sub_in1 - sub_in2;
assign sub_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] - alu_in2_imm[i][31:0]));
end
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_shr_result
wire [`XLEN:0] shr_in1 = {is_signed && alu_in1[i][`XLEN-1], alu_in1[i]};
always @(*) begin
case (alu_op[1:0])
@ -102,7 +102,7 @@ module VX_alu_int #(
assign shr_result_w[i] = `XLEN'($signed(shr_res_w));
end
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_msc_result
always @(*) begin
case (alu_op[1:0])
2'b00: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; // AND
@ -114,7 +114,7 @@ module VX_alu_int #(
assign msc_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] << alu_in2_imm[i][4:0])); // SLLW
end
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_alu_result
wire [`XLEN-1:0] slt_br_result = `XLEN'({is_br_op && ~(| sub_result[i][`XLEN-1:0]), sub_result[i][`XLEN]});
wire [`XLEN-1:0] sub_slt_br_result = (is_sub_op && ~is_br_op) ? sub_result[i][`XLEN-1:0] : slt_br_result;
always @(*) begin
@ -141,9 +141,9 @@ module VX_alu_int #(
assign cbr_dest = add_result[0][1 +: `PC_BITS];
if (LANE_BITS != 0) begin
if (LANE_BITS != 0) begin : g_tid
assign tid = execute_if.data.tid[0 +: LANE_BITS];
end else begin
end else begin : g_tid_0
assign tid = 0;
end
@ -185,7 +185,7 @@ module VX_alu_int #(
.data_out ({branch_ctl_if.valid, branch_ctl_if.wid, branch_ctl_if.taken, branch_ctl_if.dest})
);
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_commit
assign commit_if.data.data[i] = (is_br_op_r && is_br_static) ? {(PC_r + `PC_BITS'(2)), 1'd0} : alu_result_r[i];
end

14
hw/rtl/core/VX_alu_muldiv.sv
View file

@ -68,7 +68,7 @@ module VX_alu_muldiv #(
wire mul_fire_in = mul_valid_in && mul_ready_in;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mul_result_tmp
reg [`XLEN-1:0] mul_resultl, mul_resulth;
wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i];
wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i];
@ -103,7 +103,7 @@ module VX_alu_muldiv #(
wire [NUM_LANES-1:0][`XLEN:0] mul_in1;
wire [NUM_LANES-1:0][`XLEN:0] mul_in2;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mul_in
assign mul_in1[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]} : {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]};
assign mul_in2[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]} : {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};
end
@ -149,7 +149,7 @@ module VX_alu_muldiv #(
`else
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_multiplier
wire [`XLEN:0] mul_in1 = {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]};
wire [`XLEN:0] mul_in2 = {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};
@ -184,7 +184,7 @@ module VX_alu_muldiv #(
`endif
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mul_result_out
`ifdef XLEN_64
assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] :
(is_mul_w_out ? `XLEN'($signed(mul_result_tmp[i][31:0])) :
@ -219,7 +219,7 @@ module VX_alu_muldiv #(
wire [NUM_LANES-1:0][`XLEN-1:0] div_in1;
wire [NUM_LANES-1:0][`XLEN-1:0] div_in2;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_div_in
`ifdef XLEN_64
assign div_in1[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]}: execute_if.data.rs1_data[i];
assign div_in2[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]}: execute_if.data.rs2_data[i];
@ -234,7 +234,7 @@ module VX_alu_muldiv #(
wire [NUM_LANES-1:0][`XLEN-1:0] div_result_in;
wire div_fire_in = div_valid_in && div_ready_in;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_div_result_in
reg [`XLEN-1:0] div_quotient, div_remainder;
always @(*) begin
dpi_idiv (div_fire_in, is_signed_op, div_in1[i], div_in2[i], div_quotient, div_remainder);
@ -306,7 +306,7 @@ module VX_alu_muldiv #(
assign {div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out, is_div_w_out, div_pid_out, div_sop_out, div_eop_out} = div_tag_r;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_div_result_out
`ifdef XLEN_64
assign div_result_out[i] = is_rem_op_out ? (is_div_w_out ? `XLEN'($signed(div_remainder[i][31:0])) : div_remainder[i]) :
(is_div_w_out ? `XLEN'($signed(div_quotient[i][31:0])) : div_quotient[i]);

2
hw/rtl/core/VX_alu_unit.sv
View file

@ -55,7 +55,7 @@ module VX_alu_unit #(
.execute_if (per_block_execute_if)
);
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alus
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_alus
VX_execute_if #(
.NUM_LANES (NUM_LANES)

12
hw/rtl/core/VX_commit.sv
View file

@ -41,13 +41,13 @@ module VX_commit import VX_gpu_pkg::*; #(
wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] per_issue_commit_tmask;
wire [`ISSUE_WIDTH-1:0] per_issue_commit_eop;
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : commit_arbs
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_commit_arbs
wire [`NUM_EX_UNITS-1:0] valid_in;
wire [`NUM_EX_UNITS-1:0][DATAW-1:0] data_in;
wire [`NUM_EX_UNITS-1:0] ready_in;
for (genvar j = 0; j < `NUM_EX_UNITS; ++j) begin
for (genvar j = 0; j < `NUM_EX_UNITS; ++j) begin : g_data_in
assign valid_in[j] = commit_if[j * `ISSUE_WIDTH + i].valid;
assign data_in[j] = commit_if[j * `ISSUE_WIDTH + i].data;
assign commit_if[j * `ISSUE_WIDTH + i].ready = ready_in[j];
@ -84,7 +84,7 @@ module VX_commit import VX_gpu_pkg::*; #(
assign commit_fire_any = (| per_issue_commit_fire);
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_commit_size
wire [COMMIT_SIZEW-1:0] count;
`POP_COUNT(count, per_issue_commit_tmask[i]);
assign commit_size[i] = count;
@ -160,7 +160,7 @@ module VX_commit import VX_gpu_pkg::*; #(
// Writeback
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_writeback
assign writeback_if[i].valid = commit_arb_if[i].valid && commit_arb_if[i].data.wb;
assign writeback_if[i].data.uuid = commit_arb_if[i].data.uuid;
assign writeback_if[i].data.wis = wid_to_wis(commit_arb_if[i].data.wid);
@ -174,8 +174,8 @@ module VX_commit import VX_gpu_pkg::*; #(
end
`ifdef DBG_TRACE_PIPELINE
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar j = 0; j < `NUM_EX_UNITS; ++j) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_trace
for (genvar j = 0; j < `NUM_EX_UNITS; ++j) begin : g_j
always @(posedge clk) begin
if (commit_if[j * `ISSUE_WIDTH + i].valid && commit_if[j * `ISSUE_WIDTH + i].ready) begin
`TRACE(1, ("%t: %s: wid=%0d, PC=0x%0h, ex=", $time, INSTANCE_ID, commit_if[j * `ISSUE_WIDTH + i].data.wid, {commit_if[j * `ISSUE_WIDTH + i].data.PC, 1'b0}))

4
hw/rtl/core/VX_core.sv
View file

@ -229,8 +229,8 @@ module VX_core import VX_gpu_pkg::*; #(
wire [LSU_NUM_REQS-1:0] perf_dcache_wr_req_fire, perf_dcache_wr_req_fire_r;
wire [LSU_NUM_REQS-1:0] perf_dcache_rsp_fire;
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
for (genvar j = 0; j < `NUM_LSU_LANES; ++j) begin
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_perf_dcache
for (genvar j = 0; j < `NUM_LSU_LANES; ++j) begin : g_j
assign perf_dcache_rd_req_fire[i * `NUM_LSU_LANES + j] = lsu_mem_if[i].req_valid && lsu_mem_if[i].req_data.mask[j] && lsu_mem_if[i].req_ready && ~lsu_mem_if[i].req_data.rw;
assign perf_dcache_wr_req_fire[i * `NUM_LSU_LANES + j] = lsu_mem_if[i].req_valid && lsu_mem_if[i].req_data.mask[j] && lsu_mem_if[i].req_ready && lsu_mem_if[i].req_data.rw;
assign perf_dcache_rsp_fire[i * `NUM_LSU_LANES + j] = lsu_mem_if[i].rsp_valid && lsu_mem_if[i].rsp_data.mask[j] && lsu_mem_if[i].rsp_ready;

4
hw/rtl/core/VX_csr_data.sv
View file

@ -83,7 +83,7 @@ import VX_fpu_pkg::*;
wire [`NUM_FPU_BLOCKS-1:0][`NW_WIDTH-1:0] fpu_write_wid;
fflags_t [`NUM_FPU_BLOCKS-1:0] fpu_write_fflags;
for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin : g_fpu_write
assign fpu_write_enable[i] = fpu_csr_if[i].write_enable;
assign fpu_write_wid[i] = fpu_csr_if[i].write_wid;
assign fpu_write_fflags[i] = fpu_csr_if[i].write_fflags;
@ -107,7 +107,7 @@ import VX_fpu_pkg::*;
end
end
for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin : g_fpu_csr_read_frm
assign fpu_csr_if[i].read_frm = fcsr[fpu_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
end

11
hw/rtl/core/VX_csr_unit.sv
View file

@ -66,7 +66,7 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
wire [NUM_LANES-1:0][`XLEN-1:0] rs1_data;
`UNUSED_VAR (rs1_data)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_rs1_data
assign rs1_data[i] = execute_if.data.rs1_data[i];
end
@ -113,12 +113,15 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
wire [NUM_LANES-1:0][`XLEN-1:0] wtid, gtid;
for (genvar i = 0; i < NUM_LANES; ++i) begin
if (PID_BITS != 0) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_wtid
if (PID_BITS != 0) begin : g_pid
assign wtid[i] = `XLEN'(execute_if.data.pid * NUM_LANES + i);
end else begin
end else begin : g_no_pid
assign wtid[i] = `XLEN'(i);
end
end
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_gtid
assign gtid[i] = (`XLEN'(CORE_ID) << (`NW_BITS + `NT_BITS)) + (`XLEN'(execute_if.data.wid) << `NT_BITS) + wtid[i];
end

6
hw/rtl/core/VX_dispatch.sv
View file

@ -33,7 +33,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + `INST_OP_BITS + `INST_ARGS_BITS + 1 + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH;
wire [`NUM_THREADS-1:0][`NT_WIDTH-1:0] tids;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
for (genvar i = 0; i < `NUM_THREADS; ++i) begin : g_tids
assign tids[i] = `NT_WIDTH'(i);
end
@ -53,7 +53,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
wire [`NUM_EX_UNITS-1:0] operands_ready_in;
assign operands_if.ready = operands_ready_in[operands_if.data.ex_type];
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : buffers
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : g_buffers
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (2),
@ -88,7 +88,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
wire operands_if_stall = operands_if.valid && ~operands_if.ready;
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : g_perf_stalls
always @(posedge clk) begin
if (reset) begin
perf_stalls_r[i] <= '0;

44
hw/rtl/core/VX_dispatch_unit.sv
View file

@ -49,7 +49,7 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
wire [`ISSUE_WIDTH-1:0][IN_DATAW-1:0] dispatch_data;
wire [`ISSUE_WIDTH-1:0] dispatch_ready;
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_dispatch_data
assign dispatch_valid[i] = dispatch_if[i].valid;
assign dispatch_data[i] = dispatch_if[i].data;
assign dispatch_if[i].ready = dispatch_ready[i];
@ -69,10 +69,10 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
logic [BATCH_COUNT_W-1:0] batch_idx;
if (BATCH_COUNT != 1) begin
if (BATCH_COUNT != 1) begin : g_batch_idx
wire [BATCH_COUNT_W-1:0] batch_idx_n;
wire [BATCH_COUNT-1:0] valid_batches;
for (genvar i = 0; i < BATCH_COUNT; ++i) begin
for (genvar i = 0; i < BATCH_COUNT; ++i) begin : g_valid_batches
assign valid_batches[i] = | dispatch_valid[i * BLOCK_SIZE +: BLOCK_SIZE];
end
@ -96,22 +96,22 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
batch_idx <= batch_idx_n;
end
end
end else begin
end else begin : g_batch_idx_0
assign batch_idx = 0;
`UNUSED_VAR (batch_done)
end
wire [BLOCK_SIZE-1:0][ISSUE_W-1:0] issue_indices;
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_issue_indices
assign issue_indices[block_idx] = ISSUE_W'(batch_idx * BLOCK_SIZE) + ISSUE_W'(block_idx);
end
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : blocks
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_blocks
wire [ISSUE_W-1:0] issue_idx = issue_indices[block_idx];
wire valid_p, ready_p;
if (`NUM_THREADS != NUM_LANES) begin : threads_split
if (`NUM_THREADS > NUM_LANES) begin : g_partial_threads
reg [NUM_PACKETS-1:0] sent_mask_p;
wire [PID_WIDTH-1:0] start_p_n, start_p, end_p;
wire dispatch_valid_r;
@ -146,8 +146,8 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs2_data = dispatch_data[issue_idx][DATA_REGS_OFF + 1 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs3_data = dispatch_data[issue_idx][DATA_REGS_OFF + 0 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
for (genvar i = 0; i < NUM_PACKETS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
for (genvar i = 0; i < NUM_PACKETS; ++i) begin : g_per_packet_data
for (genvar j = 0; j < NUM_LANES; ++j) begin : g_j
localparam k = i * NUM_LANES + j;
assign per_packet_tmask[i][j] = dispatch_tmask[k];
assign per_packet_regs[i][0][j] = dispatch_rs1_data[k];
@ -157,10 +157,12 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
end
wire [NUM_PACKETS-1:0] packet_valids;
wire [NUM_PACKETS-1:0][PID_WIDTH-1:0] packet_ids;
for (genvar i = 0; i < NUM_PACKETS; ++i) begin
for (genvar i = 0; i < NUM_PACKETS; ++i) begin : g_packet_valids
assign packet_valids[i] = (| per_packet_tmask[i]);
end
wire [NUM_PACKETS-1:0][PID_WIDTH-1:0] packet_ids;
for (genvar i = 0; i < NUM_PACKETS; ++i) begin : g_packet_ids
assign packet_ids[i] = PID_WIDTH'(i);
end
@ -209,13 +211,13 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
assign block_pid[block_idx] = start_p;
assign block_sop[block_idx] = is_first_p;
assign block_eop[block_idx] = is_last_p;
if (FANOUT_ENABLE) begin
if (FANOUT_ENABLE) begin : g_block_ready_fanout
assign block_ready[block_idx] = dispatch_valid_r && ready_p && block_enable;
end else begin
end else begin : g_block_ready
assign block_ready[block_idx] = ready_p && block_enable;
end
assign block_done[block_idx] = fire_eop || ~dispatch_valid[issue_idx];
end else begin
end else begin : g_full_threads
assign valid_p = dispatch_valid[issue_idx];
assign block_tmask[block_idx] = dispatch_data[issue_idx][DATA_TMASK_OFF +: `NUM_THREADS];
assign block_regs[block_idx][0] = dispatch_data[issue_idx][DATA_REGS_OFF + 2 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
@ -229,13 +231,13 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
end
wire [ISSUE_ISW_W-1:0] isw;
if (BATCH_COUNT != 1) begin
if (BLOCK_SIZE != 1) begin
if (BATCH_COUNT != 1) begin : g_isw_batch
if (BLOCK_SIZE != 1) begin : g_block
assign isw = {batch_idx, BLOCK_SIZE_W'(block_idx)};
end else begin
end else begin : g_no_block
assign isw = batch_idx;
end
end else begin
end else begin : g_isw
assign isw = block_idx;
end
@ -268,9 +270,9 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
.ready_out (execute_if[block_idx].ready)
);
if (`NUM_THREADS != NUM_LANES) begin
if (`NUM_THREADS != NUM_LANES) begin : g_execute_data_w_partial
assign execute_data_w = execute_data;
end else begin
end else begin : g_execute_data_w_full
always @(*) begin
execute_data_w = execute_data;
execute_data_w[2:0] = {1'b0, 1'b1, 1'b1}; // default pid, sop, and eop

8
hw/rtl/core/VX_fetch.sv
View file

@ -71,7 +71,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
// This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache requests.
// This issue is particularly prevalent when the icache and dcache are disabled and both requests share the same bus.
wire [`NUM_WARPS-1:0] pending_ibuf_full;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_reads
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_pending_reads
VX_pending_size #(
.SIZE (`IBUF_SIZE)
) pending_reads (
@ -164,13 +164,11 @@ module VX_fetch import VX_gpu_pkg::*; #(
`endif
`ifdef DBG_TRACE_MEM
wire schedule_fire = schedule_if.valid && schedule_if.ready;
wire fetch_fire = fetch_if.valid && fetch_if.ready;
always @(posedge clk) begin
if (schedule_fire) begin
if (schedule_if.valid && schedule_if.ready) begin
`TRACE(1, ("%t: %s req: wid=%0d, PC=0x%0h, tmask=%b (#%0d)\n", $time, INSTANCE_ID, schedule_if.data.wid, {schedule_if.data.PC, 1'b0}, schedule_if.data.tmask, schedule_if.data.uuid))
end
if (fetch_fire) begin
if (fetch_if.valid && fetch_if.ready) begin
`TRACE(1, ("%t: %s rsp: wid=%0d, PC=0x%0h, tmask=%b, instr=0x%0h (#%0d)\n", $time, INSTANCE_ID, fetch_if.data.wid, {fetch_if.data.PC, 1'b0}, fetch_if.data.tmask, fetch_if.data.instr, fetch_if.data.uuid))
end
end

10
hw/rtl/core/VX_fpu_unit.sv
View file

@ -53,7 +53,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.NUM_LANES (NUM_LANES)
) per_block_commit_if[BLOCK_SIZE]();
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : fpus
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_fpus
`UNUSED_VAR (per_block_execute_if[block_idx].data.tid)
`UNUSED_VAR (per_block_execute_if[block_idx].data.wb)
@ -98,11 +98,11 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
`UNUSED_PIN (empty)
);
if (PID_BITS != 0) begin
if (PID_BITS != 0) begin : g_fpu_rsp_pid
assign fpu_rsp_pid = fpu_rsp_pid_u;
assign fpu_rsp_sop = fpu_rsp_sop_u;
assign fpu_rsp_eop = fpu_rsp_eop_u;
end else begin
end else begin : g_no_fpu_rsp_pid
`UNUSED_VAR (fpu_rsp_pid_u)
`UNUSED_VAR (fpu_rsp_sop_u)
`UNUSED_VAR (fpu_rsp_eop_u)
@ -214,7 +214,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
// handle CSR update
fflags_t fpu_rsp_fflags_q;
if (PID_BITS != 0) begin
if (PID_BITS != 0) begin : g_pid
fflags_t fpu_rsp_fflags_r;
always @(posedge clk) begin
if (reset) begin
@ -224,7 +224,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
end
end
assign fpu_rsp_fflags_q = fpu_rsp_fflags_r | fpu_rsp_fflags;
end else begin
end else begin : g_no_pid
assign fpu_rsp_fflags_q = fpu_rsp_fflags;
end

19
hw/rtl/core/VX_gather_unit.sv
View file

@ -41,17 +41,17 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
wire [BLOCK_SIZE-1:0] commit_in_ready;
wire [BLOCK_SIZE-1:0][ISSUE_ISW_W-1:0] commit_in_isw;
for (genvar i = 0; i < BLOCK_SIZE; ++i) begin
for (genvar i = 0; i < BLOCK_SIZE; ++i) begin : g_commit_in
assign commit_in_valid[i] = commit_in_if[i].valid;
assign commit_in_data[i] = commit_in_if[i].data;
assign commit_in_if[i].ready = commit_in_ready[i];
if (BLOCK_SIZE != `ISSUE_WIDTH) begin
if (BLOCK_SIZE != 1) begin
if (BLOCK_SIZE != `ISSUE_WIDTH) begin : g_commit_in_isw_partial
if (BLOCK_SIZE != 1) begin : g_block
assign commit_in_isw[i] = {commit_in_data[i][DATA_WIS_OFF+BLOCK_SIZE_W +: (ISSUE_ISW_W-BLOCK_SIZE_W)], BLOCK_SIZE_W'(i)};
end else begin
end else begin : g_no_block
assign commit_in_isw[i] = commit_in_data[i][DATA_WIS_OFF +: ISSUE_ISW_W];
end
end else begin
end else begin : g_commit_in_isw_full
assign commit_in_isw[i] = BLOCK_SIZE_W'(i);
end
end
@ -70,11 +70,12 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
commit_out_data[commit_in_isw[i]] = commit_in_data[i];
end
end
for (genvar i = 0; i < BLOCK_SIZE; ++i) begin
for (genvar i = 0; i < BLOCK_SIZE; ++i) begin : g_commit_in_ready
assign commit_in_ready[i] = commit_out_ready[commit_in_isw[i]];
end
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin: out_bufs
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin: g_out_bufs
VX_commit_if #(
.NUM_LANES (NUM_LANES)
) commit_tmp_if();
@ -96,7 +97,7 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
logic [`NUM_THREADS-1:0] commit_tmask_w;
logic [`NUM_THREADS-1:0][`XLEN-1:0] commit_data_w;
if (PID_BITS != 0) begin
if (PID_BITS != 0) begin : g_commit_data_with_pid
always @(*) begin
commit_tmask_w = '0;
commit_data_w = 'x;
@ -105,7 +106,7 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
commit_data_w[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.data[j];
end
end
end else begin
end else begin : g_commit_data_no_pid
assign commit_tmask_w = commit_tmp_if.data.tmask;
assign commit_data_w = commit_tmp_if.data.data;
end

2
hw/rtl/core/VX_ibuffer.sv
View file

@ -35,7 +35,7 @@ module VX_ibuffer import VX_gpu_pkg::*; #(
wire [PER_ISSUE_WARPS-1:0] ibuf_ready_in;
assign decode_if.ready = ibuf_ready_in[decode_if.data.wid];
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : instr_bufs
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_instr_bufs
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`IBUF_SIZE),

8
hw/rtl/core/VX_issue.sv
View file

@ -36,10 +36,10 @@ module VX_issue import VX_gpu_pkg::*; #(
`PERF_COUNTER_ADD (issue_perf, per_issue_perf, ibf_stalls, `PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2))
`PERF_COUNTER_ADD (issue_perf, per_issue_perf, scb_stalls, `PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2))
`PERF_COUNTER_ADD (issue_perf, per_issue_perf, opd_stalls, `PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2))
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : g_issue_perf_units_uses
`PERF_COUNTER_ADD (issue_perf, per_issue_perf, units_uses[i], `PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2))
end
for (genvar i = 0; i < `NUM_SFU_UNITS; ++i) begin
for (genvar i = 0; i < `NUM_SFU_UNITS; ++i) begin : g_issue_perf_sfu_uses
`PERF_COUNTER_ADD (issue_perf, per_issue_perf, sfu_uses[i], `PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2))
end
`endif
@ -52,7 +52,7 @@ module VX_issue import VX_gpu_pkg::*; #(
`SCOPE_IO_SWITCH (`ISSUE_WIDTH)
for (genvar issue_id = 0; issue_id < `ISSUE_WIDTH; ++issue_id) begin : issue_slices
for (genvar issue_id = 0; issue_id < `ISSUE_WIDTH; ++issue_id) begin : g_issue_slices
VX_decode_if #(
.NUM_WARPS (PER_ISSUE_WARPS)
) per_issue_decode_if();
@ -93,7 +93,7 @@ module VX_issue import VX_gpu_pkg::*; #(
);
// Assign transposed dispatch_if
for (genvar ex_id = 0; ex_id < `NUM_EX_UNITS; ++ex_id) begin
for (genvar ex_id = 0; ex_id < `NUM_EX_UNITS; ++ex_id) begin : g_dispatch_if
`ASSIGN_VX_IF(dispatch_if[ex_id * `ISSUE_WIDTH + issue_id], per_issue_dispatch_if[ex_id]);
end
end

4
hw/rtl/core/VX_issue_top.sv
View file

@ -80,7 +80,7 @@ module VX_issue_top import VX_gpu_pkg::*; #(
assign decode_if.data.rs3 = decode_rs3;
assign decode_ready = decode_if.ready;
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_writeback_if
assign writeback_if[i].valid = writeback_valid[i];
assign writeback_if[i].data.uuid = writeback_uuid[i];
assign writeback_if[i].data.wis = writeback_wis[i];
@ -92,7 +92,7 @@ module VX_issue_top import VX_gpu_pkg::*; #(
assign writeback_if[i].data.eop = writeback_eop[i];
end
for (genvar i = 0; i < `NUM_EX_UNITS * `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `NUM_EX_UNITS * `ISSUE_WIDTH; ++i) begin : g_dispatch_if
assign dispatch_valid[i] = dispatch_if[i].valid;
assign dispatch_uuid[i] = dispatch_if[i].data.uuid;
assign dispatch_wis[i] = dispatch_if[i].data.wis;

19
hw/rtl/core/VX_lsu_slice.sv
View file

@ -59,14 +59,14 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
wire req_is_fence, rsp_is_fence;
wire [NUM_LANES-1:0][`XLEN-1:0] full_addr;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_full_addr
assign full_addr[i] = execute_if.data.rs1_data[i] + `SEXT(`XLEN, execute_if.data.op_args.lsu.offset);
end
// address type calculation
wire [NUM_LANES-1:0][`MEM_REQ_FLAGS_WIDTH-1:0] mem_req_flags;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_flags
wire [MEM_ADDRW-1:0] block_addr = full_addr[i][MEM_ASHIFT +: MEM_ADDRW];
// is I/O address
wire [MEM_ADDRW-1:0] io_addr_start = MEM_ADDRW'(`XLEN'(`IO_BASE_ADDR) >> MEM_ASHIFT);
@ -151,13 +151,13 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] req_align;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_addr
assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0];
assign mem_req_addr[i] = full_addr[i][`MEM_ADDR_WIDTH-1:REQ_ASHIFT];
end
// byte enable formatting
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_byteen_w
reg [LSU_WORD_SIZE-1:0] mem_req_byteen_w;
always @(*) begin
mem_req_byteen_w = '0;
@ -185,7 +185,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
end
// memory misalignment not supported!
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_missalign
wire lsu_req_fire = execute_if.valid && execute_if.ready;
`RUNTIME_ASSERT((~lsu_req_fire || ~execute_if.data.tmask[i] || req_is_fence || (full_addr[i] % (1 << `INST_LSU_WSIZE(execute_if.data.op_type))) == 0),
("%t: misaligned memory access, wid=%0d, PC=0x%0h, addr=0x%0h, wsize=%0d! (#%0d)",
@ -193,7 +193,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
end
// store data formatting
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_data
always @(*) begin
mem_req_data[i] = execute_if.data.rs2_data[i];
case (req_align[i])
@ -215,7 +215,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
wire [LSUQ_SIZEW-1:0] pkt_waddr, pkt_raddr;
if (PID_BITS != 0) begin
if (PID_BITS != 0) begin : g_pids
reg [`LSUQ_IN_SIZE-1:0][PID_BITS:0] pkt_ctr;
reg [`LSUQ_IN_SIZE-1:0] pkt_sop, pkt_eop;
@ -274,7 +274,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
`RUNTIME_ASSERT(~(mem_req_rd_fire && full), ("%t: allocator full!", $time))
`RUNTIME_ASSERT(~mem_req_rd_sop_fire || 0 == pkt_ctr[pkt_waddr], ("%t: oops! broken sop request!", $time))
`UNUSED_VAR (mem_rsp_sop)
end else begin
end else begin : g_no_pids
assign pkt_waddr = 0;
assign mem_rsp_sop_pkt = mem_rsp_sop;
assign mem_rsp_eop_pkt = mem_rsp_eop;
@ -424,7 +424,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
`endif
`endif
for (genvar i = 0; i < NUM_LANES; i++) begin
for (genvar i = 0; i < NUM_LANES; i++) begin : g_rsp_data
`ifdef XLEN_64
wire [63:0] rsp_data64 = mem_rsp_data[i];
wire [31:0] rsp_data32 = (rsp_align[i][2] ? mem_rsp_data[i][63:32] : mem_rsp_data[i][31:0]);
@ -481,6 +481,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
.valid_out (commit_no_rsp_if.valid),
.ready_out (commit_no_rsp_if.ready)
);
assign commit_no_rsp_if.data.rd = '0;
assign commit_no_rsp_if.data.wb = 1'b0;
assign commit_no_rsp_if.data.data = commit_rsp_if.data.data; // arbiter MUX optimization

2
hw/rtl/core/VX_lsu_unit.sv
View file

@ -54,7 +54,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
.NUM_LANES (NUM_LANES)
) per_block_commit_if[BLOCK_SIZE]();
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsus
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_lsus
VX_lsu_slice #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, block_idx))
) lsu_slice(

20
hw/rtl/core/VX_mem_unit.sv
View file

@ -45,7 +45,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (LSU_TAG_WIDTH)
) lsu_lmem_if[`NUM_LSU_BLOCKS]();
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_switches
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lmem_switches
VX_lmem_switch #(
.REQ0_OUT_BUF (3),
.REQ1_OUT_BUF (0),
@ -65,7 +65,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (LSU_TAG_WIDTH)
) lmem_bus_if[LSU_NUM_REQS]();
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_adapters
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lmem_adapters
VX_mem_bus_if #(
.DATA_SIZE (LSU_WORD_SIZE),
.TAG_WIDTH (LSU_TAG_WIDTH)
@ -86,7 +86,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.mem_bus_if (lmem_bus_tmp_if)
);
for (genvar j = 0; j < `NUM_LSU_LANES; ++j) begin
for (genvar j = 0; j < `NUM_LSU_LANES; ++j) begin : g_lmem_bus_if
`ASSIGN_VX_MEM_BUS_IF (lmem_bus_if[i * `NUM_LSU_LANES + j], lmem_bus_tmp_if[j]);
end
end
@ -115,7 +115,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
`ifdef PERF_ENABLE
assign lmem_perf = '0;
`endif
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lsu_dcache_if
`ASSIGN_VX_MEM_BUS_IF (lsu_dcache_if[i], lsu_mem_if[i]);
end
@ -127,9 +127,9 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) dcache_coalesced_if[`NUM_LSU_BLOCKS]();
if (LSU_WORD_SIZE != DCACHE_WORD_SIZE) begin : coalescer_if
if (LSU_WORD_SIZE != DCACHE_WORD_SIZE) begin : g_enabled
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : coalescers
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_coalescers
VX_mem_coalescer #(
.INSTANCE_ID ($sformatf("%s-coalescer%0d", INSTANCE_ID, i)),
.NUM_REQS (`NUM_LSU_LANES),
@ -182,15 +182,15 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
);
end
end else begin
end else begin : g_passthru
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_dcache_coalesced_if
`ASSIGN_VX_MEM_BUS_IF (dcache_coalesced_if[i], lsu_dcache_if[i]);
end
end
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : dcache_adapters
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_dcache_adapters
VX_mem_bus_if #(
.DATA_SIZE (DCACHE_WORD_SIZE),
@ -212,7 +212,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.mem_bus_if (dcache_bus_tmp_if)
);
for (genvar j = 0; j < DCACHE_CHANNELS; ++j) begin
for (genvar j = 0; j < DCACHE_CHANNELS; ++j) begin : g_dcache_bus_if
`ASSIGN_VX_MEM_BUS_IF (dcache_bus_if[i * DCACHE_CHANNELS + j], dcache_bus_tmp_if[j]);
end

8
hw/rtl/core/VX_mem_unit_top.sv
View file

@ -62,7 +62,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
) lsu_mem_if[`NUM_LSU_BLOCKS]();
// LSU memory request
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lsu_mem_req
assign lsu_mem_if[i].req_valid = lsu_req_valid[i];
assign lsu_mem_if[i].req_data.rw = lsu_req_rw[i];
assign lsu_mem_if[i].req_data.mask = lsu_req_mask[i];
@ -75,7 +75,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
end
// LSU memory response
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lsu_rsp
assign lsu_rsp_valid[i] = lsu_mem_if[i].rsp_valid;
assign lsu_rsp_mask[i] = lsu_mem_if[i].rsp_data.mask;
assign lsu_rsp_data[i] = lsu_mem_if[i].rsp_data.data;
@ -89,7 +89,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
) mem_bus_if[DCACHE_NUM_REQS]();
// memory request
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin : g_mem_req
assign mem_req_valid[i] = mem_bus_if[i].req_valid;
assign mem_req_rw[i] = mem_bus_if[i].req_data.rw;
assign mem_req_byteen[i] = mem_bus_if[i].req_data.byteen;
@ -101,7 +101,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
end
// memory response
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin : g_mem_bus_rsp
assign mem_bus_if[i].rsp_valid = mem_rsp_valid[i];
assign mem_bus_if[i].rsp_data.tag = mem_rsp_tag[i];
assign mem_bus_if[i].rsp_data.data = mem_rsp_data[i];

31
hw/rtl/core/VX_operands.sv
View file

@ -81,20 +81,23 @@ module VX_operands import VX_gpu_pkg::*; #(
wire [NUM_SRC_OPDS-1:0][`NR_BITS-1:0] src_opds;
assign src_opds = {scoreboard_if.data.rs3, scoreboard_if.data.rs2, scoreboard_if.data.rs1};
for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin
if (ISSUE_WIS != 0) begin
for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_req_data_in
if (ISSUE_WIS != 0) begin : g_wis
assign req_data_in[i] = {src_opds[i][`NR_BITS-1:BANK_SEL_BITS], scoreboard_if.data.wis};
end else begin
end else begin : g_no_wis
assign req_data_in[i] = src_opds[i][`NR_BITS-1:BANK_SEL_BITS];
end
if (NUM_BANKS != 1) begin
end
for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_req_bank_idx
if (NUM_BANKS != 1) begin : g_banks
assign req_bank_idx[i] = src_opds[i][BANK_SEL_BITS-1:0];
end else begin
end else begin : g_1bank
assign req_bank_idx[i] = '0;
end
end
for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin
for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_src_valid
assign src_valid[i] = (src_opds[i] != 0) && ~data_fetched_st1[i];
end
@ -232,30 +235,30 @@ module VX_operands import VX_gpu_pkg::*; #(
);
wire [PER_BANK_ADDRW-1:0] gpr_wr_addr;
if (ISSUE_WIS != 0) begin
if (ISSUE_WIS != 0) begin : g_gpr_wr_addr
assign gpr_wr_addr = {writeback_if.data.rd[`NR_BITS-1:BANK_SEL_BITS], writeback_if.data.wis};
end else begin
end else begin : g_gpr_wr_addr_no_wis
assign gpr_wr_addr = writeback_if.data.rd[`NR_BITS-1:BANK_SEL_BITS];
end
wire [BANK_SEL_WIDTH-1:0] gpr_wr_bank_idx;
if (NUM_BANKS != 1) begin
if (NUM_BANKS != 1) begin : g_gpr_wr_bank_idx
assign gpr_wr_bank_idx = writeback_if.data.rd[BANK_SEL_BITS-1:0];
end else begin
end else begin : g_gpr_wr_bank_idx_0
assign gpr_wr_bank_idx = '0;
end
for (genvar b = 0; b < NUM_BANKS; ++b) begin : gpr_rams
for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_gpr_rams
wire gpr_wr_enabled;
if (BANK_SEL_BITS != 0) begin
if (BANK_SEL_BITS != 0) begin : g_gpr_wr_enabled
assign gpr_wr_enabled = writeback_if.valid
&& (gpr_wr_bank_idx == BANK_SEL_BITS'(b));
end else begin
end else begin : g_gpr_wr_enabled_1bank
assign gpr_wr_enabled = writeback_if.valid;
end
wire [BYTEENW-1:0] wren;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
for (genvar i = 0; i < `NUM_THREADS; ++i) begin : g_wren
assign wren[i*XLEN_SIZE+:XLEN_SIZE] = {XLEN_SIZE{writeback_if.data.tmask[i]}};
end

4
hw/rtl/core/VX_pe_switch.sv
View file

@ -54,7 +54,7 @@ module VX_pe_switch import VX_gpu_pkg::*; #(
.ready_out (pe_req_ready)
);
for (genvar i = 0; i < PE_COUNT; ++i) begin
for (genvar i = 0; i < PE_COUNT; ++i) begin : g_execute_out_if
assign execute_out_if[i].valid = pe_req_valid[i];
assign execute_out_if[i].data = pe_req_data[i];
assign pe_req_ready[i] = execute_out_if[i].ready;
@ -66,7 +66,7 @@ module VX_pe_switch import VX_gpu_pkg::*; #(
wire [PE_COUNT-1:0][RSP_DATAW-1:0] pe_rsp_data;
wire [PE_COUNT-1:0] pe_rsp_ready;
for (genvar i = 0; i < PE_COUNT; ++i) begin
for (genvar i = 0; i < PE_COUNT; ++i) begin : g_commit_in_if
assign pe_rsp_valid[i] = commit_in_if[i].valid;
assign pe_rsp_data[i] = commit_in_if[i].data;
assign commit_in_if[i].ready = pe_rsp_ready[i];

6
hw/rtl/core/VX_schedule.sv
View file

@ -78,7 +78,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
wire [`NUM_ALU_BLOCKS-1:0][`NW_WIDTH-1:0] branch_wid;
wire [`NUM_ALU_BLOCKS-1:0] branch_taken;
wire [`NUM_ALU_BLOCKS-1:0][`PC_BITS-1:0] branch_dest;
for (genvar i = 0; i < `NUM_ALU_BLOCKS; ++i) begin
for (genvar i = 0; i < `NUM_ALU_BLOCKS; ++i) begin : g_branch_init
assign branch_valid[i] = branch_ctl_if[i].valid;
assign branch_wid[i] = branch_ctl_if[i].wid;
assign branch_taken[i] = branch_ctl_if[i].taken;
@ -322,7 +322,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
);
wire [`NUM_WARPS-1:0][(`NUM_THREADS + `PC_BITS)-1:0] schedule_data;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_schedule_data
assign schedule_data[i] = {thread_masks[i], warp_pcs[i]};
end
@ -367,7 +367,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
wire [`NUM_WARPS-1:0] pending_warp_empty;
wire [`NUM_WARPS-1:0] pending_warp_alm_empty;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_sizes
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_pending_sizes
VX_pending_size #(
.SIZE (4096),
.ALM_EMPTY (1)

14
hw/rtl/core/VX_scoreboard.sv
View file

@ -66,13 +66,13 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
`BUFFER_EX(perf_sfu_per_cycle_r, perf_sfu_per_cycle, 1'b1, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT));
wire [PER_ISSUE_WARPS-1:0] stg_valid_in;
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_stg_valid_in
assign stg_valid_in[w] = staging_if[w].valid;
end
wire perf_stall_per_cycle = (|stg_valid_in) && ~(|(stg_valid_in & operands_ready));
always @(posedge clk) begin
always @(posedge clk) begin : g_perf_stalls
if (reset) begin
perf_stalls <= '0;
end else begin
@ -80,7 +80,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
end
end
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : g_perf_units_uses
always @(posedge clk) begin
if (reset) begin
perf_units_uses[i] <= '0;
@ -90,7 +90,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
end
end
for (genvar i = 0; i < `NUM_SFU_UNITS; ++i) begin
for (genvar i = 0; i < `NUM_SFU_UNITS; ++i) begin : g_perf_sfu_uses
always @(posedge clk) begin
if (reset) begin
perf_sfu_uses[i] <= '0;
@ -101,7 +101,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
end
`endif
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : stanging_bufs
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_stanging_bufs
VX_pipe_buffer #(
.DATAW (DATAW)
) stanging_buf (
@ -116,7 +116,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
);
end
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_scoreboard
reg [`NUM_REGS-1:0] inuse_regs;
reg [NUM_OPDS-1:0] operands_busy, operands_busy_n;
@ -233,7 +233,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
wire [PER_ISSUE_WARPS-1:0][DATAW-1:0] arb_data_in;
wire [PER_ISSUE_WARPS-1:0] arb_ready_in;
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_arb_data_in
assign arb_valid_in[w] = staging_if[w].valid && operands_ready[w];
assign arb_data_in[w] = staging_if[w].data;
assign staging_if[w].ready = arb_ready_in[w] && operands_ready[w];

2
hw/rtl/core/VX_split_join.sv
View file

@ -45,7 +45,7 @@ module VX_split_join import VX_gpu_pkg::*; #(
wire ipdom_push = valid && split.valid && split.is_dvg;
wire ipdom_pop = valid && sjoin.valid && sjoin_is_dvg;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : ipdom_stacks
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_ipdom_stacks
VX_ipdom_stack #(
.WIDTH (`NUM_THREADS+`PC_BITS),
.DEPTH (`DV_STACK_SIZE),

10
hw/rtl/core/VX_wctl_unit.sv
View file

@ -50,9 +50,9 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
wire is_bar = (execute_if.data.op_type == `INST_SFU_BAR);
wire [`UP(LANE_BITS)-1:0] tid;
if (LANE_BITS != 0) begin
if (LANE_BITS != 0) begin : g_tid
assign tid = execute_if.data.tid[0 +: LANE_BITS];
end else begin
end else begin : g_no_tid
assign tid = 0;
end
@ -63,7 +63,7 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
wire not_pred = execute_if.data.op_args.wctl.is_neg;
wire [NUM_LANES-1:0] taken;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_taken
assign taken[i] = (execute_if.data.rs1_data[i][0] ^ not_pred);
end
@ -131,7 +131,7 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
// wspawn
wire [`NUM_WARPS-1:0] wspawn_wmask;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_wspawn_wmask
assign wspawn_wmask[i] = (i < rs1_data[`NW_BITS:0]) && (i != execute_if.data.wid);
end
assign wspawn.valid = is_wspawn;
@ -162,7 +162,7 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
assign warp_ctl_if.sjoin = sjoin_r;
assign warp_ctl_if.barrier = barrier_r;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_commit_if
assign commit_if.data.data[i] = `XLEN'(dvstack_ptr);
end

6
hw/rtl/fpu/VX_fpu_cvt.sv
View file

@ -58,7 +58,7 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
wire [NUM_PES-1:0][DATAW-1:0] pe_data_in;
wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in
assign data_in[i][0 +: 32] = dataa[i];
assign data_in[i][32 +: `INST_FRM_BITS] = frm;
assign data_in[i][32 + `INST_FRM_BITS +: 1] = is_itof;
@ -92,12 +92,12 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
for (genvar i = 0; i < NUM_PES; ++i) begin : fcvt_units
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fcvt_units
VX_fcvt_unit #(
.LATENCY (`LATENCY_FCVT),
.OUT_REG (1)

10
hw/rtl/fpu/VX_fpu_div.sv
View file

@ -56,7 +56,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
wire [NUM_PES-1:0][DATAW-1:0] pe_data_in;
wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in
assign data_in[i][0 +: 32] = dataa[i];
assign data_in[i][32 +: 32] = datab[i];
assign data_in[i][64 +: `INST_FRM_BITS] = frm;
@ -89,7 +89,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
@ -98,7 +98,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`ifdef QUARTUS
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs
acl_fdiv fdiv (
.clk (clk),
.areset (1'b0),
@ -116,7 +116,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`elsif VIVADO
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs
wire [3:0] tuser;
xil_fdiv fdiv (
.aclk (clk),
@ -138,7 +138,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`else
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs
reg [63:0] r;
`UNUSED_VAR (r)
fflags_t f;

12
hw/rtl/fpu/VX_fpu_dpi.sv
View file

@ -124,7 +124,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
end
generate
begin : fma
begin : g_fma
reg [NUM_LANES-1:0][`XLEN-1:0] result_fma;
reg [NUM_LANES-1:0][63:0] result_fadd;
@ -200,7 +200,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
endgenerate
generate
begin : fdiv
begin : g_fdiv
reg [NUM_LANES-1:0][`XLEN-1:0] result_fdiv_r;
reg [NUM_LANES-1:0][63:0] result_fdiv;
@ -239,7 +239,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
endgenerate
generate
begin : fsqrt
begin : g_fsqrt
reg [NUM_LANES-1:0][`XLEN-1:0] result_fsqrt_r;
reg [NUM_LANES-1:0][63:0] result_fsqrt;
@ -278,7 +278,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
endgenerate
generate
begin : fcvt
begin : g_fcvt
reg [NUM_LANES-1:0][`XLEN-1:0] result_fcvt;
reg [NUM_LANES-1:0][63:0] result_itof;
@ -342,7 +342,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
endgenerate
generate
begin : fncp
begin : g_fncp
reg [NUM_LANES-1:0][`XLEN-1:0] result_fncp;
reg [NUM_LANES-1:0][63:0] result_fclss;
@ -449,7 +449,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
wire [NUM_FPC-1:0][RSP_DATAW-1:0] per_core_data_out;
for (genvar i = 0; i < NUM_FPC; ++i) begin
for (genvar i = 0; i < NUM_FPC; ++i) begin : g_per_core_data_out
assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
end

10
hw/rtl/fpu/VX_fpu_dsp.sv
View file

@ -83,7 +83,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
wire [NUM_LANES-1:0][31:0] datab_s;
wire [NUM_LANES-1:0][31:0] datac_s;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data
assign dataa_s[i] = dataa[i][31:0];
assign datab_s[i] = datab[i][31:0];
assign datac_s[i] = datac[i][31:0];
@ -111,7 +111,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
.ready_out (per_core_ready_in)
);
for (genvar i = 0; i < NUM_FPCORES; ++i) begin
for (genvar i = 0; i < NUM_FPCORES; ++i) begin : g_per_core_data_in
assign {
per_core_mask_in[i],
per_core_tag_in[i],
@ -211,7 +211,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
.ready_out (div_sqrt_ready_in)
);
for (genvar i = 0; i < 2; ++i) begin
for (genvar i = 0; i < 2; ++i) begin : g_div_sqrt_data_in
assign {
div_sqrt_mask_in[i],
div_sqrt_tag_in[i],
@ -271,7 +271,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
);
wire [1:0][RSP_DATAW-1:0] div_sqrt_arb_data_in;
for (genvar i = 0; i < 2; ++i) begin
for (genvar i = 0; i < 2; ++i) begin : g_div_sqrt_arb_data_in
assign div_sqrt_arb_data_in[i] = {
div_sqrt_result[i],
div_sqrt_has_fflags[i],
@ -403,7 +403,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
`UNUSED_PIN (sel_out)
);
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result
`ifdef FPU_RV64F
reg [`XLEN-1:0] result_w;
always @(*) begin

12
hw/rtl/fpu/VX_fpu_fma.sv
View file

@ -63,7 +63,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
reg [NUM_LANES-1:0][31:0] a, b, c;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_select
always @(*) begin
if (is_madd) begin
// MADD / MSUB / NMADD / NMSUB
@ -86,7 +86,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
end
end
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in
assign data_in[i][0 +: 32] = a[i];
assign data_in[i][32 +: 32] = b[i];
assign data_in[i][64 +: 32] = c[i];
@ -120,7 +120,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
@ -129,7 +129,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`ifdef QUARTUS
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas
acl_fmadd fmadd (
.clk (clk),
.areset (1'b0),
@ -147,7 +147,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`elsif VIVADO
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas
wire [2:0] tuser;
xil_fma fma (
@ -172,7 +172,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`else
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas
reg [63:0] r;
`UNUSED_VAR (r)
fflags_t f;

4
hw/rtl/fpu/VX_fpu_fpnew.sv
View file

@ -162,7 +162,7 @@ module VX_fpu_fpnew
end
`UNUSED_VAR (mask_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin : fpnew_cores
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_fpnew_coreses
wire [(TAG_WIDTH+1)-1:0] fpu_tag;
wire fpu_valid_out_uq;
wire fpu_ready_in_uq;
@ -201,7 +201,7 @@ module VX_fpu_fpnew
`UNUSED_PIN (busy_o)
);
if (i == 0) begin
if (i == 0) begin : g_output_0
assign {fpu_tag_out, fpu_has_fflags_out} = fpu_tag;
assign fpu_valid_out = fpu_valid_out_uq;
assign fpu_ready_in = fpu_ready_in_uq;

6
hw/rtl/fpu/VX_fpu_ncp.sv
View file

@ -57,7 +57,7 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
wire [NUM_PES-1:0][DATAW-1:0] pe_data_in;
wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in
assign data_in[i][0 +: 32] = dataa[i];
assign data_in[i][32 +: 32] = datab[i];
assign data_in[i][64 +: `INST_FRM_BITS] = frm;
@ -91,12 +91,12 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
for (genvar i = 0; i < NUM_PES; ++i) begin : fncp_units
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fncp_units
VX_fncp_unit #(
.LATENCY (`LATENCY_FNCP),
.OUT_REG (1)

10
hw/rtl/fpu/VX_fpu_sqrt.sv
View file

@ -55,7 +55,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
wire [NUM_PES-1:0][DATAW-1:0] pe_data_in;
wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out;
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in
assign data_in[i][0 +: 32] = dataa[i];
assign data_in[i][32 +: `INST_FRM_BITS] = frm;
end
@ -87,7 +87,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
@ -96,7 +96,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`ifdef QUARTUS
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts
acl_fsqrt fsqrt (
.clk (clk),
.areset (1'b0),
@ -113,7 +113,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`elsif VIVADO
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts
wire tuser;
xil_fsqrt fsqrt (
@ -134,7 +134,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`else
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts
reg [63:0] r;
`UNUSED_VAR (r)
fflags_t f;

24
hw/rtl/libs/VX_avs_adapter.sv
View file

@ -67,19 +67,19 @@ module VX_avs_adapter #(
wire [BANK_OFFSETW-1:0] req_bank_off;
wire [NUM_BANKS-1:0] bank_req_ready;
if (NUM_BANKS > 1) begin
if (NUM_BANKS > 1) begin : g_bank_sel
assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0];
end else begin
end else begin : g_bank_sel
assign req_bank_sel = '0;
end
assign req_bank_off = mem_req_addr[ADDR_WIDTH-1:LOG2_NUM_BANKS];
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_req_queue_push
assign req_queue_push[i] = mem_req_valid && ~mem_req_rw && bank_req_ready[i] && (req_bank_sel == i);
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin : pending_sizes
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_pending_sizes
VX_pending_size #(
.SIZE (RD_QUEUE_SIZE)
) pending_size (
@ -95,7 +95,7 @@ module VX_avs_adapter #(
);
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin : rd_req_queues
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_rd_req_queues
VX_fifo_queue #(
.DATAW (TAG_WIDTH),
.DEPTH (RD_QUEUE_SIZE)
@ -114,7 +114,7 @@ module VX_avs_adapter #(
);
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin : req_out_bufs
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_req_out_bufs
wire valid_out;
wire rw_out;
wire [DATA_SIZE-1:0] byteen_out;
@ -151,11 +151,7 @@ module VX_avs_adapter #(
assign bank_req_ready[i] = ready_out_w && ~req_queue_going_full[i];
end
if (NUM_BANKS > 1) begin
assign mem_req_ready = bank_req_ready[req_bank_sel];
end else begin
assign mem_req_ready = bank_req_ready;
end
assign mem_req_ready = bank_req_ready[req_bank_sel];
// Responses handling /////////////////////////////////////////////////////
@ -166,7 +162,7 @@ module VX_avs_adapter #(
wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] rsp_queue_data_out;
wire [NUM_BANKS-1:0] rsp_queue_empty;
for (genvar i = 0; i < NUM_BANKS; ++i) begin : rd_rsp_queues
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_rd_rsp_queues
VX_fifo_queue #(
.DATAW (DATA_WIDTH),
.DEPTH (RD_QUEUE_SIZE)
@ -185,8 +181,8 @@ module VX_avs_adapter #(
);
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin
assign rsp_arb_valid_in[i] = !rsp_queue_empty[i];
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_rsp_arbs
assign rsp_arb_valid_in[i] = ~rsp_queue_empty[i];
assign rsp_arb_data_in[i] = {rsp_queue_data_out[i], req_queue_tag_out[i]};
assign req_queue_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i];
end

26
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -95,9 +95,9 @@ module VX_axi_adapter #(
wire [BANK_ADDRW-1:0] req_bank_sel;
if (NUM_BANKS > 1) begin
if (NUM_BANKS > 1) begin : g_req_bank_sel
assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0];
end else begin
end else begin : g_req_bank_sel_0
assign req_bank_sel = '0;
end
@ -106,7 +106,7 @@ module VX_axi_adapter #(
reg [NUM_BANKS-1:0] m_axi_aw_ack;
reg [NUM_BANKS-1:0] m_axi_w_ack;
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_m_axi_w
wire m_axi_aw_fire = m_axi_awvalid[i] && m_axi_awready[i];
wire m_axi_w_fire = m_axi_wvalid[i] && m_axi_wready[i];
always @(posedge clk) begin
@ -129,20 +129,16 @@ module VX_axi_adapter #(
wire axi_write_ready [NUM_BANKS];
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_ready
assign axi_write_ready[i] = (m_axi_awready[i] || m_axi_aw_ack[i])
&& (m_axi_wready[i] || m_axi_w_ack[i]);
end
// Vortex request ack
if (NUM_BANKS > 1) begin
assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel];
end else begin
assign mem_req_ready = mem_req_rw ? axi_write_ready[0] : m_axi_arready[0];
end
// request ack
assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel];
// AXI write request address channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_addr
assign m_axi_awvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_aw_ack[i];
assign m_axi_awaddr[i] = (ADDR_WIDTH'(mem_req_addr) >> LOG2_NUM_BANKS) << AXSIZE;
assign m_axi_awid[i] = mem_req_tag;
@ -157,7 +153,7 @@ module VX_axi_adapter #(
end
// AXI write request data channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_data
assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_w_ack[i];
assign m_axi_wdata[i] = mem_req_data;
assign m_axi_wstrb[i] = mem_req_byteen;
@ -165,7 +161,7 @@ module VX_axi_adapter #(
end
// AXI write response channel (ignore)
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_rsp
`UNUSED_VAR (m_axi_bvalid[i])
`UNUSED_VAR (m_axi_bid[i])
`UNUSED_VAR (m_axi_bresp[i])
@ -174,7 +170,7 @@ module VX_axi_adapter #(
end
// AXI read request channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_read_req
assign m_axi_arvalid[i] = mem_req_valid && ~mem_req_rw && (req_bank_sel == i);
assign m_axi_araddr[i] = (ADDR_WIDTH'(mem_req_addr) >> LOG2_NUM_BANKS) << AXSIZE;
assign m_axi_arid[i] = mem_req_tag;
@ -196,7 +192,7 @@ module VX_axi_adapter #(
`UNUSED_VAR (m_axi_rlast)
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_read_rsp
assign rsp_arb_valid_in[i] = m_axi_rvalid[i];
assign rsp_arb_data_in[i] = {m_axi_rdata[i], m_axi_rid[i]};
assign m_axi_rready[i] = rsp_arb_ready_in[i];

20
hw/rtl/libs/VX_bits_insert.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -19,19 +19,19 @@ module VX_bits_insert #(
parameter S = 1,
parameter POS = 0
) (
input wire [N-1:0] data_in,
input wire [`UP(S)-1:0] ins_in,
input wire [N-1:0] data_in,
input wire [`UP(S)-1:0] ins_in,
output wire [N+S-1:0] data_out
);
if (S == 0) begin
);
if (S == 0) begin : g_passthru
`UNUSED_VAR (ins_in)
assign data_out = data_in;
end else begin
if (POS == 0) begin
end else begin : g_insert
if (POS == 0) begin : g_pos_0
assign data_out = {data_in, ins_in};
end else if (POS == N) begin
end else if (POS == N) begin : g_pos_N
assign data_out = {ins_in, data_in};
end else begin
end else begin : g_pos
assign data_out = {data_in[N-1:POS], ins_in, data_in[POS-1:0]};
end
end

18
hw/rtl/libs/VX_bits_remove.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -19,17 +19,19 @@ module VX_bits_remove #(
parameter S = 1,
parameter POS = 0
) (
input wire [N-1:0] data_in,
input wire [N-1:0] data_in,
output wire [N-S-1:0] data_out
);
`STATIC_ASSERT (((0 == S) || ((POS + S) <= N)), ("invalid parameter"))
if (POS == 0 || S == 0) begin
if (S == 0) begin : g_passthru
assign data_out = data_in;
end else if (POS == 0) begin : g_pos_0
assign data_out = data_in[N-1:S];
end else if ((POS + S) < N) begin
assign data_out = {data_in[N-1:(POS+S)], data_in[POS-1:0]};
end else begin
end else if ((POS + S) == N) begin : g_pos_N
assign data_out = data_in[POS-1:0];
end else begin : g_pos
assign data_out = {data_in[N-1:(POS+S)], data_in[POS-1:0]};
end
`UNUSED_VAR (data_in)

32
hw/rtl/libs/VX_bypass_buffer.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -25,30 +25,25 @@
module VX_bypass_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
);
if (PASSTHRU == 0) begin : g_buffer
reg [DATAW-1:0] buffer;
reg has_data;
always @(posedge clk) begin
if (reset) begin
has_data <= 0;
end else begin
end else begin
if (ready_out) begin
has_data <= 0;
end else if (~has_data) begin
@ -63,7 +58,16 @@ module VX_bypass_buffer #(
assign ready_in = ready_out || ~has_data;
assign data_out = has_data ? buffer : data_in;
assign valid_out = valid_in || has_data;
end
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else
endmodule
`TRACING_ON

4
hw/rtl/libs/VX_cyclic_arbiter.sv
View file

@ -26,7 +26,7 @@ module VX_cyclic_arbiter #(
output wire grant_valid,
input wire grant_ready
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -36,7 +36,7 @@ module VX_cyclic_arbiter #(
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
end else begin : g_arbiter
localparam IS_POW2 = (1 << LOG_NUM_REQS) == NUM_REQS;

4
hw/rtl/libs/VX_decoder.sv
View file

@ -27,14 +27,14 @@ module VX_decoder #(
input wire [M-1:0] valid_in,
output wire [D-1:0][M-1:0] data_out
);
if (MODEL == 1) begin
if (MODEL == 1) begin : g_model1
reg [D-1:0][M-1:0] data_out_w;
always @(*) begin
data_out_w = '0;
data_out_w[data_in] = valid_in;
end
assign data_out = data_out_w;
end else begin
end else begin : g_model0
assign data_out = (D*M)'(valid_in) << (data_in * M);
end

30
hw/rtl/libs/VX_divider.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -24,7 +24,7 @@ module VX_divider #(
parameter LATENCY = 0
) (
input wire clk,
input wire enable,
input wire enable,
input wire [N_WIDTH-1:0] numer,
input wire [D_WIDTH-1:0] denom,
output wire [Q_WIDTH-1:0] quotient,
@ -37,7 +37,7 @@ module VX_divider #(
wire [D_WIDTH-1:0] remainder_unqual;
lpm_divide divide (
.clock (clk),
.clock (clk),
.clken (enable),
.numer (numer),
.denom (denom),
@ -47,7 +47,7 @@ module VX_divider #(
defparam
divide.lpm_type = "LPM_DIVIDE",
divide.lpm_widthn = N_WIDTH,
divide.lpm_widthn = N_WIDTH,
divide.lpm_widthd = D_WIDTH,
divide.lpm_nrepresentation = N_SIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_drepresentation = D_SIGNED ? "SIGNED" : "UNSIGNED",
@ -62,36 +62,36 @@ module VX_divider #(
reg [N_WIDTH-1:0] quotient_unqual;
reg [D_WIDTH-1:0] remainder_unqual;
always @(*) begin
always @(*) begin
begin
if (N_SIGNED && D_SIGNED) begin
quotient_unqual = $signed(numer) / $signed(denom);
remainder_unqual = $signed(numer) % $signed(denom);
end
end
else if (N_SIGNED && !D_SIGNED) begin
quotient_unqual = $signed(numer) / denom;
remainder_unqual = $signed(numer) % denom;
end
end
else if (!N_SIGNED && D_SIGNED) begin
quotient_unqual = numer / $signed(denom);
remainder_unqual = numer % $signed(denom);
end
end
else begin
quotient_unqual = numer / denom;
remainder_unqual = numer % denom;
remainder_unqual = numer % denom;
end
end
end
if (LATENCY == 0) begin
if (LATENCY == 0) begin : g_comb
assign quotient = quotient_unqual [Q_WIDTH-1:0];
assign remainder = remainder_unqual [R_WIDTH-1:0];
end else begin
end else begin : g_pipe
reg [N_WIDTH-1:0] quotient_pipe [LATENCY-1:0];
reg [D_WIDTH-1:0] remainder_pipe [LATENCY-1:0];
for (genvar i = 0; i < LATENCY; ++i) begin
always @(posedge clk) begin
for (genvar i = 0; i < LATENCY; ++i) begin : g_reg
always @(posedge clk) begin
if (enable) begin
quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1];
remainder_pipe[i] <= (0 == i) ? remainder_unqual : remainder_pipe[i-1];
@ -101,7 +101,7 @@ module VX_divider #(
assign quotient = quotient_pipe[LATENCY-1][Q_WIDTH-1:0];
assign remainder = remainder_pipe[LATENCY-1][R_WIDTH-1:0];
end
end
`endif

72
hw/rtl/libs/VX_dp_ram.sv
View file

@ -44,10 +44,10 @@ module VX_dp_ram #(
`STATIC_ASSERT((WRENW * WSELW == DATAW), ("invalid parameter"))
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin \
if (INIT_FILE != "") begin \
if (INIT_ENABLE != 0) begin : g_init \
if (INIT_FILE != "") begin : g_file \
initial $readmemh(INIT_FILE, ram); \
end else begin \
end else begin : g_value \
initial begin \
for (integer i = 0; i < SIZE; ++i) \
ram[i] = INIT_VALUE; \
@ -58,17 +58,15 @@ module VX_dp_ram #(
`UNUSED_PARAM (RW_ASSERT)
`UNUSED_VAR (read)
if (WRENW > 1) begin
`RUNTIME_ASSERT(~write || (| wren), ("%t: invalid write enable mask", $time))
end
`RUNTIME_ASSERT((((WRENW == 1) ) || ~write) || (| wren), ("%t: invalid write enable mask", $time))
if (OUT_REG && !READ_ENABLE) begin
if (OUT_REG && !READ_ENABLE) begin : g_out_reg
`UNUSED_PARAM (NO_RWCHECK)
reg [DATAW-1:0] rdata_r;
wire cs = read || write;
if (WRENW != 1) begin
if (WRENW != 1) begin : g_writeen
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -86,7 +84,7 @@ module VX_dp_ram #(
end
end
end
end else begin
end else begin : g_no_lutram
reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -107,7 +105,7 @@ module VX_dp_ram #(
end
`else
// default synthesis
if (LUTRAM != 0) begin
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -125,7 +123,7 @@ module VX_dp_ram #(
end
end
end
end else begin
end else begin : g_no_lutram
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -145,8 +143,8 @@ module VX_dp_ram #(
end
end
`endif
end else begin
if (LUTRAM != 0) begin
end else begin : g_no_writeen
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -161,7 +159,7 @@ module VX_dp_ram #(
end
end
end else begin
end else begin : g_no_lutram
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -178,13 +176,13 @@ module VX_dp_ram #(
end
end
assign rdata = rdata_r;
end else begin
end else begin : g_no_out_reg
// OUT_REG==0 || READ_ENABLE=1
wire [DATAW-1:0] rdata_w;
`ifdef SYNTHESIS
if (WRENW > 1) begin
if (WRENW > 1) begin : g_writeen
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -196,8 +194,8 @@ module VX_dp_ram #(
end
end
assign rdata_w = ram[raddr];
end else begin
if (NO_RWCHECK != 0) begin
end else begin : g_no_lutram
if (NO_RWCHECK != 0) begin : g_no_rwcheck
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -209,7 +207,7 @@ module VX_dp_ram #(
end
end
assign rdata_w = ram[raddr];
end else begin
end else begin : g_rwcheck
reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -225,7 +223,7 @@ module VX_dp_ram #(
end
`else
// default synthesis
if (LUTRAM != 0) begin
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -237,8 +235,8 @@ module VX_dp_ram #(
end
end
assign rdata_w = ram[raddr];
end else begin
if (NO_RWCHECK != 0) begin
end else begin : g_no_lutram
if (NO_RWCHECK != 0) begin : g_no_rwcheck
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -250,7 +248,7 @@ module VX_dp_ram #(
end
end
assign rdata_w = ram[raddr];
end else begin
end else begin : g_rwcheck
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -265,9 +263,9 @@ module VX_dp_ram #(
end
end
`endif
end else begin
end else begin : g_no_writeen
// (WRENW == 1)
if (LUTRAM != 0) begin
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -276,8 +274,8 @@ module VX_dp_ram #(
end
end
assign rdata_w = ram[raddr];
end else begin
if (NO_RWCHECK != 0) begin
end else begin : g_no_lutram
if (NO_RWCHECK != 0) begin : g_no_rwcheck
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -286,7 +284,7 @@ module VX_dp_ram #(
end
end
assign rdata_w = ram[raddr];
end else begin
end else begin : g_rwcheck
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
@ -304,7 +302,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
wire [DATAW-1:0] ram_n;
for (genvar i = 0; i < WRENW; ++i) begin
for (genvar i = 0; i < WRENW; ++i) begin : g_ram_n
assign ram_n[i * WSELW +: WSELW] = ((WRENW == 1) | wren[i]) ? wdata[i * WSELW +: WSELW] : ram[waddr][i * WSELW +: WSELW];
end
@ -320,9 +318,7 @@ module VX_dp_ram #(
end
end
if (LUTRAM || !NO_RWCHECK) begin
assign rdata_w = ram[raddr];
end else begin
if (!LUTRAM && NO_RWCHECK) begin : g_rdata_no_bypass
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
@ -340,13 +336,15 @@ module VX_dp_ram #(
end
assign rdata_w = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
if (RW_ASSERT) begin
if (RW_ASSERT) begin : g_rw_assert
`RUNTIME_ASSERT(~read || (rdata_w == ram[raddr]), ("%t: read after write hazard", $time))
end
end else begin : g_rdata_with_bypass
assign rdata_w = ram[raddr];
end
`endif
if (OUT_REG != 0) begin
if (OUT_REG != 0) begin : g_rdata_req
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (READ_ENABLE && reset) begin
@ -356,7 +354,7 @@ module VX_dp_ram #(
end
end
assign rdata = rdata_r;
end else begin
end else begin : g_rdata_comb
assign rdata = rdata_w;
end

8
hw/rtl/libs/VX_elastic_buffer.sv
View file

@ -31,7 +31,7 @@ module VX_elastic_buffer #(
input wire ready_out,
output wire valid_out
);
if (SIZE == 0) begin
if (SIZE == 0) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -40,7 +40,7 @@ module VX_elastic_buffer #(
assign data_out = data_in;
assign ready_in = ready_out;
end else if (SIZE == 1) begin
end else if (SIZE == 1) begin : g_eb1
VX_pipe_buffer #(
.DATAW (DATAW),
@ -56,7 +56,7 @@ module VX_elastic_buffer #(
.ready_out (ready_out)
);
end else if (SIZE == 2 && LUTRAM == 0) begin
end else if (SIZE == 2 && LUTRAM == 0) begin : g_eb2
wire valid_out_t;
wire [DATAW-1:0] data_out_t;
@ -90,7 +90,7 @@ module VX_elastic_buffer #(
.ready_out (ready_out)
);
end else begin
end else begin : g_ebN
wire empty, full;

28
hw/rtl/libs/VX_encoder.sv
View file

@ -27,17 +27,17 @@ module VX_encoder #(
output wire [LN-1:0] data_out,
output wire valid_out
);
if (N == 1) begin
if (N == 1) begin : g_n1
assign data_out = 0;
assign valid_out = data_in;
end else if (N == 2) begin
end else if (N == 2) begin : g_n2
assign data_out = data_in[!REVERSE];
assign valid_out = (| data_in);
end else if (MODEL == 1) begin
end else if (MODEL == 1) begin : g_model1
localparam M = 1 << LN;
`IGNORE_UNOPTFLAT_BEGIN
wire [LN-1:0][M-1:0] addr;
@ -47,21 +47,19 @@ module VX_encoder #(
// base case, also handle padding for non-power of two inputs
assign v[0] = REVERSE ? (M'(data_in) << (M - N)) : M'(data_in);
for (genvar lvl = 1; lvl < (LN+1); ++lvl) begin
for (genvar lvl = 1; lvl < (LN+1); ++lvl) begin : g_scan_l
localparam SN = 1 << (LN - lvl);
localparam SI = M / SN;
localparam SW = lvl;
for (genvar s = 0; s < SN; ++s) begin
for (genvar s = 0; s < SN; ++s) begin : g_scan_s
`IGNORE_UNOPTFLAT_BEGIN
wire [1:0] vs = {v[lvl-1][s*SI+(SI>>1)], v[lvl-1][s*SI]};
`IGNORE_UNOPTFLAT_END
assign v[lvl][s*SI] = (| vs);
if (lvl == 1) begin
if (lvl == 1) begin : g_lvl_1
assign addr[lvl-1][s*SI +: SW] = vs[!REVERSE];
end else begin
end else begin : g_lvl_n
assign addr[lvl-1][s*SI +: SW] = {
vs[!REVERSE],
addr[lvl-2][s*SI +: SW-1] | addr[lvl-2][s*SI+(SI>>1) +: SW-1]
@ -73,11 +71,11 @@ module VX_encoder #(
assign data_out = addr[LN-1][LN-1:0];
assign valid_out = v[LN][0];
end else if (MODEL == 2 && REVERSE == 0) begin
end else if (MODEL == 2 && REVERSE == 0) begin : g_model2
for (genvar j = 0; j < LN; ++j) begin
for (genvar j = 0; j < LN; ++j) begin : g_data_out
wire [N-1:0] mask;
for (genvar i = 0; i < N; ++i) begin
for (genvar i = 0; i < N; ++i) begin : g_mask
assign mask[i] = i[j];
end
assign data_out[j] = | (mask & data_in);
@ -85,11 +83,11 @@ module VX_encoder #(
assign valid_out = (| data_in);
end else begin
end else begin : g_model0
reg [LN-1:0] index_w;
if (REVERSE != 0) begin
if (REVERSE != 0) begin : g_msb
always @(*) begin
index_w = 'x;
for (integer i = N-1; i >= 0; --i) begin
@ -98,7 +96,7 @@ module VX_encoder #(
end
end
end
end else begin
end else begin : g_lsb
always @(*) begin
index_w = 'x;
for (integer i = 0; i < N; ++i) begin

8
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -58,7 +58,7 @@ module VX_fifo_queue #(
.size (size)
);
if (DEPTH == 1) begin
if (DEPTH == 1) begin : g_depth_1
reg [DATAW-1:0] head_r;
@ -70,11 +70,11 @@ module VX_fifo_queue #(
assign data_out = head_r;
end else begin
end else begin : g_depth_n
localparam ADDRW = `CLOG2(DEPTH);
if (OUT_REG != 0) begin
if (OUT_REG != 0) begin : g_out_reg
wire [DATAW-1:0] dout;
reg [DATAW-1:0] dout_r;
@ -128,7 +128,7 @@ module VX_fifo_queue #(
assign data_out = dout_r;
end else begin
end else begin : g_no_out_reg
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r;

10
hw/rtl/libs/VX_find_first.sv
View file

@ -33,20 +33,20 @@ module VX_find_first #(
wire [TN-1:0][DATAW-1:0] d_n;
`IGNORE_WARNINGS_END
for (genvar i = 0; i < N; ++i) begin
for (genvar i = 0; i < N; ++i) begin : g_reverse
assign s_n[TL+i] = REVERSE ? valid_in[N-1-i] : valid_in[i];
assign d_n[TL+i] = REVERSE ? data_in[N-1-i] : data_in[i];
end
if (TL < (TN-N)) begin
for (genvar i = TL+N; i < TN; ++i) begin
if (TL < (TN-N)) begin : g_fill
for (genvar i = TL+N; i < TN; ++i) begin : g_i
assign s_n[i] = 0;
assign d_n[i] = '0;
end
end
for (genvar j = 0; j < LOGN; ++j) begin
for (genvar i = 0; i < (2**j); ++i) begin
for (genvar j = 0; j < LOGN; ++j) begin : g_scan
for (genvar i = 0; i < (2**j); ++i) begin : g_i
assign s_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] | s_n[2**(j+1)-1+i*2+1];
assign d_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] ? d_n[2**(j+1)-1+i*2] : d_n[2**(j+1)-1+i*2+1];
end

10
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -27,7 +27,7 @@ module VX_generic_arbiter #(
output wire grant_valid,
input wire grant_ready
);
if (TYPE == "P") begin
if (TYPE == "P") begin : g_priority
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -42,7 +42,7 @@ module VX_generic_arbiter #(
.grant_onehot (grant_onehot)
);
end else if (TYPE == "R") begin
end else if (TYPE == "R") begin : g_round_robin
VX_rr_arbiter #(
.NUM_REQS (NUM_REQS)
@ -56,7 +56,7 @@ module VX_generic_arbiter #(
.grant_ready (grant_ready)
);
end else if (TYPE == "M") begin
end else if (TYPE == "M") begin : g_matrix
VX_matrix_arbiter #(
.NUM_REQS (NUM_REQS)
@ -70,7 +70,7 @@ module VX_generic_arbiter #(
.grant_ready (grant_ready)
);
end else if (TYPE == "C") begin
end else if (TYPE == "C") begin : g_cyclic
VX_cyclic_arbiter #(
.NUM_REQS (NUM_REQS)
@ -84,7 +84,7 @@ module VX_generic_arbiter #(
.grant_ready (grant_ready)
);
end else begin
end else begin : g_invalid
`ERROR(("invalid parameter"));

14
hw/rtl/libs/VX_lzc.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -23,18 +23,18 @@ module VX_lzc #(
output wire [LOGN-1:0] data_out,
output wire valid_out
);
if (N == 1) begin
if (N == 1) begin : g_passthru
`UNUSED_PARAM (REVERSE)
assign data_out = '0;
assign valid_out = data_in;
end else begin
end else begin : g_lzc
wire [N-1:0][LOGN-1:0] indices;
for (genvar i = 0; i < N; ++i) begin
for (genvar i = 0; i < N; ++i) begin : g_indices
assign indices[i] = REVERSE ? LOGN'(i) : LOGN'(N-1-i);
end
@ -42,7 +42,7 @@ module VX_lzc #(
.N (N),
.DATAW (LOGN),
.REVERSE (!REVERSE)
) find_first (
) find_first (
.data_in (indices),
.valid_in (data_in),
.data_out (data_out),
@ -50,6 +50,6 @@ module VX_lzc #(
);
end
endmodule
`TRACING_ON

22
hw/rtl/libs/VX_matrix_arbiter.sv
View file

@ -26,7 +26,7 @@ module VX_matrix_arbiter #(
output wire grant_valid,
input wire grant_ready
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -36,32 +36,30 @@ module VX_matrix_arbiter #(
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
end else begin : g_arbiter
reg [NUM_REQS-1:1] state [NUM_REQS-1:0];
wire [NUM_REQS-1:0] pri [NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant;
for (genvar r = 0; r < NUM_REQS; ++r) begin
for (genvar c = 0; c < NUM_REQS; ++c) begin
if (r > c) begin
for (genvar r = 0; r < NUM_REQS; ++r) begin : g_pri_r
for (genvar c = 0; c < NUM_REQS; ++c) begin : g_pri_c
if (r > c) begin : g_row
assign pri[r][c] = requests[c] && state[c][r];
end
else if (r < c) begin
end else if (r < c) begin : g_col
assign pri[r][c] = requests[c] && !state[r][c];
end
else begin
end else begin : g_equal
assign pri[r][c] = 0;
end
end
end
for (genvar r = 0; r < NUM_REQS; ++r) begin
for (genvar r = 0; r < NUM_REQS; ++r) begin : g_grant
assign grant[r] = requests[r] && ~(| pri[r]);
end
for (genvar r = 0; r < NUM_REQS; ++r) begin
for (genvar c = r + 1; c < NUM_REQS; ++c) begin
for (genvar r = 0; r < NUM_REQS; ++r) begin : g_state_r
for (genvar c = r + 1; c < NUM_REQS; ++c) begin : g_state_c
always @(posedge clk) begin
if (reset) begin
state[r][c] <= '0;

24
hw/rtl/libs/VX_mem_adapter.sv
View file

@ -76,7 +76,7 @@ module VX_mem_adapter #(
`UNUSED_VAR (mem_rsp_tag_out)
if (DST_LDATAW > SRC_LDATAW) begin
if (DST_LDATAW > SRC_LDATAW) begin : g_wider_dst_data
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -88,12 +88,12 @@ module VX_mem_adapter #(
wire [P-1:0][SRC_DATA_WIDTH-1:0] mem_rsp_data_out_w = mem_rsp_data_out;
if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH - D)) begin
if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH - D)) begin : g_mem_req_addr_out_w_src
`UNUSED_VAR (mem_req_addr_in_qual)
assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0];
end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH - D)) begin
end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH - D)) begin : g_mem_req_addr_out_w_dst
assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual);
end else begin
end else begin : g_mem_req_addr_out_w
assign mem_req_addr_out_w = mem_req_addr_in_qual;
end
@ -125,7 +125,7 @@ module VX_mem_adapter #(
assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out[SRC_TAG_WIDTH+D-1:D]);
assign mem_rsp_ready_out = mem_rsp_ready_in_w;
end else if (DST_LDATAW < SRC_LDATAW) begin
end else if (DST_LDATAW < SRC_LDATAW) begin : g_wider_src_data
reg [D-1:0] req_ctr, rsp_ctr;
@ -173,12 +173,12 @@ module VX_mem_adapter #(
wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr};
if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH + D)) begin
if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH + D)) begin : g_mem_req_addr_out_w_src
`UNUSED_VAR (mem_req_addr_in_qual)
assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0];
end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH + D)) begin
end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH + D)) begin : g_mem_req_addr_out_w_dst
assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual);
end else begin
end else begin : g_mem_req_addr_out_w
assign mem_req_addr_out_w = mem_req_addr_in_qual;
end
@ -194,17 +194,17 @@ module VX_mem_adapter #(
assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out);
assign mem_rsp_ready_out = mem_rsp_ready_in_w;
end else begin
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
if (DST_ADDR_WIDTH < SRC_ADDR_WIDTH) begin
if (DST_ADDR_WIDTH < SRC_ADDR_WIDTH) begin : g_mem_req_addr_out_w_src
`UNUSED_VAR (mem_req_addr_in)
assign mem_req_addr_out_w = mem_req_addr_in[DST_ADDR_WIDTH-1:0];
end else if (DST_ADDR_WIDTH > SRC_ADDR_WIDTH) begin
end else if (DST_ADDR_WIDTH > SRC_ADDR_WIDTH) begin : g_mem_req_addr_out_w_dst
assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in);
end else begin
end else begin : g_mem_req_addr_out_w
assign mem_req_addr_out_w = mem_req_addr_in;
end

37
hw/rtl/libs/VX_mem_coalescer.sv
View file

@ -115,11 +115,11 @@ module VX_mem_coalescer #(
logic [NUM_REQS-1:0] req_rem_mask_r, req_rem_mask_n;
wire [NUM_REQS-1:0][DATA_RATIO_W-1:0] in_addr_offset;
for (genvar i = 0; i < NUM_REQS; i++) begin
for (genvar i = 0; i < NUM_REQS; i++) begin : g_in_addr_offset
assign in_addr_offset[i] = in_req_addr[i][DATA_RATIO_W-1:0];
end
for (genvar i = 0; i < OUT_REQS; ++i) begin
for (genvar i = 0; i < OUT_REQS; ++i) begin : g_seed_gen
wire [DATA_RATIO-1:0] batch_mask;
wire [DATA_RATIO_W-1:0] batch_idx;
@ -135,16 +135,19 @@ module VX_mem_coalescer #(
);
wire [DATA_RATIO-1:0][OUT_ADDR_WIDTH-1:0] addr_base;
wire [DATA_RATIO-1:0][FLAGS_WIDTH-1:0] req_flags;
for (genvar j = 0; j < DATA_RATIO; ++j) begin
for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_addr_base
assign addr_base[j] = in_req_addr[DATA_RATIO * i + j][ADDR_WIDTH-1:DATA_RATIO_W];
end
wire [DATA_RATIO-1:0][FLAGS_WIDTH-1:0] req_flags;
for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_req_flags
assign req_flags[j] = in_req_flags[DATA_RATIO * i + j];
end
assign seed_addr_n[i] = addr_base[batch_idx];
assign seed_flags_n[i] = req_flags[batch_idx];
for (genvar j = 0; j < DATA_RATIO; ++j) begin
for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_addr_matches_n
assign addr_matches_n[i * DATA_RATIO + j] = (addr_base[j] == seed_addr_n[i]);
end
end
@ -291,15 +294,19 @@ module VX_mem_coalescer #(
assign {ibuf_dout_tag, ibuf_dout_pmask, ibuf_dout_offset} = ibuf_dout;
wire [NUM_REQS-1:0][DATA_IN_WIDTH-1:0] in_rsp_data_n;
wire [NUM_REQS-1:0] in_rsp_mask_n;
for (genvar i = 0; i < OUT_REQS; ++i) begin
for (genvar j = 0; j < DATA_RATIO; ++j) begin
assign in_rsp_mask_n[i * DATA_RATIO + j] = out_rsp_mask[i] && ibuf_dout_pmask[i * DATA_RATIO + j];
for (genvar i = 0; i < OUT_REQS; ++i) begin : g_in_rsp_data_n
for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_j
assign in_rsp_data_n[i * DATA_RATIO + j] = out_rsp_data[i][ibuf_dout_offset[i * DATA_RATIO + j] * DATA_IN_WIDTH +: DATA_IN_WIDTH];
end
end
wire [NUM_REQS-1:0] in_rsp_mask_n;
for (genvar i = 0; i < OUT_REQS; ++i) begin : g_in_rsp_mask_n
for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_j
assign in_rsp_mask_n[i * DATA_RATIO + j] = out_rsp_mask[i] && ibuf_dout_pmask[i * DATA_RATIO + j];
end
end
assign in_rsp_valid = out_rsp_valid;
assign in_rsp_mask = in_rsp_mask_n;
assign in_rsp_data = in_rsp_data_n;
@ -310,11 +317,15 @@ module VX_mem_coalescer #(
wire [`UP(UUID_WIDTH)-1:0] out_req_uuid;
wire [`UP(UUID_WIDTH)-1:0] out_rsp_uuid;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_out_req_uuid
assign out_req_uuid = out_req_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH];
assign out_rsp_uuid = out_rsp_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_out_req_uuid_0
assign out_req_uuid = '0;
end
if (UUID_WIDTH != 0) begin : g_out_rsp_uuid
assign out_rsp_uuid = out_rsp_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH];
end else begin : g_out_rsp_uuid_0
assign out_rsp_uuid = '0;
end

49
hw/rtl/libs/VX_mem_scheduler.sv
View file

@ -160,9 +160,9 @@ module VX_mem_scheduler #(
wire reqq_ready_in;
wire [REQQ_TAG_WIDTH-1:0] reqq_tag_u;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_reqq_tag_u_uuid
assign reqq_tag_u = {core_req_tag[TAG_WIDTH-1 -: UUID_WIDTH], ibuf_waddr};
end else begin
end else begin : g_reqq_tag_u
assign reqq_tag_u = ibuf_waddr;
end
@ -220,7 +220,7 @@ module VX_mem_scheduler #(
// Handle memory coalescing ///////////////////////////////////////////////
if (COALESCE_ENABLE) begin
if (COALESCE_ENABLE) begin : g_coalescer
VX_mem_coalescer #(
.INSTANCE_ID ($sformatf("%s-coalescer", INSTANCE_ID)),
@ -273,8 +273,7 @@ module VX_mem_scheduler #(
.out_rsp_ready (mem_rsp_ready)
);
end else begin
end else begin : g_no_coalescer
assign reqq_valid_s = reqq_valid;
assign reqq_mask_s = reqq_mask;
assign reqq_rw_s = reqq_rw;
@ -303,16 +302,16 @@ module VX_mem_scheduler #(
wire [BATCH_SEL_WIDTH-1:0] req_batch_idx;
for (genvar i = 0; i < MEM_BATCHES; ++i) begin
for (genvar j = 0; j < MEM_CHANNELS; ++j) begin
for (genvar i = 0; i < MEM_BATCHES; ++i) begin : g_mem_req_data_b
for (genvar j = 0; j < MEM_CHANNELS; ++j) begin : g_j
localparam r = i * MEM_CHANNELS + j;
if (r < MERGED_REQS) begin
if (r < MERGED_REQS) begin : g_valid
assign mem_req_mask_b[i][j] = reqq_mask_s[r];
assign mem_req_byteen_b[i][j] = reqq_byteen_s[r];
assign mem_req_addr_b[i][j] = reqq_addr_s[r];
assign mem_req_flags_b[i][j] = reqq_flags_s[r];
assign mem_req_data_b[i][j] = reqq_data_s[r];
end else begin
end else begin : g_extra
assign mem_req_mask_b[i][j] = 0;
assign mem_req_byteen_b[i][j] = '0;
assign mem_req_addr_b[i][j] = '0;
@ -329,7 +328,7 @@ module VX_mem_scheduler #(
assign mem_req_flags_s = mem_req_flags_b[req_batch_idx];
assign mem_req_data_s = mem_req_data_b[req_batch_idx];
if (MEM_BATCHES != 1) begin
if (MEM_BATCHES != 1) begin : g_batch
reg [MEM_BATCH_BITS-1:0] req_batch_idx_r;
wire is_degenerate_batch = ~(| mem_req_mask_s);
@ -354,7 +353,7 @@ module VX_mem_scheduler #(
wire [MEM_BATCHES-1:0][MEM_BATCH_BITS-1:0] req_batch_idxs;
wire [MEM_BATCH_BITS-1:0] req_batch_idx_last;
for (genvar i = 0; i < MEM_BATCHES; ++i) begin
for (genvar i = 0; i < MEM_BATCHES; ++i) begin : g_req_batch
assign req_batch_valids[i] = (| mem_req_mask_b[i]);
assign req_batch_idxs[i] = MEM_BATCH_BITS'(i);
end
@ -375,7 +374,7 @@ module VX_mem_scheduler #(
assign req_sent_all = mem_req_ready_b && (req_batch_idx_r == req_batch_idx_last);
assign mem_req_tag_s = {reqq_tag_s, req_batch_idx};
end else begin
end else begin : g_no_batch
assign mem_req_valid_s = reqq_valid_s;
assign req_batch_idx = '0;
@ -407,13 +406,13 @@ module VX_mem_scheduler #(
wire [CORE_REQS-1:0] rsp_rem_mask_n, curr_mask;
wire [BATCH_SEL_WIDTH-1:0] rsp_batch_idx;
if (CORE_BATCHES > 1) begin
if (CORE_BATCHES > 1) begin : g_rsp_batch_idx
assign rsp_batch_idx = mem_rsp_tag_s[CORE_BATCH_BITS-1:0];
end else begin
end else begin : g_rsp_batch_idx_0
assign rsp_batch_idx = '0;
end
for (genvar r = 0; r < CORE_REQS; ++r) begin
for (genvar r = 0; r < CORE_REQS; ++r) begin : g_curr_mask
localparam i = r / CORE_CHANNELS;
localparam j = r % CORE_CHANNELS;
assign curr_mask[r] = (BATCH_SEL_WIDTH'(i) == rsp_batch_idx) && mem_rsp_mask_s[j];
@ -434,7 +433,7 @@ module VX_mem_scheduler #(
end
end
if (RSP_PARTIAL != 0) begin
if (RSP_PARTIAL != 0) begin : g_rsp_partial
reg [CORE_QUEUE_SIZE-1:0] rsp_sop_r;
@ -451,14 +450,14 @@ module VX_mem_scheduler #(
assign crsp_mask = curr_mask;
assign crsp_sop = rsp_sop_r[ibuf_raddr];
for (genvar r = 0; r < CORE_REQS; ++r) begin
for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data
localparam j = r % CORE_CHANNELS;
assign crsp_data[r] = mem_rsp_data_s[j];
end
assign mem_rsp_ready_s = crsp_ready;
end else begin
end else begin : g_rsp_full
reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
reg [CORE_BATCHES-1:00][CORE_CHANNELS-1:0][WORD_WIDTH-1:0] rsp_store_n;
@ -486,7 +485,7 @@ module VX_mem_scheduler #(
assign crsp_mask = rsp_orig_mask[ibuf_raddr];
assign crsp_sop = 1'b1;
for (genvar r = 0; r < CORE_REQS; ++r) begin
for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data
localparam i = r / CORE_CHANNELS;
localparam j = r % CORE_CHANNELS;
assign crsp_data[r] = rsp_store_n[i][j];
@ -496,9 +495,9 @@ module VX_mem_scheduler #(
end
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_crsp_tag
assign crsp_tag = {mem_rsp_tag_s[MEM_TAG_WIDTH-1 -: UUID_WIDTH], ibuf_dout};
end else begin
end else begin : g_crsp_tag_0
assign crsp_tag = ibuf_dout;
end
@ -524,9 +523,9 @@ module VX_mem_scheduler #(
`ifdef SIMULATION
wire [`UP(UUID_WIDTH)-1:0] req_dbg_uuid;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_req_dbg_uuid
assign req_dbg_uuid = core_req_tag[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_req_dbg_uuid_0
assign req_dbg_uuid = '0;
end
@ -566,11 +565,11 @@ module VX_mem_scheduler #(
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_dbg_uuid;
wire [`UP(UUID_WIDTH)-1:0] rsp_dbg_uuid;
if (UUID_WIDTH != 0) begin
if (UUID_WIDTH != 0) begin : g_dbg_uuid
assign mem_req_dbg_uuid = mem_req_tag_s[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
assign mem_rsp_dbg_uuid = mem_rsp_tag_s[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
assign rsp_dbg_uuid = core_rsp_tag[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
end else begin : g_dbg_uuid_0
assign mem_req_dbg_uuid = '0;
assign mem_rsp_dbg_uuid = '0;
assign rsp_dbg_uuid = '0;

20
hw/rtl/libs/VX_multiplier.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -21,7 +21,7 @@ module VX_multiplier #(
parameter SIGNED = 0,
parameter LATENCY = 0
) (
input wire clk,
input wire clk,
input wire enable,
input wire [A_WIDTH-1:0] dataa,
input wire [B_WIDTH-1:0] datab,
@ -29,15 +29,15 @@ module VX_multiplier #(
);
wire [R_WIDTH-1:0] prod_w;
if (SIGNED != 0) begin
if (SIGNED != 0) begin : g_prod_s
assign prod_w = R_WIDTH'($signed(dataa) * $signed(datab));
end else begin
end else begin : g_prod_u
assign prod_w = R_WIDTH'(dataa * datab);
end
if (LATENCY == 0) begin
if (LATENCY == 0) begin : g_passthru
assign result = prod_w;
end else begin
end else begin : g_latency
reg [LATENCY-1:0][R_WIDTH-1:0] prod_r;
always @(posedge clk) begin
if (enable) begin
@ -46,8 +46,8 @@ module VX_multiplier #(
prod_r[i] <= prod_r[i-1];
end
end
end
assign result = prod_r[LATENCY-1];
end
assign result = prod_r[LATENCY-1];
end
endmodule

14
hw/rtl/libs/VX_mux.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -19,13 +19,13 @@ module VX_mux #(
parameter N = 1,
parameter LN = `LOG2UP(N)
) (
input wire [N-1:0][DATAW-1:0] data_in,
input wire [LN-1:0] sel_in,
input wire [N-1:0][DATAW-1:0] data_in,
input wire [LN-1:0] sel_in,
output wire [DATAW-1:0] data_out
);
if (N > 1) begin
);
if (N > 1) begin : g_mux
assign data_out = data_in[sel_in];
end else begin
end else begin : g_passthru
`UNUSED_VAR (sel_in)
assign data_out = data_in;
end

28
hw/rtl/libs/VX_onehot_mux.sv
View file

@ -24,13 +24,13 @@ module VX_onehot_mux #(
input wire [N-1:0] sel_in,
output wire [DATAW-1:0] data_out
);
if (N == 1) begin
if (N == 1) begin : g_passthru
`UNUSED_VAR (sel_in)
assign data_out = data_in;
end else if (LUT_OPT && N == 2) begin
end else if (LUT_OPT && N == 2) begin : g_lut2
`UNUSED_VAR (sel_in)
assign data_out = sel_in[0] ? data_in[0] : data_in[1];
end else if (LUT_OPT && N == 3) begin
end else if (LUT_OPT && N == 3) begin : g_lut3
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
@ -41,7 +41,7 @@ module VX_onehot_mux #(
endcase
end
assign data_out = data_out_w;
end else if (LUT_OPT && N == 4) begin
end else if (LUT_OPT && N == 4) begin : g_lut4
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
@ -53,7 +53,7 @@ module VX_onehot_mux #(
endcase
end
assign data_out = data_out_w;
end else if (LUT_OPT && N == 5) begin
end else if (LUT_OPT && N == 5) begin : g_lut5
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
@ -66,7 +66,7 @@ module VX_onehot_mux #(
endcase
end
assign data_out = data_out_w;
end else if (LUT_OPT && N == 6) begin
end else if (LUT_OPT && N == 6) begin : g_lut6
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
@ -80,7 +80,7 @@ module VX_onehot_mux #(
endcase
end
assign data_out = data_out_w;
end else if (LUT_OPT && N == 7) begin
end else if (LUT_OPT && N == 7) begin : g_lut7
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
@ -95,7 +95,7 @@ module VX_onehot_mux #(
endcase
end
assign data_out = data_out_w;
end else if (LUT_OPT && N == 8) begin
end else if (LUT_OPT && N == 8) begin : g_lut8
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
@ -111,19 +111,19 @@ module VX_onehot_mux #(
endcase
end
assign data_out = data_out_w;
end else if (MODEL == 1) begin
end else if (MODEL == 1) begin : g_model1
wire [N-1:0][DATAW-1:0] mask;
for (genvar i = 0; i < N; ++i) begin
for (genvar i = 0; i < N; ++i) begin : g_mask
assign mask[i] = {DATAW{sel_in[i]}} & data_in[i];
end
for (genvar i = 0; i < DATAW; ++i) begin
for (genvar i = 0; i < DATAW; ++i) begin : g_data_out
wire [N-1:0] gather;
for (genvar j = 0; j < N; ++j) begin
for (genvar j = 0; j < N; ++j) begin : g_gather
assign gather[j] = mask[j][i];
end
assign data_out[i] = (| gather);
end
end else if (MODEL == 2) begin
end else if (MODEL == 2) begin : g_model2
VX_find_first #(
.N (N),
.DATAW (DATAW)
@ -133,7 +133,7 @@ module VX_onehot_mux #(
.data_out (data_out),
`UNUSED_PIN (valid_out)
);
end else if (MODEL == 3) begin
end else if (MODEL == 3) begin : g_model3
reg [DATAW-1:0] data_out_w;
always @(*) begin
data_out_w = 'x;

4
hw/rtl/libs/VX_onehot_shift.sv
View file

@ -22,8 +22,8 @@ module VX_onehot_shift #(
input wire [M-1:0] data_in1,
output wire [N*M-1:0] data_out
);
for (genvar i = 0; i < M; ++i) begin
for (genvar j = 0; j < N; ++j) begin
for (genvar i = 0; i < M; ++i) begin : g_i
for (genvar j = 0; j < N; ++j) begin : g_j
assign data_out[i*N + j] = data_in1[i] & data_in0[j];
end
end

6
hw/rtl/libs/VX_pe_serializer.sv
View file

@ -79,7 +79,7 @@ module VX_pe_serializer #(
assign pe_enable = enable;
if (NUM_LANES != NUM_PES) begin
if (NUM_LANES != NUM_PES) begin : g_serialize
localparam BATCH_SIZE = NUM_LANES / NUM_PES;
localparam BATCH_SIZEW = `LOG2UP(BATCH_SIZE);
@ -87,7 +87,7 @@ module VX_pe_serializer #(
reg [BATCH_SIZEW-1:0] batch_in_idx, batch_out_idx;
reg batch_in_done, batch_out_done;
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : g_pe_data_out_w
assign pe_data_out_w[i] = data_in[batch_in_idx * NUM_PES + i];
end
@ -125,7 +125,7 @@ module VX_pe_serializer #(
assign data_out_u = data_out_n;
assign tag_out_u = pe_tag_in;
end else begin
end else begin : g_passthru
assign pe_data_out_w = data_in;

12
hw/rtl/libs/VX_pending_size.sv
View file

@ -35,7 +35,7 @@ module VX_pending_size #(
`STATIC_ASSERT(INCRW <= SIZEW, ("invalid parameter: %d vs %d", INCRW, SIZEW))
`STATIC_ASSERT(DECRW <= SIZEW, ("invalid parameter: %d vs %d", DECRW, SIZEW))
if (SIZE == 1) begin
if (SIZE == 1) begin : g_size1
reg size_r;
@ -59,12 +59,12 @@ module VX_pending_size #(
assign alm_full = 1'b1;
assign size = size_r;
end else begin
end else begin : g_sizeN
reg empty_r, alm_empty_r;
reg full_r, alm_full_r;
if (INCRW != 1 || DECRW != 1) begin
if (INCRW != 1 || DECRW != 1) begin : g_wide_step
localparam SUBW = `MIN(SIZEW, `MAX(INCRW, DECRW)+1);
@ -92,7 +92,7 @@ module VX_pending_size #(
assign size = size_r;
end else begin
end else begin : g_single_step
localparam ADDRW = `LOG2UP(SIZE);
@ -124,7 +124,7 @@ module VX_pending_size #(
end
end
if (SIZE > 2) begin
if (SIZE > 2) begin : g_sizeN
wire is_empty_n = (used_r == ADDRW'(1));
wire is_full_n = (used_r == ADDRW'(SIZE-1));
@ -152,7 +152,7 @@ module VX_pending_size #(
end
end
end else begin
end else begin : g_size2
always @(posedge clk) begin
if (reset) begin

6
hw/rtl/libs/VX_pipe_buffer.sv
View file

@ -37,13 +37,13 @@ module VX_pipe_buffer #(
input wire ready_out,
output wire valid_out
);
if (DEPTH == 0) begin
if (DEPTH == 0) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
end else begin : g_register
wire [DEPTH:0] valid;
`IGNORE_UNOPTFLAT_BEGIN
wire [DEPTH:0] ready;
@ -54,7 +54,7 @@ module VX_pipe_buffer #(
assign data[0] = data_in;
assign ready_in = ready[0];
for (genvar i = 0; i < DEPTH; ++i) begin
for (genvar i = 0; i < DEPTH; ++i) begin : g_pipe_regs
assign ready[i] = (ready[i+1] || ~valid[i+1]);
VX_pipe_register #(
.DATAW (1 + DATAW),

36
hw/rtl/libs/VX_pipe_register.sv
View file

@ -26,13 +26,13 @@ module VX_pipe_register #(
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (DEPTH == 0) begin
if (DEPTH == 0) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)
assign data_out = data_in;
end else if (DEPTH == 1) begin
if (RESETW == 0) begin
end else if (DEPTH == 1) begin : g_depth1
if (RESETW == 0) begin : g_no_reset
`UNUSED_VAR (reset)
reg [DATAW-1:0] value;
@ -42,18 +42,7 @@ module VX_pipe_register #(
end
end
assign data_out = value;
end else if (RESETW == DATAW) begin
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (reset) begin
value <= INIT_VALUE;
end else if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end else begin
end else if (RESETW < DATAW) begin : g_partial_reset
reg [DATAW-RESETW-1:0] value_d;
reg [RESETW-1:0] value_r;
@ -71,12 +60,23 @@ module VX_pipe_register #(
end
end
assign data_out = {value_r, value_d};
end else begin : g_full_reset
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (reset) begin
value <= INIT_VALUE;
end else if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end
end else begin
end else begin : g_recursive
wire [DEPTH:0][DATAW-1:0] data_delayed;
assign data_delayed[0] = data_in;
for (genvar i = 1; i <= DEPTH; ++i) begin
for (genvar i = 1; i <= DEPTH; ++i) begin : g_pipe_reg
VX_pipe_register #(
.DATAW (DATAW),
.RESETW (RESETW),

16
hw/rtl/libs/VX_popcount.sv
View file

@ -100,11 +100,11 @@ module VX_popcount #(
`elsif QUARTUS
assign data_out = $countones(data_in);
`else
if (N == 1) begin
if (N == 1) begin : g_passthru
assign data_out = data_in;
end else if (N <= 3) begin
end else if (N <= 3) begin : g_popcount3
reg [2:0] t_in;
wire [1:0] t_out;
@ -115,7 +115,7 @@ module VX_popcount #(
VX_popcount32 pc32(t_in, t_out);
assign data_out = t_out[M-1:0];
end else if (N <= 6) begin
end else if (N <= 6) begin : g_popcount6
reg [5:0] t_in;
wire [2:0] t_out;
@ -126,7 +126,7 @@ module VX_popcount #(
VX_popcount63 pc63(t_in, t_out);
assign data_out = t_out[M-1:0];
end else if (N <= 9) begin
end else if (N <= 9) begin : g_popcount9
reg [8:0] t_in;
wire [4:0] t1_out;
@ -140,7 +140,7 @@ module VX_popcount #(
VX_sum33 sum33(t1_out[2:0], {1'b0, t1_out[4:3]}, t2_out);
assign data_out = t2_out[M-1:0];
end else if (N <= 12) begin
end else if (N <= 12) begin : g_popcount12
reg [11:0] t_in;
wire [5:0] t1_out;
@ -154,7 +154,7 @@ module VX_popcount #(
VX_sum33 sum33(t1_out[2:0], t1_out[5:3], t2_out);
assign data_out = t2_out[M-1:0];
end else if (N <= 18) begin
end else if (N <= 18) begin : g_popcount18
reg [17:0] t_in;
wire [8:0] t1_out;
@ -171,7 +171,7 @@ module VX_popcount #(
VX_popcount32 pc32c({t1_out[2], t1_out[5], t1_out[8]}, t2_out[5:4]);
assign data_out = {2'b0,t2_out[1:0]} + {1'b0,t2_out[3:2],1'b0} + {t2_out[5:4],2'b0};
end else if (MODEL == 1) begin
end else if (MODEL == 1) begin : g_model1
localparam PN = 1 << `CLOG2(N);
localparam LOGPN = `CLOG2(PN);
@ -204,7 +204,7 @@ module VX_popcount #(
assign data_out = tmp[LOGPN-1][0];
end else begin
end else begin : g_model2
reg [M-1:0] cnt_w;

4
hw/rtl/libs/VX_priority_arbiter.sv
View file

@ -23,13 +23,13 @@ module VX_priority_arbiter #(
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin : g_passthru
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
end else begin : g_encoder
VX_priority_encoder #(
.N (NUM_REQS)

20
hw/rtl/libs/VX_priority_encoder.sv
View file

@ -27,34 +27,34 @@ module VX_priority_encoder #(
);
wire [N-1:0] reversed;
if (REVERSE != 0) begin
for (genvar i = 0; i < N; ++i) begin
if (REVERSE != 0) begin : g_reverse
for (genvar i = 0; i < N; ++i) begin : g_i
assign reversed[N-i-1] = data_in[i];
end
end else begin
end else begin : g_no_reverse
assign reversed = data_in;
end
if (N == 1) begin
if (N == 1) begin : g_n1
assign onehot_out = reversed;
assign index_out = '0;
assign valid_out = reversed;
end else if (N == 2) begin
end else if (N == 2) begin : g_n2
assign onehot_out = {reversed[1] && ~reversed[0], reversed[0]};
assign index_out = ~reversed[0];
assign valid_out = (| reversed);
end else if (MODEL == 1) begin
end else if (MODEL == 1) begin : g_model1
`IGNORE_UNOPTFLAT_BEGIN
wire [N-1:0] higher_pri_regs;
`IGNORE_UNOPTFLAT_END
assign higher_pri_regs[0] = 1'b0;
for (genvar i = 1; i < N; ++i) begin
for (genvar i = 1; i < N; ++i) begin : g_higher_pri_regs
assign higher_pri_regs[i] = higher_pri_regs[i-1] | reversed[i-1];
end
assign onehot_out[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
@ -68,7 +68,7 @@ module VX_priority_encoder #(
.valid_out (valid_out)
);
end else if (MODEL == 2) begin
end else if (MODEL == 2) begin : g_model2
wire [N-1:0] scan_lo;
@ -91,7 +91,7 @@ module VX_priority_encoder #(
assign onehot_out = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
end else if (MODEL == 3) begin
end else if (MODEL == 3) begin : g_model3
assign onehot_out = reversed & -reversed;
@ -104,7 +104,7 @@ module VX_priority_encoder #(
.valid_out (valid_out)
);
end else begin
end else begin : g_model0
reg [LN-1:0] index_w;
reg [N-1:0] onehot_w;

40
hw/rtl/libs/VX_reduce.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -14,7 +14,7 @@
`include "VX_platform.vh"
`TRACING_OFF
module VX_reduce #(
module VX_reduce #(
parameter DATAW_IN = 1,
parameter DATAW_OUT = DATAW_IN,
parameter N = 1,
@ -23,9 +23,9 @@ module VX_reduce #(
input wire [N-1:0][DATAW_IN-1:0] data_in,
output wire [DATAW_OUT-1:0] data_out
);
if (N == 1) begin
if (N == 1) begin : g_passthru
assign data_out = DATAW_OUT'(data_in[0]);
end else begin
end else begin : g_reduce
localparam int N_A = N / 2;
localparam int N_B = N - N_A;
@ -33,40 +33,46 @@ module VX_reduce #(
wire [N_B-1:0][DATAW_IN-1:0] in_B;
wire [DATAW_OUT-1:0] out_A, out_B;
for (genvar i = 0; i < N_A; i++) begin
for (genvar i = 0; i < N_A; i++) begin : g_in_A
assign in_A[i] = data_in[i];
end
for (genvar i = 0; i < N_B; i++) begin
for (genvar i = 0; i < N_B; i++) begin : g_in_B
assign in_B[i] = data_in[N_A + i];
end
VX_reduce #(
.DATAW_IN (DATAW_IN),
.DATAW_IN (DATAW_IN),
.DATAW_OUT (DATAW_OUT),
.N (N_A),
.OP (OP)
) reduce_A (
.data_in (in_A),
.data_in (in_A),
.data_out (out_A)
);
VX_reduce #(
.DATAW_IN (DATAW_IN),
.DATAW_IN (DATAW_IN),
.DATAW_OUT (DATAW_OUT),
.N (N_B),
.OP (OP)
) reduce_B (
.data_in (in_B),
.data_in (in_B),
.data_out (out_B)
);
if (OP == "+") assign data_out = out_A + out_B;
else if (OP == "^") assign data_out = out_A ^ out_B;
else if (OP == "&") assign data_out = out_A & out_B;
else if (OP == "|") assign data_out = out_A | out_B;
else `ERROR(("invalid parameter"));
if (OP == "+") begin : g_plus
assign data_out = out_A + out_B;
end else if (OP == "^") begin : g_xor
assign data_out = out_A ^ out_B;
end else if (OP == "&") begin : g_and
assign data_out = out_A & out_B;
end else if (OP == "|") begin : g_or
assign data_out = out_A | out_B;
end else begin : g_error
`ERROR(("invalid parameter"));
end
end
endmodule
`TRACING_ON

8
hw/rtl/libs/VX_reset_relay.sv
View file

@ -22,19 +22,19 @@ module VX_reset_relay #(
input wire reset,
output wire [N-1:0] reset_o
);
if (MAX_FANOUT >= 0 && N > (MAX_FANOUT + MAX_FANOUT/2)) begin
if (MAX_FANOUT >= 0 && N > (MAX_FANOUT + MAX_FANOUT/2)) begin : g_relay
localparam F = `UP(MAX_FANOUT);
localparam R = N / F;
`PRESERVE_NET reg [R-1:0] reset_r;
for (genvar i = 0; i < R; ++i) begin
for (genvar i = 0; i < R; ++i) begin : g_reset_r
always @(posedge clk) begin
reset_r[i] <= reset;
end
end
for (genvar i = 0; i < N; ++i) begin
for (genvar i = 0; i < N; ++i) begin : g_reset_o
assign reset_o[i] = reset_r[i / F];
end
end else begin
end else begin : g_passthru
`UNUSED_VAR (clk)
assign reset_o = {N{reset}};
end

26
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -28,7 +28,7 @@ module VX_rr_arbiter #(
output wire grant_valid,
input wire grant_ready
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -38,7 +38,7 @@ module VX_rr_arbiter #(
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else if (LUT_OPT && NUM_REQS == 2) begin
end else if (LUT_OPT && NUM_REQS == 2) begin : g_lut2
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -66,7 +66,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 3) begin
end else if (LUT_OPT && NUM_REQS == 3) begin : g_lut3
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -99,7 +99,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 4) begin
end else if (LUT_OPT && NUM_REQS == 4) begin : g_lut4
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -139,7 +139,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 5) begin
end else if (LUT_OPT && NUM_REQS == 5) begin : g_lut5
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -188,7 +188,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 6) begin
end else if (LUT_OPT && NUM_REQS == 6) begin : g_lut6
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -248,7 +248,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 7) begin
end else if (LUT_OPT && NUM_REQS == 7) begin : g_lut7
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -321,7 +321,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 8) begin
end else if (LUT_OPT && NUM_REQS == 8) begin : g_lut8
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [NUM_REQS-1:0] grant_onehot_w;
@ -409,7 +409,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_w;
assign grant_valid = (| requests);
end else if (MODEL == 1) begin
end else if (MODEL == 1) begin : g_model1
`IGNORE_UNOPTFLAT_BEGIN
wire [NUM_REQS-1:0] masked_pri_reqs, unmasked_pri_reqs;
@ -419,12 +419,12 @@ module VX_rr_arbiter #(
wire [NUM_REQS-1:0] masked_reqs = requests & reqs_mask;
assign masked_pri_reqs[0] = 1'b0;
for (genvar i = 1; i < NUM_REQS; ++i) begin
for (genvar i = 1; i < NUM_REQS; ++i) begin : g_masked_pri_reqs
assign masked_pri_reqs[i] = masked_pri_reqs[i-1] | masked_reqs[i-1];
end
assign unmasked_pri_reqs[0] = 1'b0;
for (genvar i = 1; i < NUM_REQS; ++i) begin
for (genvar i = 1; i < NUM_REQS; ++i) begin : g_unmasked_pri_reqs
assign unmasked_pri_reqs[i] = unmasked_pri_reqs[i-1] | requests[i-1];
end
@ -456,12 +456,12 @@ module VX_rr_arbiter #(
.valid_out(grant_valid)
);
end else if (MODEL == 2) begin
end else if (MODEL == 2) begin : g_model2
reg [NUM_REQS-1:0][LOG_NUM_REQS-1:0] grant_table;
reg [LOG_NUM_REQS-1:0] state;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_grant_table
always @(*) begin
grant_table[i] = 'x;
for (integer j = NUM_REQS-1; j >= 0; --j) begin

26
hw/rtl/libs/VX_scan.sv
View file

@ -32,31 +32,31 @@ module VX_scan #(
`IGNORE_UNOPTFLAT_END
// reverses bits
if (REVERSE != 0) begin
if (REVERSE != 0) begin : g_data_in_reverse
assign t[0] = data_in;
end else begin
end else begin : g_data_in_no_reverse
assign t[0] = {<<{data_in}};
end
// optimize for the common case of small and-scans
if ((N == 2) && (OP == "&")) begin
if ((N == 2) && (OP == "&")) begin : g_scan_n2_and
assign t[LOGN] = {t[0][1], &t[0][1:0]};
end else if ((N == 3) && (OP == "&")) begin
end else if ((N == 3) && (OP == "&")) begin : g_scan_n3_and
assign t[LOGN] = {t[0][2], &t[0][2:1], &t[0][2:0]};
end else if ((N == 4) && (OP == "&")) begin
end else if ((N == 4) && (OP == "&")) begin : g_scan_n4_and
assign t[LOGN] = {t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0]};
end else begin
end else begin : g_scan
// general case
wire [N-1:0] fill;
for (genvar i = 0; i < LOGN; ++i) begin
for (genvar i = 0; i < LOGN; ++i) begin : g_i
wire [N-1:0] shifted = N'({fill, t[i]} >> (1<<i));
if (OP == "^") begin
if (OP == "^") begin : g_xor
assign fill = {N{1'b0}};
assign t[i+1] = t[i] ^ shifted;
end else if (OP == "&") begin
end else if (OP == "&") begin : g_and
assign fill = {N{1'b1}};
assign t[i+1] = t[i] & shifted;
end else if (OP == "|") begin
end else if (OP == "|") begin : g_or
assign fill = {N{1'b0}};
assign t[i+1] = t[i] | shifted;
end
@ -64,10 +64,10 @@ module VX_scan #(
end
// reverse bits
if (REVERSE != 0) begin
if (REVERSE != 0) begin : g_data_out_reverse
assign data_out = t[LOGN];
end else begin
for (genvar i = 0; i < N; ++i) begin
end else begin : g_data_out
for (genvar i = 0; i < N; ++i) begin : g_i
assign data_out[i] = t[LOGN][N-1-i];
end
end

16
hw/rtl/libs/VX_scope_switch.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -14,9 +14,9 @@
`include "VX_platform.vh"
`TRACING_OFF
module VX_scope_switch #(
module VX_scope_switch #(
parameter N = 0
) (
) (
input wire clk,
input wire reset,
input wire req_in,
@ -24,7 +24,7 @@ module VX_scope_switch #(
input wire rsp_in [N],
output wire rsp_out
);
if (N > 1) begin
if (N > 1) begin : g_switch
reg req_out_r [N];
reg rsp_out_r;
@ -34,7 +34,7 @@ module VX_scope_switch #(
req_out_r[i] <= 0;
end
rsp_out_r <= 0;
end else begin
end else begin
for (integer i = 0; i < N; ++i) begin
req_out_r[i] <= req_in;
end
@ -48,8 +48,8 @@ module VX_scope_switch #(
assign req_out = req_out_r;
assign rsp_out = rsp_out_r;
end else begin
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)

17
hw/rtl/libs/VX_serial_div.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -29,7 +29,7 @@ module VX_serial_div #(
input wire is_signed,
input wire [LANES-1:0][WIDTHN-1:0] numer,
input wire [LANES-1:0][WIDTHD-1:0] denom,
input wire [LANES-1:0][WIDTHD-1:0] denom,
output wire [LANES-1:0][WIDTHQ-1:0] quotient,
output wire [LANES-1:0][WIDTHR-1:0] remainder
@ -49,14 +49,14 @@ module VX_serial_div #(
reg [CNTRW-1:0] cntr;
reg busy_r;
for (genvar i = 0; i < LANES; ++i) begin
for (genvar i = 0; i < LANES; ++i) begin : g_setup
wire negate_numer = is_signed && numer[i][WIDTHN-1];
wire negate_denom = is_signed && denom[i][WIDTHD-1];
assign numer_qual[i] = negate_numer ? -$signed(numer[i]) : numer[i];
assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i];
assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i];
end
always @(posedge clk) begin
if (reset) begin
busy_r <= 0;
@ -74,18 +74,21 @@ module VX_serial_div #(
end
end
for (genvar i = 0; i < LANES; ++i) begin
for (genvar i = 0; i < LANES; ++i) begin : g_div
always @(posedge clk) begin
if (strobe) begin
working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
denom_r[i] <= denom_qual[i];
inv_quot[i] <= (denom[i] != 0) && is_signed && (numer[i][31] ^ denom[i][31]);
inv_rem[i] <= is_signed && numer[i][31];
end else if (busy_r) begin
end else if (busy_r) begin
working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
end
end
end
for (genvar i = 0; i < LANES; ++i) begin : g_output
wire [WIDTHQ-1:0] q = working[i][WIDTHQ-1:0];
wire [WIDTHR-1:0] r = working[i][WIDTHN+WIDTHR:WIDTHN+1];
assign quotient[i] = inv_quot[i] ? -$signed(q) : q;

16
hw/rtl/libs/VX_serial_mul.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -13,7 +13,7 @@
`include "VX_platform.vh"
// Iterative integer multiplier
// Iterative integer multiplier
// An adaptation of ZipCPU algorithm for a multi-lane elastic architecture.
// https://zipcpu.com/zipcpu/2021/07/03/slowmpy.html
@ -65,7 +65,7 @@ module VX_serial_mul #(
end
end
for (genvar i = 0; i < LANES; ++i) begin
for (genvar i = 0; i < LANES; ++i) begin : g_mul
wire [X_WIDTH-1:0] axb = b[i][0] ? a[i] : '0;
always @(posedge clk) begin
@ -73,12 +73,12 @@ module VX_serial_mul #(
if (SIGNED) begin
a[i] <= X_WIDTH'($signed(dataa[i]));
b[i] <= Y_WIDTH'($signed(datab[i]));
end else begin
end else begin
a[i] <= dataa[i];
b[i] <= datab[i];
end
p[i] <= 0;
end else if (busy_r) begin
end else if (busy_r) begin
b[i] <= (b[i] >> 1);
p[i][Y_WIDTH-2:0] <= p[i][Y_WIDTH-1:1];
if (SIGNED) begin
@ -93,9 +93,9 @@ module VX_serial_mul #(
end
end
if (SIGNED) begin
if (SIGNED) begin : g_signed
assign result[i] = R_WIDTH'(p[i][P_WIDTH-1:0] + {1'b1, {(X_WIDTH-2){1'b0}}, 1'b1, {(Y_WIDTH){1'b0}}});
end else begin
end else begin : g_unsigned
assign result[i] = R_WIDTH'(p[i]);
end
end

18
hw/rtl/libs/VX_shift_register.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -14,13 +14,13 @@
`include "VX_platform.vh"
`TRACING_OFF
module VX_shift_register #(
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = 0,
parameter DEPTH = 1,
parameter NUM_TAPS = 1,
parameter NUM_TAPS = 1,
parameter TAP_START = 0,
parameter TAP_STRIDE = 1
parameter TAP_STRIDE = 1
) (
input wire clk,
input wire reset,
@ -28,7 +28,7 @@ module VX_shift_register #(
input wire [DATAW-1:0] data_in,
output wire [NUM_TAPS-1:0][DATAW-1:0] data_out
);
if (DEPTH != 0) begin
if (DEPTH != 0) begin : g_shift_register
reg [DEPTH-1:0][DATAW-1:0] entries;
always @(posedge clk) begin
@ -36,7 +36,7 @@ module VX_shift_register #(
if ((i >= (DATAW-RESETW)) && reset) begin
for (integer j = 0; j < DEPTH; ++j)
entries[j][i] <= 0;
end else if (enable) begin
end else if (enable) begin
for (integer j = 1; j < DEPTH; ++j)
entries[j-1][i] <= entries[j][i];
entries[DEPTH-1][i] <= data_in[i];
@ -44,10 +44,10 @@ module VX_shift_register #(
end
end
for (genvar i = 0; i < NUM_TAPS; ++i) begin
for (genvar i = 0; i < NUM_TAPS; ++i) begin : g_data_out
assign data_out[i] = entries[i * TAP_STRIDE + TAP_START];
end
end else begin
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)

16
hw/rtl/libs/VX_skid_buffer.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -19,19 +19,19 @@ module VX_skid_buffer #(
parameter PASSTHRU = 0,
parameter HALF_BW = 0,
parameter OUT_REG = 0
) (
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
if (PASSTHRU != 0) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@ -40,7 +40,7 @@ module VX_skid_buffer #(
assign data_out = data_in;
assign ready_in = ready_out;
end else if (HALF_BW != 0) begin
end else if (HALF_BW != 0) begin : g_half_bw
VX_toggle_buffer #(
.DATAW (DATAW)
@ -55,7 +55,7 @@ module VX_skid_buffer #(
.ready_out (ready_out)
);
end else begin
end else begin : g_full_bw
VX_stream_buffer #(
.DATAW (DATAW),

72
hw/rtl/libs/VX_stream_arb.sv
View file

@ -37,13 +37,13 @@ module VX_stream_arb #(
output wire [NUM_OUTPUTS-1:0][NUM_REQS_W-1:0] sel_out,
input wire [NUM_OUTPUTS-1:0] ready_out
);
if (NUM_INPUTS > NUM_OUTPUTS) begin
if (NUM_INPUTS > NUM_OUTPUTS) begin : g_more_inputs
if (NUM_OUTPUTS > 1) begin
if (NUM_OUTPUTS > 1) begin : g_multiple_outputs
// (#inputs > #outputs) and (#outputs > 1)
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_arb_slices
localparam SLICE_BEGIN = i * NUM_REQS;
localparam SLICE_END = `MIN(SLICE_BEGIN + NUM_REQS, NUM_INPUTS);
@ -69,7 +69,7 @@ module VX_stream_arb #(
);
end
end else if (MAX_FANOUT != 0 && (NUM_INPUTS > (MAX_FANOUT + MAX_FANOUT /2))) begin
end else if (MAX_FANOUT != 0 && (NUM_INPUTS > (MAX_FANOUT + MAX_FANOUT /2))) begin : g_fanout
// (#inputs > max_fanout) and (#outputs == 1)
@ -81,7 +81,7 @@ module VX_stream_arb #(
wire [NUM_SLICES-1:0][DATAW+LOG_NUM_REQS2-1:0] data_tmp;
wire [NUM_SLICES-1:0] ready_tmp;
for (genvar i = 0; i < NUM_SLICES; ++i) begin
for (genvar i = 0; i < NUM_SLICES; ++i) begin : g_fanout_slice_arbs
localparam SLICE_BEGIN = i * MAX_FANOUT;
localparam SLICE_END = `MIN(SLICE_BEGIN + MAX_FANOUT, NUM_INPUTS);
@ -90,26 +90,24 @@ module VX_stream_arb #(
wire [DATAW-1:0] data_tmp_u;
wire [`LOG2UP(SLICE_SIZE)-1:0] sel_tmp_u;
if (MAX_FANOUT != 1) begin
VX_stream_arb #(
.NUM_INPUTS (SLICE_SIZE),
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (3)
) fanout_slice_arb (
.clk (clk),
.reset (reset),
.valid_in (valid_in[SLICE_END-1: SLICE_BEGIN]),
.data_in (data_in[SLICE_END-1: SLICE_BEGIN]),
.ready_in (ready_in[SLICE_END-1: SLICE_BEGIN]),
.valid_out (valid_tmp[i]),
.data_out (data_tmp_u),
.sel_out (sel_tmp_u),
.ready_out (ready_tmp[i])
);
end
VX_stream_arb #(
.NUM_INPUTS (SLICE_SIZE),
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (3)
) fanout_slice_arb (
.clk (clk),
.reset (reset),
.valid_in (valid_in[SLICE_END-1: SLICE_BEGIN]),
.data_in (data_in[SLICE_END-1: SLICE_BEGIN]),
.ready_in (ready_in[SLICE_END-1: SLICE_BEGIN]),
.valid_out (valid_tmp[i]),
.data_out (data_tmp_u),
.sel_out (sel_tmp_u),
.ready_out (ready_tmp[i])
);
assign data_tmp[i] = {data_tmp_u, LOG_NUM_REQS2'(sel_tmp_u)};
end
@ -139,7 +137,7 @@ module VX_stream_arb #(
assign data_out = data_out_u[LOG_NUM_REQS2 +: DATAW];
assign sel_out = {sel_out_u, data_out_u[0 +: LOG_NUM_REQS2]};
end else begin
end else begin : g_one_output
// (#inputs <= max_fanout) and (#outputs == 1)
@ -169,7 +167,7 @@ module VX_stream_arb #(
assign data_in_w = data_in[arb_index];
assign arb_ready = ready_in_w;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_ready_in
assign ready_in[i] = ready_in_w && arb_onehot[i];
end
@ -190,13 +188,13 @@ module VX_stream_arb #(
);
end
end else if (NUM_OUTPUTS > NUM_INPUTS) begin
end else if (NUM_OUTPUTS > NUM_INPUTS) begin : g_more_outputs
if (NUM_INPUTS > 1) begin
if (NUM_INPUTS > 1) begin : g_multiple_inputs
// (#inputs > 1) and (#outputs > #inputs)
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_arb_slices
localparam SLICE_BEGIN = i * NUM_REQS;
localparam SLICE_END = `MIN(SLICE_BEGIN + NUM_REQS, NUM_OUTPUTS);
@ -221,12 +219,12 @@ module VX_stream_arb #(
`UNUSED_PIN (sel_out)
);
for (genvar j = SLICE_BEGIN; j < SLICE_END; ++j) begin
for (genvar j = SLICE_BEGIN; j < SLICE_END; ++j) begin : g_sel_out
assign sel_out[j] = i;
end
end
end else if (MAX_FANOUT != 0 && (NUM_OUTPUTS > (MAX_FANOUT + MAX_FANOUT /2))) begin
end else if (MAX_FANOUT != 0 && (NUM_OUTPUTS > (MAX_FANOUT + MAX_FANOUT /2))) begin : g_fanout
// (#inputs == 1) and (#outputs > max_fanout)
@ -255,7 +253,7 @@ module VX_stream_arb #(
`UNUSED_PIN (sel_out)
);
for (genvar i = 0; i < NUM_SLICES; ++i) begin
for (genvar i = 0; i < NUM_SLICES; ++i) begin : g_fanout_slice_arbs
localparam SLICE_BEGIN = i * MAX_FANOUT;
localparam SLICE_END = `MIN(SLICE_BEGIN + MAX_FANOUT, NUM_OUTPUTS);
@ -281,7 +279,7 @@ module VX_stream_arb #(
);
end
end else begin
end else begin : g_one_input
// (#inputs == 1) and (#outputs <= max_fanout)
@ -309,7 +307,7 @@ module VX_stream_arb #(
assign arb_ready = valid_in[0];
assign ready_in = arb_valid;
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
@ -330,11 +328,11 @@ module VX_stream_arb #(
assign sel_out = 0;
end else begin
end else begin : g_passthru
// #Inputs == #Outputs
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),

18
hw/rtl/libs/VX_stream_buffer.sv
View file

@ -37,14 +37,8 @@ module VX_stream_buffer #(
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
if (OUT_REG != 0) begin
if (PASSTHRU == 0) begin : g_buffer
if (OUT_REG != 0) begin : g_with_reg
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
@ -83,7 +77,7 @@ module VX_stream_buffer #(
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end else begin
end else begin : g_no_reg
reg [1:0][DATAW-1:0] shift_reg;
reg [1:0] fifo_state;
@ -115,6 +109,12 @@ module VX_stream_buffer #(
assign data_out = shift_reg[fifo_state[1]];
end
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end
endmodule

9
hw/rtl/libs/VX_stream_pack.sv
View file

@ -38,7 +38,8 @@ module VX_stream_pack #(
output wire [TAG_WIDTH-1:0] tag_out,
input wire ready_out
);
if (NUM_REQS > 1) begin
if (NUM_REQS > 1) begin : g_pack
localparam LOG_NUM_REQS = `CLOG2(NUM_REQS);
wire [LOG_NUM_REQS-1:0] grant_index;
@ -62,11 +63,11 @@ module VX_stream_pack #(
wire [NUM_REQS-1:0] tag_matches;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_tag_matches
assign tag_matches[i] = (tag_in[i][TAG_SEL_BITS-1:0] == tag_sel[TAG_SEL_BITS-1:0]);
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_ready_in
assign ready_in[i] = grant_ready & tag_matches[i];
end
@ -87,7 +88,7 @@ module VX_stream_pack #(
.ready_out (ready_out)
);
end else begin
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)

42
hw/rtl/libs/VX_stream_switch.sv
View file

@ -36,18 +36,17 @@ module VX_stream_switch #(
output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out,
input wire [NUM_OUTPUTS-1:0] ready_out
);
if (NUM_INPUTS > NUM_OUTPUTS) begin
if (NUM_INPUTS > NUM_OUTPUTS) begin : g_more_inputs
wire [NUM_OUTPUTS-1:0][NUM_REQS-1:0] valid_in_w;
wire [NUM_OUTPUTS-1:0][NUM_REQS-1:0][DATAW-1:0] data_in_w;
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_data_in
for (genvar j = 0; j < NUM_REQS; ++j) begin : g_j
localparam ii = i * NUM_REQS + j;
if (ii < NUM_INPUTS) begin
if (ii < NUM_INPUTS) begin : g_valid
assign valid_in_w[i][j] = valid_in[ii];
assign data_in_w[i][j] = data_in[ii];
end else begin
end else begin : g_extra
assign valid_in_w[i][j] = 0;
assign data_in_w[i][j] = '0;
end
@ -58,21 +57,21 @@ module VX_stream_switch #(
wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_w;
wire [NUM_OUTPUTS-1:0] ready_out_w;
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_data_out_w
assign valid_out_w[i] = valid_in_w[i][sel_in[i]];
assign data_out_w[i] = data_in_w[i][sel_in[i]];
end
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_ready_out_w
for (genvar j = 0; j < NUM_REQS; ++j) begin : g_j
localparam ii = i * NUM_REQS + j;
if (ii < NUM_INPUTS) begin
if (ii < NUM_INPUTS) begin : g_valid
assign ready_in[ii] = ready_out_w[i] && (sel_in[i] == LOG_NUM_REQS'(j));
end
end
end
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
@ -89,22 +88,25 @@ module VX_stream_switch #(
);
end
end else if (NUM_OUTPUTS > NUM_INPUTS) begin
end else if (NUM_OUTPUTS > NUM_INPUTS) begin : g_more_outputs
wire [NUM_INPUTS-1:0][NUM_REQS-1:0] valid_out_w;
wire [NUM_INPUTS-1:0][NUM_REQS-1:0] ready_out_w;
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_valid_out_w
for (genvar j = 0; j < NUM_REQS; ++j) begin : g_j
assign valid_out_w[i][j] = valid_in[i] && (sel_in[i] == LOG_NUM_REQS'(j));
end
end
for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_ready_in
assign ready_in[i] = ready_out_w[i][sel_in[i]];
end
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_out_buf
for (genvar j = 0; j < NUM_REQS; ++j) begin : g_j
localparam ii = i * NUM_REQS + j;
if (ii < NUM_OUTPUTS) begin
if (ii < NUM_OUTPUTS) begin : g_valid
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
@ -119,20 +121,20 @@ module VX_stream_switch #(
.valid_out (valid_out[ii]),
.ready_out (ready_out[ii])
);
end else begin
end else begin : g_extra
`UNUSED_VAR (valid_out_w[i][j])
assign ready_out_w[i][j] = '0;
end
end
end
end else begin
end else begin : g_passthru
// #Inputs == #Outputs
`UNUSED_VAR (sel_in)
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),

6
hw/rtl/libs/VX_stream_unpack.sv
View file

@ -36,7 +36,7 @@ module VX_stream_unpack #(
output wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag_out,
input wire [NUM_REQS-1:0] ready_out
);
if (NUM_REQS > 1) begin
if (NUM_REQS > 1) begin : g_unpack
reg [NUM_REQS-1:0] rem_mask_r;
wire [NUM_REQS-1:0] ready_out_w;
@ -56,7 +56,7 @@ module VX_stream_unpack #(
assign ready_in = sent_all;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_outbuf
VX_elastic_buffer #(
.DATAW (DATA_WIDTH + TAG_WIDTH),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
@ -73,7 +73,7 @@ module VX_stream_unpack #(
);
end
end else begin
end else begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)

16
hw/rtl/libs/VX_stream_xbar.sv
View file

@ -43,9 +43,9 @@ module VX_stream_xbar #(
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
if (NUM_INPUTS != 1) begin
if (NUM_INPUTS != 1) begin : g_multiple_inputs
if (NUM_OUTPUTS != 1) begin
if (NUM_OUTPUTS != 1) begin : g_multiple_outputs
// (#inputs > 1) and (#outputs > 1)
@ -63,7 +63,7 @@ module VX_stream_xbar #(
.data_out (per_output_ready_in_w)
);
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_sel_in_decoders
VX_decoder #(
.N (OUT_WIDTH)
) sel_in_decoder (
@ -82,7 +82,7 @@ module VX_stream_xbar #(
.data_out (per_output_valid_in_w)
);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_xbar_arbs
VX_stream_arb #(
.NUM_INPUTS (NUM_INPUTS),
.NUM_OUTPUTS (1),
@ -103,7 +103,7 @@ module VX_stream_xbar #(
);
end
end else begin
end else begin : g_one_output
// (#inputs >= 1) and (#outputs == 1)
@ -129,7 +129,7 @@ module VX_stream_xbar #(
`UNUSED_VAR (sel_in)
end
end else if (NUM_OUTPUTS != 1) begin
end else if (NUM_OUTPUTS != 1) begin : g_one_input
// (#inputs == 1) and (#outputs > 1)
@ -147,7 +147,7 @@ module VX_stream_xbar #(
assign ready_in[0] = ready_out_w[sel_in[0]];
assign data_out_w = {NUM_OUTPUTS{data_in[0]}};
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
@ -167,7 +167,7 @@ module VX_stream_xbar #(
assign sel_out = 0;
end else begin
end else begin : g_passthru
// (#inputs == 1) and (#outputs == 1)

23
hw/rtl/libs/VX_toggle_buffer.sv
View file

@ -1,11 +1,11 @@
// Copyright 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -26,23 +26,26 @@
module VX_toggle_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
);
if (PASSTHRU != 0) begin : g_passthru
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
end else begin : g_buffer
reg [DATAW-1:0] buffer;
reg has_data;
@ -54,7 +57,7 @@ module VX_toggle_buffer #(
has_data <= valid_in;
end else if (ready_out) begin
has_data <= 0;
end
end
end
if (~has_data) begin
buffer <= data_in;

4
hw/rtl/libs/VX_transpose.sv
View file

@ -21,8 +21,8 @@ module VX_transpose #(
input wire [N-1:0][M-1:0] data_in,
output wire [M-1:0][N-1:0] data_out
);
for (genvar i = 0; i < N; ++i) begin
for (genvar j = 0; j < M; ++j) begin
for (genvar i = 0; i < N; ++i) begin : g_i
for (genvar j = 0; j < M; ++j) begin : g_j
assign data_out[j][i] = data_in[i][j];
end
end

8
hw/rtl/mem/VX_gbar_arb.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -33,7 +33,7 @@ module VX_gbar_arb #(
wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in;
wire [NUM_REQS-1:0] req_ready_in;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_data_in
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign req_data_in[i] = {bus_in_if[i].req_id, bus_in_if[i].req_size_m1, bus_in_if[i].req_core_id};
assign bus_in_if[i].req_ready = req_ready_in[i];
@ -71,7 +71,7 @@ module VX_gbar_arb #(
rsp_id <= bus_out_if.rsp_id;
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_bus_in_if
assign bus_in_if[i].rsp_valid = rsp_valid;
assign bus_in_if[i].rsp_id = rsp_id;
end

2
hw/rtl/mem/VX_lmem_switch.sv
View file

@ -32,7 +32,7 @@ module VX_lmem_switch import VX_gpu_pkg::*; #(
wire req_global_ready;
wire req_local_ready;
for (genvar i = 0; i < `NUM_LSU_LANES; ++i) begin
for (genvar i = 0; i < `NUM_LSU_LANES; ++i) begin : g_is_addr_local_mask
assign is_addr_local_mask[i] = lsu_in_if.req_data.flags[i][`MEM_REQ_FLAG_LOCAL];
end

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