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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
df99b9da0e
commit
6eeb8eac0f
8 changed files with 49 additions and 52 deletions
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@ -1,18 +1,18 @@
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// Copyright 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// A stream elastic buffer operates at full-bandwidth where push and pop can happen simultaneously
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// A stream elastic buffer operates at full-bandwidth where fire_in and fire_out can happen simultaneously
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// It has the following benefits:
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// + full-bandwidth throughput
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// + ready_in and ready_out are decoupled
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@ -27,21 +27,21 @@ module VX_stream_buffer #(
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parameter DATAW = 1,
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parameter OUT_REG = 0,
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parameter PASSTHRU = 0
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) (
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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);
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if (PASSTHRU != 0) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign ready_in = ready_out;
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assign valid_out = valid_in;
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assign valid_out = valid_in;
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assign data_out = data_in;
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end else begin
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if (OUT_REG != 0) begin
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@ -49,77 +49,71 @@ module VX_stream_buffer #(
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reg [DATAW-1:0] data_out_r;
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reg [DATAW-1:0] buffer;
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reg valid_out_r;
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reg use_buffer;
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wire push = valid_in && ready_in;
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wire stall_out = valid_out_r && ~ready_out;
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reg no_buffer;
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wire fire_in = valid_in && ready_in;
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wire flow_out = ready_out || ~valid_out_r;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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use_buffer <= 0;
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valid_out_r <= 0;
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no_buffer <= 1;
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end else begin
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if (ready_out) begin
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use_buffer <= 0;
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no_buffer <= 1;
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end else if (valid_in && valid_out) begin
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use_buffer <= 1;
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no_buffer <= 0;
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end
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if (~stall_out) begin
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valid_out_r <= valid_in || use_buffer;
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if (flow_out) begin
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valid_out_r <= valid_in || ~no_buffer;
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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if (fire_in) begin
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buffer <= data_in;
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end
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if (~stall_out) begin
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data_out_r <= use_buffer ? buffer : data_in;
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if (flow_out) begin
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data_out_r <= no_buffer ? data_in : buffer;
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end
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end
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assign ready_in = ~use_buffer;
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assign ready_in = no_buffer;
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assign valid_out = valid_out_r;
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assign data_out = data_out_r;
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end else begin
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reg [1:0][DATAW-1:0] shift_reg;
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reg valid_out_r, ready_in_r, rd_ptr_r;
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reg [DATAW-1:0] shift_reg [1:0];
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reg [1:0] fifo_state;
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wire push = valid_in && ready_in;
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wire pop = valid_out_r && ready_out;
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wire fire_in = valid_in && ready_in;
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wire fire_out = valid_out && ready_out;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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ready_in_r <= 1;
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rd_ptr_r <= 1;
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fifo_state <= 2'b00;
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end else begin
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if (push) begin
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if (!pop) begin
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ready_in_r <= rd_ptr_r;
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valid_out_r <= 1;
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end
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end else if (pop) begin
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ready_in_r <= 1;
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valid_out_r <= rd_ptr_r;
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end
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rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
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end
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case ({fire_in, fire_out})
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2'b10: fifo_state <= {fifo_state[0], 1'b1}; // 00 -> 01, 01 -> 10
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2'b01: fifo_state <= {1'b0, fifo_state[1]}; // 10 -> 01, 01 -> 00
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default: fifo_state <= fifo_state;
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endcase
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end
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end
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always @(posedge clk) begin
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if (push) begin
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if (fire_in) begin
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shift_reg[1] <= shift_reg[0];
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shift_reg[0] <= data_in;
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end
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end
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assign ready_in = ready_in_r;
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assign valid_out = valid_out_r;
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assign data_out = shift_reg[rd_ptr_r];
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assign ready_in = ~fifo_state[1];
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assign valid_out = fifo_state[0];
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assign data_out = shift_reg[fifo_state[1]];
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end
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end
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@ -11,4 +11,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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@ -8,4 +8,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)
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RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces
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@ -11,4 +11,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem $(FPU_INCLUDE) -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem $(FPU_INCLUDE) $(FPU_INCLUDE)
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@ -1 +1,4 @@
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## empty
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set CLK_FREQ_MHZ 300
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set clk_port_name clk
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set clk_port [get_ports $clk_port_name]
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create_clock -name core_clock -period [expr 1000.0 / $CLK_FREQ_MHZ] $clk_port
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@ -29,4 +29,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip $(FPU_INCLUDE)
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@ -8,4 +8,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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@ -13,4 +13,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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