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Modelsim Makefile compile + simulate - DPI

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This commit is contained in:
felsabbagh3 2019-10-26 19:01:49 -04:00
parent ad46194d1b
commit 6fda88b68f
6 changed files with 238 additions and 6 deletions
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22
rtl/VX_countones.v Normal file
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@ -0,0 +1,22 @@
module VX_countones
#(
parameter N = 10
)
(
input wire[N-1:0] valids,
output reg[$clog2(N):0] count
);
integer i;
always @(*) begin
count = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
count = count + 1;
end
end
end
endmodule

23
rtl/VX_warp_scheduler.v
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@ -105,7 +105,7 @@ module VX_warp_scheduler (
reg[`NW-1:0] total_barrier_stall;
/* verilator lint_off UNUSED */
wire[$clog2(`NW):0] num_active;
// wire[$clog2(`NW):0] num_active;
/* verilator lint_on UNUSED */
integer curr_w_help;
@ -195,8 +195,20 @@ module VX_warp_scheduler (
end
end
VX_countones #(.N(`NW)) barrier_count(
.valids(curr_barrier_mask),
.count (curr_barrier_count)
);
wire[$clog2(`NW):0] count_visible_active;
VX_countones #(.N(`NW)) num_visible(
.valids(visible_active),
.count (count_visible_active)
);
// assign curr_barrier_count = $countones(curr_barrier_mask);
assign curr_barrier_mask = barrier_stall_mask[barrier_id][`NW-1:0];
assign curr_barrier_count = $countones(curr_barrier_mask);
assign reached_barrier_limit = curr_barrier_count == (num_warps);
assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug
@ -211,7 +223,7 @@ module VX_warp_scheduler (
end
assign update_visible_active = ($countones(visible_active) < 1) && !(stall || wstall_this_cycle || hazard || is_join);
assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join);
wire[(1+32+`NT_M1):0] q1 = {1'b1, 32'b0 , thread_masks[split_warp_num]};
wire[(1+32+`NT_M1):0] q2 = {1'b0, split_save_pc , split_later_mask};
@ -262,7 +274,7 @@ module VX_warp_scheduler (
assign new_pc = warp_pc + 4;
assign use_active = (num_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall)) : visible_active;
assign use_active = (count_visible_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall)) : visible_active;
// Choosing a warp to schedule
VX_priority_encoder choose_schedule(
@ -272,8 +284,9 @@ module VX_warp_scheduler (
);
// Valid counter
assign num_active = $countones(visible_active);
// assign num_active = $countones(visible_active);
// VX_one_counter valid_counter(
// .valids(visible_active),
// .ones_found()

124
rtl/modelsim/Makefile Normal file
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@ -0,0 +1,124 @@
###############################################################################
#
# ICARUS VERILOG & GTKWAVE MAKEFILE
# MADE BY WILLIAM GIBB FOR HACDC
# williamgibb@gmail.com
#
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# "make check" - compiles your verilog design - good for checking code
# "make simulate" - compiles your design+TB & simulates your design
# "make display" - compiles, simulates and displays waveforms
#
###############################################################################
#
# CHANGE THESE THREE LINES FOR YOUR DESIGN
#
ALL:sim
#TOOL INPUT
SRC = \
vortex_tb.v \
../VX_define.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \
../interfaces/VX_dcache_request_inter.v \
../interfaces/VX_dcache_response_inter.v \
../interfaces/VX_dram_req_rsp_inter.v \
../interfaces/VX_exec_unit_req_inter.v \
../interfaces/VX_frE_to_bckE_req_inter.v \
../interfaces/VX_gpr_clone_inter.v \
../interfaces/VX_gpr_data_inter.v \
../interfaces/VX_gpr_jal_inter.v \
../interfaces/VX_gpr_read_inter.v \
../interfaces/VX_gpr_wspawn_inter.v \
../interfaces/VX_gpu_inst_req_inter.v \
../interfaces/VX_icache_request_inter.v \
../interfaces/VX_icache_response_inter.v \
../interfaces/VX_inst_exec_wb_inter.v \
../interfaces/VX_inst_mem_wb_inter.v \
../interfaces/VX_inst_meta_inter.v \
../interfaces/VX_jal_response_inter.v \
../interfaces/VX_join_inter.v \
../interfaces/VX_lsu_req_inter.v \
../interfaces/VX_mem_req_inter.v \
../interfaces/VX_mw_wb_inter.v \
../interfaces/VX_warp_ctl_inter.v \
../interfaces/VX_wb_inter.v \
../interfaces/VX_wstall_inter.v \
../VX_alu.v \
../VX_back_end.v \
../VX_csr_handler.v \
../VX_csr_wrapper.v \
../VX_decode.v \
../VX_dmem_controller.v \
../VX_execute_unit.v \
../VX_fetch.v \
../VX_front_end.v \
../VX_generic_priority_encoder.v \
../VX_generic_register.v \
../VX_generic_stack.v \
../VX_gpgpu_inst.v \
../VX_gpr.v \
../VX_gpr_stage.v \
../VX_gpr_wrapper.v \
../VX_inst_multiplex.v \
../VX_lsu.v \
../VX_lsu_addr_gen.v \
../VX_priority_encoder.v \
../VX_priority_encoder_w_mask.v \
../VX_scheduler.v \
../VX_warp.v \
../VX_countones.v \
../VX_warp_scheduler.v \
../VX_writeback.v \
../Vortex.v \
../byte_enabled_simple_dual_port_ram.v \
../cache/VX_Cache_Bank.v \
../cache/VX_cache_bank_valid.v \
../cache/VX_cache_data.v \
../cache/VX_d_cache.v \
../cache/VX_generic_pe.v \
../cache/cache_set.v \
../pipe_regs/VX_d_e_reg.v \
../pipe_regs/VX_f_d_reg.v \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
CMD= \
-do "vcd file vortex.vcd; \
run"
# ../shared_memory/VX_set_bit.v \
# ../cache/bank.v \
# ../cache/VX_d_cache_tb.v \
# ../cache/VX_d_cache_encapsulate.v \
# ../VX_rename.v \
# ../cache/VX_Cache_Block_DM.v \
# ../VX_one_counter.v \
###############################################################################
# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
###############################################################################
#TOOLS
#TOOL OUTPUT
###############################################################################
#MAKE DIRECTIVES
# setup: source cshrc.modelsim
# vlib
comp:
vlog -sv -sv12compat -work vortex_lib $(SRC)
sim: comp
vsim vortex_tb -logfile vortex_tb.log -c -lib vortex_lib $(CMD)

8
rtl/modelsim/cshrc.modelsim Normal file
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@ -0,0 +1,8 @@
setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin"
setenv MTI_VCO_MODE 1
if (${?LM_LICENSE_FILE}) then
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}"
else
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu"
endif
setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu

65
rtl/modelsim/vortex_tb.v Normal file
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@ -0,0 +1,65 @@
// `include "../VX_define.v"
// `include "../Vortex.v"
`timescale 1ns/1ps
module vortex_tb (
);
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
reg[31:0] icache_request_pc_address;
// IO
reg io_valid;
reg[31:0] io_data;
// Req
reg [31:0] o_m_read_addr;
reg [31:0] o_m_evict_addr;
reg o_m_valid;
reg [31:0] o_m_writedata[8 - 1:0][4-1:0];
reg o_m_read_or_write;
// Rsp
reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
reg i_m_ready;
reg out_ebreak;
integer temp;
initial begin
for (temp = 0; temp < 10; temp=temp+1)
begin
icache_response_instruction = 32'h0;
$display("SIMULATING");
end
// while (!out_ebreak) begin
// icache_response_instruction = 0;
// end
end
Vortex vortex(
.clk (clk),
.reset (reset),
.icache_response_instruction(icache_response_instruction),
.icache_request_pc_address (icache_request_pc_address),
.io_valid (io_valid),
.io_data (io_data),
.o_m_read_addr (o_m_read_addr),
.o_m_evict_addr (o_m_evict_addr),
.o_m_valid (o_m_valid),
.o_m_writedata (o_m_writedata),
.o_m_read_or_write (o_m_read_or_write),
.i_m_readdata (i_m_readdata),
.i_m_ready (i_m_ready),
.out_ebreak (out_ebreak)
);
always @(clk) #5 clk <= ~clk;
endmodule

2
syn/syn.tcl
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@ -3,7 +3,7 @@ set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_
set symbol_library {}
set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]
set verilog_files [ list Vortex.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v bank.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_set_bit.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v bank.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_set_bit.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
]
set top_level Vortex