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pt sampling - dcache arb; pt address compute setup

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This commit is contained in:
Krishna Yalamarthy 2021-03-17 12:07:25 -04:00
parent 2cbc1c4161
commit 6febdf7399
7 changed files with 450 additions and 5 deletions
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8
hw/VX_config.h
View file

@ -1,5 +1,5 @@
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at 2021-03-13 13:57:30.622905
// Generated at 2021-03-16 09:55:41.298661
#ifndef VX_USER_CONFIG
#define VX_USER_CONFIG
@ -7,7 +7,7 @@
#endif
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at 2021-03-13 13:57:30.624676
// Generated at 2021-03-16 09:55:41.301258
// Translated from VX_config.vh:
@ -98,6 +98,10 @@
#define EXT_F_ENABLE
#endif
#ifndef EXT_TEX_DISABLE
#define EXT_TEX_ENABLE
#endif
// Device identification
#define VENDOR_ID 0
#define ARCHITECTURE_ID 0

88
hw/rtl/VX_execute.v
View file

@ -63,6 +63,90 @@ module VX_execute #(
.alu_commit_if (alu_commit_if)
);
`ifdef EXT_TEX_ENABLE
VX_dcache_core_req_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) tex_dcache_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) tex_dcache_rsp_if();
VX_dcache_core_req_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) lsu_dcache_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) lsu_dcache_rsp_if();
VX_mem_arb #(
.NUM_REQS (2),
.DATA_WIDTH (`WORD_WIDTH),
.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
.TAG_OUT_WIDTH (`DCORE_TAG_WIDTH),
.BUFFERED_REQ (0),
.BUFFERED_RSP (0)
) dcache_arb (
.clk (clk),
.reset (reset),
// Tex/LSU request
.req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}),
.req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}),
.req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}),
.req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}),
.req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}),
.req_tag_in ({tex_dcache_req_if.tag, lsu_dcache_req_if.tag}),
.req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}),
// Dcache request
.req_valid_out (dcache_req_if.valid),
.req_rw_out (dcache_req_if.rw),
.req_byteen_out (dcache_req_if.byteen),
.req_addr_out (dcache_req_if.addr),
.req_data_out (dcache_req_if.data),
.req_tag_out (dcache_req_if.tag),
.req_ready_out (dcache_req_if.ready),
// Tex/LSU response
.rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}),
.rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}),
.rsp_tag_out ({tex_dcache_rsp_if.tag, lsu_dcache_rsp_if.tag}),
.rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready}),
// Dcache response
.rsp_valid_in (dcache_rsp_if.valid),
.rsp_tag_in (dcache_rsp_if.tag),
.rsp_data_in (dcache_rsp_if.data),
.rsp_ready_in (dcache_rsp_if.ready)
);
VX_lsu_unit #(
.CORE_ID(CORE_ID)
) lsu_unit (
`SCOPE_BIND_VX_execute_lsu_unit
.clk (clk),
.reset (reset),
.dcache_req_if (lsu_dcache_req_if),
.dcache_rsp_if (lsu_dcache_rsp_if),
.lsu_req_if (lsu_req_if),
.ld_commit_if (ld_commit_if),
.st_commit_if (st_commit_if)
);
`else
VX_lsu_unit #(
.CORE_ID(CORE_ID)
) lsu_unit (
@ -76,6 +160,8 @@ module VX_execute #(
.st_commit_if (st_commit_if)
);
`endif
VX_csr_unit #(
.CORE_ID(CORE_ID)
) csr_unit (
@ -138,6 +224,8 @@ module VX_execute #(
.gpu_req_if (gpu_req_if),
`ifdef EXT_TEX_ENABLE
.tex_csr_if (tex_csr_if),
.dcache_req_if (tex_dcache_req_if),
.dcache_rsp_if (tex_dcache_rsp_if),
`endif
.warp_ctl_if (warp_ctl_if),
.gpu_commit_if (gpu_commit_if)

10
hw/rtl/VX_gpu_unit.v
View file

@ -13,6 +13,9 @@ module VX_gpu_unit #(
`ifdef EXT_TEX_ENABLE
VX_tex_csr_if tex_csr_if,
VX_dcache_core_req_if dcache_req_if,
VX_dcache_core_rsp_if dcache_rsp_if,
`endif
// Outputs
@ -112,7 +115,8 @@ module VX_gpu_unit #(
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
assign tex_req_if.v[i] = gpu_req_if.rs2_data[i];
assign tex_req_if.lod_t[i] = gpu_req_if.rs3_data[i];
assign tex_req_if.lod[i] = gpu_req_if.rs3_data[i][31:8];
assign tex_req_if.t[i] = gpu_req_if.rs3_data[i][7:0];
end
VX_tex_unit #(
@ -122,7 +126,9 @@ module VX_gpu_unit #(
.reset (reset),
.tex_req_if (tex_req_if),
.tex_csr_if (tex_csr_if),
.tex_rsp_if (tex_rsp_if)
.tex_rsp_if (tex_rsp_if),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if)
);
assign tex_rsp_if.ready = !stall_out;

3
hw/rtl/interfaces/VX_tex_req_if.v
View file

@ -13,7 +13,8 @@ interface VX_tex_req_if ();
wire wb;
wire [`NUM_THREADS-1:0][31:0] u;
wire [`NUM_THREADS-1:0][31:0] v;
wire [`NUM_THREADS-1:0][31:0] lod_t;
wire [`NUM_THREADS-1:0][23:0] lod;
wire [`NUM_THREADS-1:0][7:0] t;
wire ready;
endinterface

295
hw/rtl/tex_unit/VX_tex_memory.v Normal file
View file

@ -0,0 +1,295 @@
`include "VX_define.vh"
module VX_tex_memory #(
parameter CORE_ID = 0
) (
`SCOPE_IO_VX_lsu_unit
input wire clk,
input wire reset,
// Dcache interface
VX_dcache_core_req_if dcache_req_if,
VX_dcache_core_rsp_if dcache_rsp_if,
// inputs
VX_lsu_req_if lsu_req_if,
// outputs
VX_commit_if ld_commit_if
// VX_commit_if st_commit_if
);
`UNUSED_PARAM (CORE_ID)
wire req_valid;
wire [`NUM_THREADS-1:0] req_tmask;
wire [`NUM_THREADS-1:0][31:0] req_addr;
wire [`LSU_BITS-1:0] req_type;
wire [`NUM_THREADS-1:0][31:0] req_data;
wire [`NR_BITS-1:0] req_rd;
wire req_wb;
wire [`NW_BITS-1:0] req_wid;
wire [31:0] req_pc;
wire req_is_dup;
wire [`NUM_THREADS-1:0][31:0] full_address;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
end
wire [`NUM_THREADS-1:0] addr_matches;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign addr_matches[i] = (full_address[0][31:2] == full_address[i][31:2]) || ~lsu_req_if.tmask[i];
end
wire is_dup_load = lsu_req_if.wb && lsu_req_if.tmask[0] && (& addr_matches);
`IGNORE_WARNINGS_BEGIN
reg [`LSUQ_SIZE-1:0][`DCORE_TAG_ID_BITS-1:0] pending_tags;
`IGNORE_WARNINGS_END
wire ready_in;
wire stall_in = ~ready_in && req_valid;
VX_pipe_register #(
.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.RESETW (1)
) req_pipe_reg (
.clk (clk),
.reset (reset),
.enable (!stall_in),
.data_in ({lsu_req_if.valid, is_dup_load, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_address, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_type, req_rd, req_wb, req_data})
);
// Can accept new request?
assign lsu_req_if.ready = ~stall_in;
wire [`NW_BITS-1:0] rsp_wid;
wire [31:0] rsp_pc;
wire [`NR_BITS-1:0] rsp_rd;
wire rsp_wb;
wire [`LSU_BITS-1:0] rsp_type;
wire rsp_is_dup;
`UNUSED_VAR (rsp_type)
reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask;
reg [`NUM_THREADS-1:0] rsp_rem_mask_n;
reg [`NUM_THREADS-1:0] req_sent_mask;
wire req_sent_all;
wire [`DCORE_TAG_ID_BITS-1:0] mbuf_waddr, mbuf_raddr;
wire mbuf_full;
wire [`NUM_THREADS-1:0][1:0] req_offset, rsp_offset;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign req_offset[i] = req_addr[i][1:0];
end
wire mbuf_push = (| (dcache_req_if.valid & dcache_req_if.ready))
&& (0 == req_sent_mask) // first submission only
&& req_wb; // loads only
wire mbuf_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
wire mbuf_pop = mbuf_pop_part && (rsp_rem_mask_n == 0 || rsp_is_dup);
assign mbuf_raddr = dcache_rsp_if.tag[`DCORE_TAG_ID_BITS-1:0];
VX_index_buffer #(
.DATAW (`NW_BITS + 32 + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * 2) + 1),
.SIZE (`LSUQ_SIZE)
) req_metadata (
.clk (clk),
.reset (reset),
.write_addr (mbuf_waddr),
.acquire_slot (mbuf_push),
.read_addr (mbuf_raddr),
.write_data ({req_wid, req_pc, req_rd, req_wb, req_type, req_offset, req_is_dup}),
.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup}),
.release_addr (mbuf_raddr),
.release_slot (mbuf_pop),
.full (mbuf_full)
);
assign req_sent_all = (&(dcache_req_if.ready | req_sent_mask | ~req_tmask))
|| (req_is_dup && dcache_req_if.ready[0]);
always @(posedge clk) begin
if (reset) begin
req_sent_mask <= 0;
end else begin
if (req_sent_all)
req_sent_mask <= 0;
else
req_sent_mask <= req_sent_mask | (dcache_req_if.valid & dcache_req_if.ready);
end
end
// need to hold the acquired tag index until the full request is submitted
reg [`DCORE_TAG_ID_BITS-1:0] req_tag_hold;
wire [`DCORE_TAG_ID_BITS-1:0] req_tag = (0 == req_sent_mask) ? mbuf_waddr : req_tag_hold;
always @(posedge clk) begin
if (mbuf_push)
req_tag_hold <= mbuf_waddr;
end
assign rsp_rem_mask_n = rsp_rem_mask[mbuf_raddr] & ~dcache_rsp_if.valid;
always @(posedge clk) begin
if (mbuf_push) begin
rsp_rem_mask[mbuf_waddr] <= req_tmask;
pending_tags[mbuf_waddr] <= req_tag;
end
if (mbuf_pop_part) begin
rsp_rem_mask[mbuf_raddr] <= rsp_rem_mask_n;
end
end
// wire req_ready_dep = (req_wb && ~mbuf_full) || (~req_wb && st_commit_if.ready);
wire req_ready_dep = (req_wb && ~mbuf_full);
wire [`NUM_THREADS-1:0] dup_mask = {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1};
// DCache Request
reg [`NUM_THREADS-1:0][29:0] mem_req_addr;
reg [`NUM_THREADS-1:0][3:0] mem_req_byteen;
reg [`NUM_THREADS-1:0][31:0] mem_req_data;
always @(*) begin
for (integer i = 0; i < `NUM_THREADS; i++) begin
mem_req_byteen[i] = {4{req_wb}};
case (`LSU_WSIZE(req_type))
0: mem_req_byteen[i][req_offset[i]] = 1;
1: begin
mem_req_byteen[i][req_offset[i]] = 1;
mem_req_byteen[i][{req_addr[i][1], 1'b1}] = 1;
end
default : mem_req_byteen[i] = {4{1'b1}};
endcase
mem_req_data[i] = 'x;
case (req_offset[i])
1: mem_req_data[i][31:8] = req_data[i][23:0];
2: mem_req_data[i][31:16] = req_data[i][15:0];
3: mem_req_data[i][31:24] = req_data[i][7:0];
default: mem_req_data[i] = req_data[i];
endcase
mem_req_addr[i] = req_addr[i][31:2];
end
end
assign dcache_req_if.valid = {`NUM_THREADS{req_valid && req_ready_dep}} & req_tmask & dup_mask & ~req_sent_mask;
assign dcache_req_if.rw = {`NUM_THREADS{~req_wb}};
assign dcache_req_if.addr = mem_req_addr;
assign dcache_req_if.byteen = mem_req_byteen;
assign dcache_req_if.data = mem_req_data;
`ifdef DBG_CACHE_REQ_INFO
assign dcache_req_if.tag = {`NUM_THREADS{{req_pc, req_wid, req_tag}}};
`else
assign dcache_req_if.tag = {`NUM_THREADS{req_tag}};
`endif
assign ready_in = req_ready_dep && req_sent_all;
// send store commit
wire is_store_rsp = req_valid && ~req_wb && req_sent_all;
// assign st_commit_if.valid = is_store_rsp;
// assign st_commit_if.wid = req_wid;
// assign st_commit_if.tmask = req_tmask;
// assign st_commit_if.PC = req_pc;
// assign st_commit_if.rd = 0;
// assign st_commit_if.wb = 0;
// assign st_commit_if.eop = 1'b1;
// assign st_commit_if.data = 0;
// load response formatting
reg [`NUM_THREADS-1:0][31:0] rsp_data;
wire [`NUM_THREADS-1:0] rsp_tmask;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
wire [31:0] src_data = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i];
reg [31:0] rsp_data_shifted;
always @(*) begin
rsp_data_shifted[31:16] = src_data[31:16];
rsp_data_shifted[15:0] = rsp_offset[i][1] ? src_data[31:16] : src_data[15:0];
rsp_data_shifted[7:0] = rsp_offset[i][0] ? rsp_data_shifted[15:8] : rsp_data_shifted[7:0];
end
always @(*) begin
case (`LSU_FMT(rsp_type))
`FMT_B: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0]));
`FMT_H: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0]));
`FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0]));
`FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0]));
default: rsp_data[i] = rsp_data_shifted;
endcase
end
end
assign rsp_tmask = rsp_is_dup ? rsp_rem_mask[mbuf_raddr] : dcache_rsp_if.valid;
// send load commit
wire load_rsp_stall = ~ld_commit_if.ready && ld_commit_if.valid;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
.RESETW (1)
) rsp_pipe_reg (
.clk (clk),
.reset (reset),
.enable (!load_rsp_stall),
.data_in ({(| dcache_rsp_if.valid), rsp_wid, rsp_tmask, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}),
.data_out ({ld_commit_if.valid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data, ld_commit_if.eop})
);
// Can accept new cache response?
assign dcache_rsp_if.ready = ~load_rsp_stall;
// scope registration
`SCOPE_ASSIGN (dcache_req_fire, dcache_req_if.valid & dcache_req_if.ready);
`SCOPE_ASSIGN (dcache_req_wid, req_wid);
`SCOPE_ASSIGN (dcache_req_pc, req_pc);
`SCOPE_ASSIGN (dcache_req_addr, req_addr);
`SCOPE_ASSIGN (dcache_req_rw, ~req_wb);
`SCOPE_ASSIGN (dcache_req_byteen,dcache_req_if.byteen);
`SCOPE_ASSIGN (dcache_req_data, dcache_req_if.data);
`SCOPE_ASSIGN (dcache_req_tag, req_tag);
`SCOPE_ASSIGN (dcache_rsp_fire, dcache_rsp_if.valid & {`NUM_THREADS{dcache_rsp_if.ready}});
`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
`ifdef DBG_PRINT_CORE_DCACHE
always @(posedge clk) begin
if ((| (dcache_req_if.valid & dcache_req_if.ready))) begin
if ((| dcache_req_if.rw))
$display("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, data=%0h",
$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data);
else
$display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, rd=%0d, is_dup=%b",
$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, req_rd, req_is_dup);
end
if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
$display("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h, is_dup=%b",
$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data, rsp_is_dup);
end
if (mbuf_full) begin
$write("%t: D$%0d queue-full:", $time, CORE_ID);
for (integer j = 0; j < `LSUQ_SIZE; j++) begin
$write(" tag%0d=%0h", j, pending_tags[j]);
end
$write("\n");
end
end
`endif
endmodule

12
hw/rtl/tex_unit/VX_tex_pt_addr.v Normal file
View file

@ -0,0 +1,12 @@
`include "VX_platform.vh"
`include "VX_define.vh"
module VX_tex_pt_addr #(
) (
);
// Need to fill in
endmodule

39
hw/rtl/tex_unit/VX_tex_unit.v
View file

@ -13,6 +13,11 @@ module VX_tex_unit #(
// Outputs
VX_tex_rsp_if tex_rsp_if
// Texture unit <-> Memory Unit
VX_dcache_core_req_if dcache_req_if,
VX_dcache_core_rsp_if dcache_rsp_if
);
`UNUSED_PARAM (CORE_ID)
@ -90,6 +95,40 @@ module VX_tex_unit #(
assign rsp_wb = tex_req_if.wb;
assign rsp_data = {`NUM_THREADS{32'hFF0000FF}}; // dummy blue value
//point sampling texel address computation
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
assign tex_req_if.v[i] = gpu_req_if.rs2_data[i];
assign tex_req_if.lod[i] = gpu_req_if.rs3_data[i][31:8];
assign tex_req_if.t[i] = gpu_req_if.rs3_data[i][7:0];
VX_tex_pt_addr #(
) tex_pt_addr (
.clk (clk),
.reset (reset),
);
end
// fifo/wait buffer for fragments and also to dcache
// texture unit <-> dcache
VX_lsu_req_if lsu_req_if();
VX_commit_if ld_commit_if();
VX_tex_memory #(
.CORE_ID(CORE_ID)
) tex_memory (
.clk (clk),
.reset (reset),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
.lsu_req_if (lsu_req_if),
.ld_commit_if (ld_commit_if)
);
// output
assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;