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Resseting GPR

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This commit is contained in:
felsabbagh3 2020-04-04 10:13:26 -07:00
parent 10e445d459
commit 70bd673031
1 changed files with 2 additions and 2 deletions
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4
rtl/byte_enabled_simple_dual_port_ram.v
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@ -25,9 +25,9 @@ module byte_enabled_simple_dual_port_ram
always @(posedge clk, posedge reset) begin
// TODO Clearing ram not currently supported on FPGA.
if (reset) begin
`ifdef ASIC
// `ifdef ASIC
for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0;
`endif
// `endif
end
else if(we) begin
integer thread_ind;