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minor updates
This commit is contained in:
Blaise Tine
parent
9b810edfe8
commit
7128082da1
5 changed files with 19 additions and 37 deletions
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@ -114,7 +114,6 @@
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`define INST_ALU_SLL 4'b1111
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`define INST_ALU_OTHER 4'b0111
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`define INST_ALU_BITS 4
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`define INST_ALU_OP(x) x[`INST_ALU_BITS-1:0]
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`define INST_ALU_CLASS(op) op[3:2]
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`define INST_ALU_SIGNED(op) op[0]
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`define INST_ALU_IS_SUB(op) (op[3:0] == 4'b1011)
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@ -137,9 +136,9 @@
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`define INST_BR_MRET 4'b1110
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`define INST_BR_OTHER 4'b1111
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`define INST_BR_BITS 4
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`define INST_BR_NEG(x) x[1]
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`define INST_BR_LESS(x) x[2]
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`define INST_BR_STATIC(x) x[3]
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`define INST_BR_NEG(op) op[1]
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`define INST_BR_LESS(op) op[2]
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`define INST_BR_STATIC(op) op[3]
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`define INST_M_MUL 3'b000
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`define INST_M_MULHU 3'b001
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@ -176,10 +175,9 @@
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`define INST_LSU_SW 4'b1010
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`define INST_LSU_SD 4'b1011 // new for RV64I SD
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`define INST_LSU_BITS 4
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`define INST_LSU_FMT(x) x[2:0]
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`define INST_LSU_WSIZE(x) x[1:0]
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`define INST_LSU_IS_MEM(x) (3'h0 == x)
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`define INST_LSU_IS_FENCE(x) (3'h1 == x)
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`define INST_LSU_FMT(op) op[2:0]
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`define INST_LSU_WSIZE(op) op[1:0]
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`define INST_LSU_IS_FENCE(mod) (mod == 1)
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`define INST_FENCE_BITS 1
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`define INST_FENCE_D 1'h0
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@ -66,15 +66,6 @@ module VX_dispatch (
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wire [`INST_LSU_BITS-1:0] lsu_op_type = `INST_LSU_BITS'(dispatch_if.op_type);
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wire lsu_is_fence = `INST_LSU_IS_FENCE(dispatch_if.op_mod);
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// USED TO TRUNCATE IMMEDIATE and RS1 TO 32 BITS
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wire [`XLEN-1:0] trunc_ibuffer_imm = ibuffer_if.imm[`XLEN-1:0];
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wire [`NUM_THREADS-1:0][`XLEN-1:0] trunc_rs1;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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// These values are used for PC calculations, so should stay as 32 bits
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assign trunc_rs1[i] = gpr_rsp_if.rs1_data[i][`XLEN-1:0];
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end
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VX_skid_buffer #(
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.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + `XLEN + `INST_LSU_BITS + 1 + `XLEN + `NR_BITS + 1 + `NUM_THREADS*`XLEN + `NUM_THREADS*`XLEN),
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.OUT_REG (1)
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@ -83,7 +74,7 @@ module VX_dispatch (
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.reset (reset),
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.valid_in (lsu_req_valid),
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.ready_in (lsu_req_ready),
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.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, lsu_op_type, lsu_is_fence, trunc_ibuffer_imm, dispatch_if.rd, dispatch_if.wb, trunc_rs1, gpr_rsp_if.rs2_data}),
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.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, lsu_op_type, lsu_is_fence, ibuffer_if.imm, dispatch_if.rd, dispatch_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
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.valid_out (lsu_req_if.valid),
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.ready_out (lsu_req_if.ready)
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@ -96,10 +87,6 @@ module VX_dispatch (
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wire [`CSR_ADDR_BITS-1:0] csr_addr = dispatch_if.imm[`CSR_ADDR_BITS-1:0];
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wire [`NRI_BITS-1:0] csr_imm = dispatch_if.imm[`CSR_ADDR_BITS +: `NRI_BITS];
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// USED TO TRUNCATE CSRs TO 32 BITS. I DONT KNOW IF THIS IS CORRECT???
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// Commenting this to fix a warning because this csr_rs1_data signal is not being used anywhere else. -Jaswanth
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// wire [31:0] csr_rs1_data = gpr_rsp_if.rs1_data[tid][31:0]; // CSR stays 32 bits
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VX_skid_buffer #(
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.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + `XLEN + `INST_CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NRI_BITS + `UP(`NT_BITS) + (`NUM_THREADS * `XLEN)),
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.OUT_REG (1)
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@ -107,15 +107,15 @@ module VX_lsu_unit #(
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wire mem_req_valid;
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wire [`NUM_THREADS-1:0] mem_req_mask;
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wire mem_req_rw;
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wire [`NUM_THREADS-1:0][`XLEN-REQ_ASHIFT-1:0] mem_req_addr;
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reg [`NUM_THREADS-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] mem_req_data;
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wire [`NUM_THREADS-1:0][`XLEN-REQ_ASHIFT-1:0] mem_req_addr;
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reg [`NUM_THREADS-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] mem_req_data;
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wire [TAG_WIDTH-1:0] mem_req_tag;
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wire mem_req_ready;
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wire mem_rsp_valid;
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wire [`NUM_THREADS-1:0] mem_rsp_mask;
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wire [`NUM_THREADS-1:0][`XLEN-1:0] mem_rsp_data;
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wire [`NUM_THREADS-1:0][`XLEN-1:0] mem_rsp_data;
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wire [TAG_WIDTH-1:0] mem_rsp_tag;
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wire mem_rsp_eop;
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wire mem_rsp_ready;
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@ -134,7 +134,7 @@ module VX_lsu_unit #(
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wire [`NUM_THREADS-1:0][REQ_ASHIFT-1:0] req_align;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0];
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assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0];
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assign mem_req_addr[i] = full_addr[i][`XLEN-1:REQ_ASHIFT];
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end
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@ -162,12 +162,10 @@ module VX_lsu_unit #(
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endcase
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end
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wire lsu_req_fire = lsu_req_if.valid && lsu_req_if.ready;
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// TODO: memory misalignment not supported!
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`RUNTIME_ASSERT(~(lsu_req_fire && `INST_LSU_WSIZE(lsu_req_if.op_type) == 1 && req_align[i][0] != 0), ("misaligned memory access!"));
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`ifdef XLEN_64
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`RUNTIME_ASSERT(~(lsu_req_fire && `INST_LSU_WSIZE(lsu_req_if.op_type) == 2 && req_align[i][1:0] != 0), ("misaligned memory access!"));
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`endif
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// memory misalignment not supported!
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wire lsu_req_fire = lsu_req_if.valid && lsu_req_if.ready;
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`RUNTIME_ASSERT((~lsu_req_fire || ~lsu_req_if.tmask[i] || lsu_req_if.is_fence || (full_addr[i] % (1 << `INST_LSU_WSIZE(lsu_req_if.op_type))) == 0),
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("misaligned memory access, PC=0x%0h, addr=0x%0h, wsize=%0d!", lsu_req_if.PC, full_addr[i], `INST_LSU_WSIZE(lsu_req_if.op_type)));
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always @(*) begin
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mem_req_data[i] = lsu_req_if.store_data[i];
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@ -9,8 +9,8 @@ interface VX_lsu_req_if ();
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wire [`XLEN-1:0] PC;
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wire [`INST_LSU_BITS-1:0] op_type;
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wire is_fence;
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wire [`NUM_THREADS-1:0][`XLEN-1:0] store_data;
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wire [`NUM_THREADS-1:0][`XLEN-1:0] base_addr;
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wire [`NUM_THREADS-1:0][`XLEN-1:0] store_data;
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wire [`NUM_THREADS-1:0][`XLEN-1:0] base_addr;
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wire [`XLEN-1:0] offset;
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wire [`NR_BITS-1:0] rd;
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wire wb;
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@ -2,7 +2,7 @@ XLEN ?= 32
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TARGET ?= opaesim
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XRT_SYN_DIR ?= ../../../hw/syn/xilinx/xrt
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XRT_SYN_DIR ?= ../../../hw/syn/xilinx/xrt
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ifeq ($(XLEN),64)
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RISCV_TOOLCHAIN_PATH ?= /opt/riscv64-gnu-toolchain
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@ -54,7 +54,6 @@ VX_CFLAGS += -DLLVM_VORTEX
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VX_LDFLAGS += -Wl,-Bstatic,--gc-sections,-T,$(VORTEX_KN_PATH)/linker/vx_link$(XLEN).ld $(VORTEX_KN_PATH)/libvortexrt.a
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CXXFLAGS += -std=c++17 -Wall -Wextra -pedantic -Wfatal-errors
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CXXFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_KN_PATH)/../hw
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LDFLAGS += -L$(VORTEX_RT_PATH)/stub -lvortex
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