mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
Tex CSRs write support added
This commit is contained in:
Krishna Yalamarthy
Blaise Tine
parent
7587876820
commit
72e06ef4fe
14 changed files with 166 additions and 7 deletions
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@ -3,6 +3,8 @@
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#define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000
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// #include <vortex.h>
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struct kernel_arg_t {
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uint32_t num_tasks;
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uint32_t task_size;
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Binary file not shown.
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@ -141,6 +141,7 @@ int main(int argc, char *argv[]) {
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kernel_arg.num_tasks = num_tasks;
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kernel_arg.task_size = count;
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kernel_arg.device_ptr = device;
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std::cout << "dev_src0=" << std::hex << kernel_arg.src0_ptr << std::endl;
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std::cout << "dev_src1=" << std::hex << kernel_arg.src1_ptr << std::endl;
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@ -14,7 +14,9 @@ void kernel_body(int task_id, void* arg) {
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unsigned u = 1;
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unsigned v = 1;
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unsigned t = 1;
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// vx_csr_set(_arg->device_ptr, 0, 0xfd0, 0xffd);
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uint32_t offset = task_id * count;
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for (uint32_t i = 0; i < count; ++i) {
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@ -1,5 +1,5 @@
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2021-03-12 17:51:37.263369
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// Generated at 2021-03-13 13:57:30.622905
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#ifndef VX_USER_CONFIG
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#define VX_USER_CONFIG
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@ -7,7 +7,7 @@
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#endif
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2021-03-12 17:51:37.265050
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// Generated at 2021-03-13 13:57:30.624676
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// Translated from VX_config.vh:
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@ -246,6 +246,31 @@
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#define CSR_NW 0xFC1
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#define CSR_NC 0xFC2
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////////// Texture Unit CSRs /////////////
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#define CSR_TEX_BEGIN 0xFD0
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// Unit 1
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#define CSR_TEX0_ADDR CSR_TEX_BEGIN
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#define CSR_TEX0_FORMAT CSR_TEX_BEGIN + 0x1
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#define CSR_TEX0_WIDTH CSR_TEX_BEGIN + 0x2
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#define CSR_TEX0_HEIGHT CSR_TEX_BEGIN + 0x3
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#define CSR_TEX0_STRIDE CSR_TEX_BEGIN + 0x4
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#define CSR_TEX0_WRAP_U CSR_TEX_BEGIN + 0x5
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#define CSR_TEX0_WRAP_V CSR_TEX_BEGIN + 0x6
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#define CSR_TEX0_MIN_FILTER CSR_TEX_BEGIN + 0x7
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#define CSR_TEX0_MAX_FILTER CSR_TEX_BEGIN + 0x8
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// Unit 2
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#define CSR_TEX1_ADDR CSR_TEX_BEGIN + 0x9
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#define CSR_TEX1_FORMAT CSR_TEX_BEGIN + 0xA
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#define CSR_TEX1_WIDTH CSR_TEX_BEGIN + 0xB
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#define CSR_TEX1_HEIGHT CSR_TEX_BEGIN + 0xC
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#define CSR_TEX1_STRIDE CSR_TEX_BEGIN + 0xD
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#define CSR_TEX1_WRAP_U CSR_TEX_BEGIN + 0xE
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#define CSR_TEX1_WRAP_V CSR_TEX_BEGIN + 0xF
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#define CSR_TEX1_MIN_FILTER CSR_TEX_BEGIN + 0x10
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#define CSR_TEX1_MAX_FILTER CSR_TEX_BEGIN + 0x11
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#define CSR_TEX_END CSR_TEX1_MAX_FILTER
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of LSU Request Queue
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@ -233,6 +233,31 @@
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`define CSR_NW 12'hFC1
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`define CSR_NC 12'hFC2
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////////// Texture Unit CSRs /////////////
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`define CSR_TEX_BEGIN 12'hFD0
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// Unit 1
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`define CSR_TEX0_ADDR `CSR_TEX_BEGIN
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`define CSR_TEX0_FORMAT `CSR_TEX_BEGIN + 12'h1
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`define CSR_TEX0_WIDTH `CSR_TEX_BEGIN + 12'h2
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`define CSR_TEX0_HEIGHT `CSR_TEX_BEGIN + 12'h3
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`define CSR_TEX0_STRIDE `CSR_TEX_BEGIN + 12'h4
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`define CSR_TEX0_WRAP_U `CSR_TEX_BEGIN + 12'h5
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`define CSR_TEX0_WRAP_V `CSR_TEX_BEGIN + 12'h6
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`define CSR_TEX0_MIN_FILTER `CSR_TEX_BEGIN + 12'h7
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`define CSR_TEX0_MAX_FILTER `CSR_TEX_BEGIN + 12'h8
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// Unit 2
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`define CSR_TEX1_ADDR `CSR_TEX_BEGIN + 12'h9
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`define CSR_TEX1_FORMAT `CSR_TEX_BEGIN + 12'hA
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`define CSR_TEX1_WIDTH `CSR_TEX_BEGIN + 12'hB
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`define CSR_TEX1_HEIGHT `CSR_TEX_BEGIN + 12'hC
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`define CSR_TEX1_STRIDE `CSR_TEX_BEGIN + 12'hD
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`define CSR_TEX1_WRAP_U `CSR_TEX_BEGIN + 12'hE
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`define CSR_TEX1_WRAP_V `CSR_TEX_BEGIN + 12'hF
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`define CSR_TEX1_MIN_FILTER `CSR_TEX_BEGIN + 12'h10
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`define CSR_TEX1_MAX_FILTER `CSR_TEX_BEGIN + 12'h11
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`define CSR_TEX_END `CSR_TEX1_MAX_FILTER
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of LSU Request Queue
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@ -13,6 +13,7 @@ module VX_csr_data #(
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VX_cmt_to_csr_if cmt_to_csr_if,
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VX_fpu_to_csr_if fpu_to_csr_if,
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VX_tex_csr_if tex_csr_if,
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input wire read_enable,
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input wire[`CSR_ADDR_BITS-1:0] read_addr,
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@ -53,7 +54,7 @@ module VX_csr_data #(
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| fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0];
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end
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if (write_enable) begin
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if (write_enable && (write_addr > `CSR_TEX_END || write_addr < `CSR_TEX_BEGIN)) begin
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case (write_addr)
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`CSR_FFLAGS: fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
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`CSR_FRM: fcsr[write_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
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@ -79,6 +80,11 @@ module VX_csr_data #(
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end
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end
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//write tex csrs
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assign tex_csr_if.write_addr = write_addr;
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assign tex_csr_if.write_data = write_data;
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assign tex_csr_if.write_enable = write_enable;
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always @(posedge clk) begin
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if (reset) begin
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csr_cycle <= 0;
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@ -12,7 +12,8 @@ module VX_csr_unit #(
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`endif
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VX_cmt_to_csr_if cmt_to_csr_if,
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VX_fpu_to_csr_if fpu_to_csr_if,
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VX_fpu_to_csr_if fpu_to_csr_if,
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VX_tex_csr_if tex_csr_if,
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VX_csr_io_req_if csr_io_req_if,
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VX_csr_io_rsp_if csr_io_rsp_if,
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@ -62,6 +63,7 @@ module VX_csr_unit #(
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`endif
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.cmt_to_csr_if (cmt_to_csr_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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.tex_csr_if (tex_csr_if),
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.read_enable (csr_pipe_req_if.valid),
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.read_addr (csr_pipe_req_if.addr),
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.read_wid (csr_pipe_req_if.wid),
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@ -385,6 +385,7 @@
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`define XDRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH+`CLOG2(2))
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////////////////////////// Texture Unit Configurable Knobs //////////////////////////////
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`define NUM_TEX_UNITS 2
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`define MADDRW 8
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`define MAXWTW 8
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`define MAXHTW 8
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@ -45,6 +45,8 @@ module VX_execute #(
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output wire ebreak
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);
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VX_fpu_to_csr_if fpu_to_csr_if();
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VX_tex_csr_if tex_csr_if();
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wire[`NUM_WARPS-1:0] csr_pending;
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wire[`NUM_WARPS-1:0] fpu_pending;
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@ -82,6 +84,7 @@ module VX_execute #(
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`endif
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.cmt_to_csr_if (cmt_to_csr_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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.tex_csr_if (tex_csr_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.csr_req_if (csr_req_if),
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@ -129,7 +132,8 @@ module VX_execute #(
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.reset (reset),
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.gpu_req_if (gpu_req_if),
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.warp_ctl_if (warp_ctl_if),
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.gpu_commit_if (gpu_commit_if)
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.gpu_commit_if (gpu_commit_if),
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.tex_csr_if (tex_csr_if)
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);
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assign ebreak = alu_req_if.valid
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@ -10,6 +10,7 @@ module VX_gpu_unit #(
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// Inputs
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VX_gpu_req_if gpu_req_if,
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VX_tex_csr_if tex_csr_if,
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// Outputs
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VX_warp_ctl_if warp_ctl_if,
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@ -99,6 +100,7 @@ module VX_gpu_unit #(
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.reset (reset),
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.tex_req_if (tex_req_if),
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.tex_csr_if (tex_csr_if),
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.tex_rsp_if (tex_rsp_if)
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);
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20
hw/rtl/interfaces/VX_tex_csr_if.v
Normal file
20
hw/rtl/interfaces/VX_tex_csr_if.v
Normal file
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@ -0,0 +1,20 @@
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`ifndef VX_TEX_CSR_IF
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`define VX_TEX_CSR_IF
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`include "VX_define.vh"
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interface VX_tex_csr_if ();
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// wire read_enable;
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// wire[`CSR_ADDR_BITS-1:0] read_addr;
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// wire[`NW_BITS-1:0] read_wid;
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// wire[31:0] read_data;
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wire write_enable;
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wire[`CSR_ADDR_BITS-1:0] write_addr;
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// wire[`NW_BITS-1:0] write_wid;
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wire[`CSR_WIDTH-1:0] write_data;
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endinterface
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`endif
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@ -8,6 +8,7 @@ interface VX_tex_req_if ();
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wire [`NUM_THREADS-1:0][31:0] u;
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wire [`NUM_THREADS-1:0][31:0] v;
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wire [`NUM_THREADS-1:0][31:0] lod_t;
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// wire [`NUM_THREADS-1:0][7:0] t;
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// wire [`MADDRW-1:0] addr;
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// wire [`MAXWTW-1:0] width;
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// wire [`MAXHTW-1:0] height;
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@ -8,6 +8,7 @@ module VX_tex_unit #(
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input wire reset,
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// Inputs
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VX_tex_req_if tex_req_if,
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VX_tex_csr_if tex_csr_if,
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// Outputs
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VX_tex_rsp_if tex_rsp_if
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@ -43,8 +44,58 @@ module VX_tex_unit #(
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// output wire cache_rsp_ready
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);
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`UNUSED_VAR (clk)
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// `UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (reset)
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`UNUSED_VAR(tex_addr)
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`UNUSED_VAR(tex_format)
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`UNUSED_VAR(tex_width)
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`UNUSED_VAR(tex_height)
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`UNUSED_VAR(tex_stride)
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`UNUSED_VAR(tex_wrap_u)
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`UNUSED_VAR(tex_wrap_v)
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`UNUSED_VAR(tex_min_filter)
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`UNUSED_VAR(tex_max_filter)
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reg [`CSR_WIDTH-1:0] tex_addr [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_wrap_u [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_wrap_v [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_min_filter [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_max_filter [`NUM_TEX_UNITS-1: 0];
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//tex csr programming, need to make make consistent with `NUM_TEX_UNITS
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always @(posedge clk ) begin
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if (tex_csr_if.write_enable) begin
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case (tex_csr_if.write_addr)
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`CSR_TEX0_ADDR : tex_addr[0] <= tex_csr_if.write_data;
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`CSR_TEX0_FORMAT : tex_format[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WIDTH : tex_width[0] <= tex_csr_if.write_data;
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`CSR_TEX0_HEIGHT : tex_height[0] <= tex_csr_if.write_data;
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`CSR_TEX0_STRIDE : tex_stride[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WRAP_U : tex_wrap_u[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WRAP_V : tex_wrap_v[0] <= tex_csr_if.write_data;
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`CSR_TEX0_MIN_FILTER : tex_min_filter[0] <= tex_csr_if.write_data;
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`CSR_TEX0_MAX_FILTER : tex_max_filter[0] <= tex_csr_if.write_data;
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`CSR_TEX1_ADDR : tex_addr[1] <= tex_csr_if.write_data;
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`CSR_TEX1_FORMAT : tex_format[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WIDTH : tex_width[1] <= tex_csr_if.write_data;
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`CSR_TEX1_HEIGHT : tex_height[1] <= tex_csr_if.write_data;
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`CSR_TEX1_STRIDE : tex_stride[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WRAP_U : tex_wrap_u[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WRAP_V : tex_wrap_v[1] <= tex_csr_if.write_data;
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`CSR_TEX1_MIN_FILTER : tex_min_filter[1] <= tex_csr_if.write_data;
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`CSR_TEX1_MAX_FILTER : tex_max_filter[1] <= tex_csr_if.write_data;
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default:
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assert(tex_csr_if.write_addr > `CSR_TEX_END || tex_csr_if.write_addr < `CSR_TEX_BEGIN) else $error("%t: invalid CSR write address: %0h", $time, tex_csr_if.write_addr);
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endcase
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tex_rsp_if.data[i] = 32'hFAAF;
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@ -52,4 +103,21 @@ module VX_tex_unit #(
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assign tex_rsp_if.ready = 1'b1;
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`ifdef DBG_PRINT_TEX_CSRS
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always @(posedge clk) begin
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if (tex_csr_if.write_addr <= `CSR_TEX_END || tex_csr_if.write_addr >= `CSR_TEX_BEGIN) begin
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$display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_stride, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]);
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end
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end
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`endif
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endmodule
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