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fix sources.txt, run_ase.sh

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This commit is contained in:
Blaise Tine 2020-06-29 12:52:28 -07:00
parent f0046fed3c
commit 75d66dc335
6 changed files with 18 additions and 14 deletions
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1
hw/opae/README
View file

@ -62,6 +62,7 @@ make ase
# tests
./run_ase.sh build_ase_1c ../../driver/tests/basic/basic
./run_ase.sh build_ase_1c ../../driver/tests/demo/demo
./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd
# modify "vsim_run.tcl" to dump VCD trace
vcd file vortex.vcd

5
hw/opae/run_ase.sh
View file

@ -7,6 +7,9 @@ BUILD_DIR=$1
PROGRAM=$(basename "$2")
PROGRAM_DIR=`dirname $2`
POCL_RT_PATH=$SCRIPT_DIR/../../benchmarks/opencl/runtime/lib
VORTEX_DRV_PATH=$SCRIPT_DIR/../../driver/opae/ase
# Export ASE_WORKDIR variable
export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work
@ -33,5 +36,5 @@ done
# run application
pushd $PROGRAM_DIR
echo " [DBG] running ./$PROGRAM $*"
ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$LD_LIBRARY_PATH ./$PROGRAM $*
ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH:$VORTEX_DRV_PATH:$LD_LIBRARY_PATH ./$PROGRAM $*
popd

1
hw/opae/sources.txt
View file

@ -67,6 +67,7 @@ QI:vortex_afu.qsf
../rtl/libs/VX_priority_encoder.v
../rtl/libs/VX_generic_queue.v
../rtl/libs/VX_indexable_queue.v
../rtl/libs/VX_fair_arbiter.v
../rtl/libs/VX_fixed_arbiter.v
../rtl/libs/VX_rr_arbiter.v
../rtl/libs/VX_countones.v

13
hw/rtl/VX_alu_unit.v
View file

@ -13,9 +13,6 @@ module VX_alu_unit (
output reg [31:0] alu_result,
output reg alu_stall
);
localparam DIV_PIPELINE_LEN = 18;
localparam MUL_PIPELINE_LEN = 1;
wire[31:0] div_result_unsigned;
wire[31:0] div_result_signed;
@ -37,11 +34,11 @@ module VX_alu_unit (
`ALU_DIV,
`ALU_DIVU,
`ALU_REM,
`ALU_REMU: inst_delay = DIV_PIPELINE_LEN;
`ALU_REMU: inst_delay = `DIV_LATENCY;
`ALU_MUL,
`ALU_MULH,
`ALU_MULHSU,
`ALU_MULHU: inst_delay = MUL_PIPELINE_LEN;
`ALU_MULHU: inst_delay = `MUL_LATENCY;
default: inst_delay = 0;
endcase
end
@ -91,7 +88,7 @@ module VX_alu_unit (
.WIDTHD(32),
.NSIGNED(0),
.DSIGNED(0),
.PIPELINE(DIV_PIPELINE_LEN)
.PIPELINE(`DIV_LATENCY)
) udiv (
.clk(clk),
.reset(reset),
@ -106,7 +103,7 @@ module VX_alu_unit (
.WIDTHD(32),
.NSIGNED(1),
.DSIGNED(1),
.PIPELINE(DIV_PIPELINE_LEN)
.PIPELINE(`DIV_LATENCY)
) sdiv (
.clk(clk),
.reset(reset),
@ -124,7 +121,7 @@ module VX_alu_unit (
.WIDTHB(33),
.WIDTHP(64),
.SIGNED(1),
.PIPELINE(MUL_PIPELINE_LEN)
.PIPELINE(`MUL_LATENCY)
) multiplier (
.clk(clk),
.reset(reset),

4
hw/rtl/VX_define.vh
View file

@ -72,6 +72,10 @@
`define CSR_WIDTH 12
`define DIV_LATENCY 16
`define MUL_LATENCY 1
///////////////////////////////////////////////////////////////////////////////
`define BYTE_EN_NO 3'h7

8
hw/rtl/libs/VX_fair_arbiter.v
View file

@ -11,7 +11,6 @@ module VX_fair_arbiter #(
output wire grant_valid
);
if (N == 1) begin
`UNUSED_VAR (clk)
@ -20,8 +19,7 @@ module VX_fair_arbiter #(
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
end else begin
reg [N-1:0] requests_use;
wire [N-1:0] update_value;
@ -48,7 +46,7 @@ module VX_fair_arbiter #(
reg [N-1:0] grant_onehot_r;
VX_priority_encoder # (
VX_priority_encoder #(
.N(N)
) priority_encoder (
.data_in (requests_use),
@ -61,7 +59,7 @@ module VX_fair_arbiter #(
grant_onehot_r[grant_index] = 1;
end
assign grant_onehot = grant_onehot_r;
assign late_value = ((refill_original ^ requests) & ~refill_original);
assign late_value = ((refill_original ^ requests) & ~refill_original);
assign update_value = (requests_use & ~grant_onehot_r) | late_value;
end