mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
optimized opae cci to dev memcpy using double buffering and request window to work around unordered read requests
This commit is contained in:
Blaise Tine
parent
3e64cb4380
commit
77a52ea20b
10 changed files with 249 additions and 110 deletions
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@ -57,6 +57,12 @@ int vx_start(vx_device_h hdevice);
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// Wait for device ready with milliseconds timeout
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int vx_ready_wait(vx_device_h hdevice, long long timeout);
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// set device constant registers
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int vx_set_regiters(int state, int value);
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// get device constant registers
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int vx_get_regiters(int state, int* value);
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////////////////////////////// UTILITY FUNCIONS ///////////////////////////////
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// upload kernel bytes to device
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Binary file not shown.
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@ -38,9 +38,13 @@ make clean
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make
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./basic
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ASE build instructions
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#ASE build instructions
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vcd file vortex.vcd
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vcd add -r /*/Vortex/hw/rtl/*
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run -all
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run -all
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#compress
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tar -zcvf vortex.vcd.tar.gz work/vortex.vcd
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# decompress
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tar -zxvf vortex.vcd.tar.gz vortex.vcd
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@ -72,7 +72,7 @@ vortex_afu.json
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../rtl/VX_dmem_ctrl.v
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../rtl/VX_alu_unit.v
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../rtl/VX_csr_data.v
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../rtl/VX_lsu_uint.v
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../rtl/VX_lsu_unit.v
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../rtl/VX_decode.v
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../rtl/VX_inst_multiplex.v
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../rtl/VX_csr_wrapper.v
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@ -1,12 +1,7 @@
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// Interface between CSR and FSM
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// All the MMIOs read/write are done from CSR and passed to the FSM for state transitions
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// To be done:
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// Change address size to buffer's address size and data size based on IO address size. Check from hello_world
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`include "platform_if.vh"
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import local_mem_cfg_pkg::*;
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`include "afu_json_info.vh"
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`include "VX_define.vh"
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module vortex_afu #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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@ -35,6 +30,9 @@ module vortex_afu #(
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localparam AVS_RD_QUEUE_SIZE = 16;
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localparam CCI_RD_WINDOW_SIZE = 8;
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localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE;
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localparam VX_SNOOP_DELAY = 300;
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localparam VX_SNOOP_LEVELS = 2;
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@ -62,6 +60,9 @@ typedef enum logic[3:0] {
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STATE_CLFLUSH
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} state_t;
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typedef logic [`LOG2UP(CCI_RD_WINDOW_SIZE)-1:0] t_cci_rdq_tag;
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typedef logic [$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:0] t_cci_rdq_data;
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state_t state;
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// Vortex signals /////////////////////////////////////////////////////////////
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@ -117,8 +118,7 @@ end
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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begin
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if (SoftReset) begin
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af2cp_sTxPort.c2.hdr <= 0;
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af2cp_sTxPort.c2.data <= 0;
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af2cp_sTxPort.c2.mmioRdValid <= 0;
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@ -152,12 +152,17 @@ begin
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csr_cmd <= $bits(csr_cmd)'(cp2af_sRxPort.c0.data);
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$display("%t: CSR_CMD: %0d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data));
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end
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default: begin
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// user-defined CSRs
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//if (mmioHdr.addres >= MMIO_CSR_USER) begin
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// write Vortex CRS
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//end
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end
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endcase
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end
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// serve MMIO read requests
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if (cp2af_sRxPort.c0.mmioRdValid)
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begin
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if (cp2af_sRxPort.c0.mmioRdValid) begin
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af2cp_sTxPort.c2.hdr.tid <= mmioHdr.tid; // copy TID
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case (mmioHdr.address)
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// AFU header
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@ -176,8 +181,9 @@ begin
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16'h0006: af2cp_sTxPort.c2.data <= 64'h0; // next AFU
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16'h0008: af2cp_sTxPort.c2.data <= 64'h0; // reserved
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MMIO_CSR_STATUS: begin
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if (state != af2cp_sTxPort.c2.data)
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if (state != af2cp_sTxPort.c2.data) begin
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$display("%t: STATUS: state=%0d", $time, state);
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end
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af2cp_sTxPort.c2.data <= state;
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end
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default: af2cp_sTxPort.c2.data <= 64'h0;
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@ -198,8 +204,7 @@ logic vx_reset;
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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begin
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if (SoftReset) begin
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state <= STATE_IDLE;
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vx_reset <= 0;
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end
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@ -217,7 +222,7 @@ begin
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CMD_TYPE_WRITE: begin
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$display("%t: STATE WRITE: ia=%h da=%h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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state <= STATE_WRITE;
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end
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end
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CMD_TYPE_RUN: begin
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$display("%t: STATE START", $time);
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vx_reset <= 1;
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@ -231,29 +236,25 @@ begin
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end
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STATE_READ: begin
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if (cci_write_ctr >= csr_data_size)
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begin
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if (cci_write_ctr >= csr_data_size) begin
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state <= STATE_IDLE;
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end
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end
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STATE_WRITE: begin
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if (avs_write_ctr >= csr_data_size)
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begin
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if (avs_write_ctr >= csr_data_size) begin
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state <= STATE_IDLE;
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end
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end
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STATE_RUN: begin
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if (vx_ebreak)
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begin
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if (vx_ebreak) begin
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state <= STATE_IDLE;
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end
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end
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STATE_CLFLUSH: begin
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if (vx_snoop_delay >= VX_SNOOP_DELAY)
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begin
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if (vx_snoop_delay >= VX_SNOOP_DELAY) begin
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state <= STATE_IDLE;
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end
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end
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@ -264,6 +265,20 @@ end
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// AVS Controller /////////////////////////////////////////////////////////////
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logic cci_rdq_empty;
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t_cci_rdq_data cci_rdq_dout;
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logic cci_rdq_pop;
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t_ccip_clAddr next_avs_address;
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always_comb
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begin
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next_avs_address = csr_mem_addr + {avs_write_ctr[31:$bits(t_cci_rdq_tag)], t_cci_rdq_tag'(cci_rdq_dout)};
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cci_rdq_pop = (state == STATE_WRITE
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&& !cci_rdq_empty
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&& !avs_waitrequest
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&& avs_write_ctr < csr_data_size);
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end
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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@ -295,22 +310,21 @@ begin
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&& !avs_waitrequest
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&& avs_read_ctr < csr_data_size)
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begin
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avs_address <= csr_mem_addr + avs_read_ctr;
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avs_read <= 1;
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avs_address <= csr_mem_addr + avs_read_ctr;
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avs_read_ctr <= avs_read_ctr + 1;
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avs_read <= 1;
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$display("%t: AVS Rd Req: addr=%h", $time, csr_mem_addr + avs_read_ctr);
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end
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end
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STATE_WRITE: begin
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if (cp2af_sRxPort.c0.rspValid
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&& avs_write_ctr < csr_data_size)
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begin
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avs_writedata <= cp2af_sRxPort.c0.data;
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avs_address <= csr_mem_addr + avs_write_ctr;
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avs_write <= 1;
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if (cci_rdq_pop)
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begin
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avs_writedata <= cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)];
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avs_address <= next_avs_address;
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avs_write_ctr <= avs_write_ctr + 1;
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$display("%t: AVS Wr Req: addr=%h (%0d/%0d)", $time, csr_mem_addr + avs_write_ctr, avs_write_ctr + 1, csr_data_size);
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avs_write <= 1;
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$display("%t: AVS Wr Req: addr=%h (%0d/%0d)", $time, next_avs_address, avs_write_ctr + 1, csr_data_size);
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end
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end
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@ -319,7 +333,7 @@ begin
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&& vx_dram_req_ready)
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begin
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avs_address <= (vx_dram_req_addr >> 6);
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avs_read <= 1;
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avs_read <= 1;
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$display("%t: AVS Rd Req: addr=%h", $time, vx_dram_req_addr >> 6);
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end
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@ -327,8 +341,8 @@ begin
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&& vx_dram_req_ready)
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begin
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avs_writedata <= vx_dram_req_data;
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avs_address <= (vx_dram_req_addr >> 6);
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avs_write <= 1;
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avs_address <= (vx_dram_req_addr >> 6);
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avs_write <= 1;
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$display("%t: AVS Wr Req: addr=%h", $time, vx_dram_req_addr >> 6);
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end
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end
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@ -362,11 +376,11 @@ end
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// AVS address read request queue /////////////////////////////////////////////
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logic cci_write_req;
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logic cci_wr_req;
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always_comb
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begin
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avs_raq_pop = vx_dram_rsp_valid || cci_write_req;
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avs_raq_pop = vx_dram_rsp_valid || cci_wr_req;
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avs_raq_din = avs_address;
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avs_raq_push = avs_read;
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end
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@ -374,7 +388,7 @@ end
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VX_generic_queue #(
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.DATAW($bits(t_local_mem_addr)),
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.SIZE(AVS_RD_QUEUE_SIZE)
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) vx_rd_addr_queue (
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) avs_rd_req_queue (
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.clk (clk),
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.reset (SoftReset),
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.push (avs_raq_push),
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@ -397,7 +411,7 @@ end
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VX_generic_queue #(
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.DATAW($bits(t_local_mem_data)),
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.SIZE(AVS_RD_QUEUE_SIZE)
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) vx_rd_data_queue (
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) avs_rd_rsp_queue (
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.clk (clk),
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.reset (SoftReset),
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.push (avs_rdq_push),
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@ -410,101 +424,134 @@ VX_generic_queue #(
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// CCI Read Request ///////////////////////////////////////////////////////////
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t_ccip_c0_ReqMemHdr rd_hdr;
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t_ccip_c0_ReqMemHdr cci_read_hdr;
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logic cci_read_pending;
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logic [31:0] cci_read_ctr;
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t_cci_rdq_tag cci_rdq_ctr;
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logic cci_rdq_full;
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logic cci_rdq_push;
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t_cci_rdq_data cci_rdq_din;
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logic cci_read_wait;
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always_comb
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begin
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rd_hdr = t_ccip_c0_ReqMemHdr'(0);
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rd_hdr.address = csr_io_addr + avs_write_ctr;
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cci_read_hdr = t_ccip_c0_ReqMemHdr'(0);
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cci_read_hdr.address = csr_io_addr + cci_read_ctr;
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cci_read_hdr.mdata = t_cci_rdq_tag'(cci_read_ctr);
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cci_rdq_push = (STATE_WRITE == state) && cp2af_sRxPort.c0.rspValid;
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cci_rdq_din = {cp2af_sRxPort.c0.data, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata)};
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end
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// Send read requests to CCI
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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begin
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if (SoftReset) begin
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af2cp_sTxPort.c0.hdr <= 0;
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af2cp_sTxPort.c0.valid <= 0;
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cci_read_pending <= 0;
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cci_read_ctr <= 0;
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cci_rdq_ctr <= 0;
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cci_read_wait <= 0;
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end
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else begin
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af2cp_sTxPort.c0.valid <= 0;
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if (STATE_WRITE == state
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&& !cp2af_sRxPort.c0TxAlmFull // ensure read queue not full
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&& !avs_waitrequest // ensure AVS write queue not full
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&& !cci_read_pending // ensure no read pending
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&& avs_write_ctr < csr_data_size) // ensure not done
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begin
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af2cp_sTxPort.c0.hdr <= rd_hdr;
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af2cp_sTxPort.c0.valid <= 1;
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cci_read_pending <= 1;
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$display("%t: CCI Rd Req: addr=%h", $time, rd_hdr.address);
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if (STATE_IDLE == state) begin
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cci_read_ctr <= 0;
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cci_rdq_ctr <= 0;
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cci_read_wait <= 0;
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end
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if (cci_read_pending
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&& cp2af_sRxPort.c0.rspValid)
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if (STATE_WRITE == state
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&& !cp2af_sRxPort.c0TxAlmFull // ensure read queue not full
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&& !cci_rdq_full // ensure destination queue not full
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&& !cci_read_wait // ensure the last batch has arrived
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&& cci_read_ctr < csr_data_size) // ensure not done
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begin
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$display("%t: CCI Rd Rsp", $time);
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cci_read_pending <= 0;
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end
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af2cp_sTxPort.c0.hdr <= cci_read_hdr;
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af2cp_sTxPort.c0.valid <= 1;
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cci_read_ctr <= cci_read_ctr + 1;
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if (cci_read_ctr == (CCI_RD_WINDOW_SIZE-1)) begin
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cci_read_wait <= 1; // end current request batch
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end
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$display("%t: CCI Rd Req: addr=%h", $time, cci_read_hdr.address);
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end
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if (cci_rdq_push) begin
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cci_rdq_ctr <= cci_rdq_ctr + 1;
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if (cci_rdq_ctr == (CCI_RD_WINDOW_SIZE-1)) begin
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cci_read_wait <= 0; // restart new request batch
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end
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$display("%t: CCI Rd Rsp: idx=%d, ctr=%d", $time, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata), cci_rdq_ctr);
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end
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end
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end
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VX_generic_queue #(
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.DATAW($bits(t_ccip_clData) + $bits(t_cci_rdq_tag)),
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.SIZE(CCI_RD_QUEUE_SIZE)
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) cci_rd_req_queue (
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.clk (clk),
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.reset (SoftReset),
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.push (cci_rdq_push),
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.data_in (cci_rdq_din),
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.pop (cci_rdq_pop),
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.data_out (cci_rdq_dout),
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.empty (cci_rdq_empty),
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.full (cci_rdq_full)
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);
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// CCI Write Request //////////////////////////////////////////////////////////
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t_ccip_c1_ReqMemHdr wr_hdr;
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t_ccip_c1_ReqMemHdr cci_write_hdr;
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logic cci_write_pending;
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logic cci_write_wait;
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always_comb
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begin
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cci_write_req = (STATE_READ == state)
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&& !avs_rdq_empty
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&& !cp2af_sRxPort.c1TxAlmFull
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&& !cci_write_pending
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&& cci_write_ctr < csr_data_size;
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cci_wr_req = (STATE_READ == state)
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&& !avs_rdq_empty
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&& !cp2af_sRxPort.c1TxAlmFull
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&& !cci_write_wait
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&& cci_write_ctr < csr_data_size;
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wr_hdr = t_ccip_c1_ReqMemHdr'(0);
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wr_hdr.address = csr_io_addr + cci_write_ctr;
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wr_hdr.sop = 1; // single line write mode
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cci_write_hdr = t_ccip_c1_ReqMemHdr'(0);
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cci_write_hdr.address = csr_io_addr + cci_write_ctr;
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cci_write_hdr.sop = 1; // single line write mode
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end
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// Send write requests to CCI
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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begin
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if (SoftReset) begin
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af2cp_sTxPort.c1.hdr <= 0;
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af2cp_sTxPort.c1.data <= 0;
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af2cp_sTxPort.c1.valid <= 0;
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cci_write_ctr <= 0;
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cci_write_pending <= 0;
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cci_write_wait <= 0;
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end
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else begin
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af2cp_sTxPort.c1.valid <= 0;
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if (STATE_IDLE == state)
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begin
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if (STATE_IDLE == state) begin
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cci_write_ctr <= 0;
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end
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if (cci_write_req)
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begin
|
||||
af2cp_sTxPort.c1.hdr <= wr_hdr;
|
||||
if (cci_wr_req) begin
|
||||
af2cp_sTxPort.c1.hdr <= cci_write_hdr;
|
||||
af2cp_sTxPort.c1.data <= t_ccip_clData'(avs_rdq_dout);
|
||||
af2cp_sTxPort.c1.valid <= 1;
|
||||
cci_write_pending <= 1;
|
||||
$display("%t: CCI Wr Req: addr=%h", $time, wr_hdr.address);
|
||||
cci_write_wait <= 1;
|
||||
$display("%t: CCI Wr Req: addr=%h", $time, cci_write_hdr.address);
|
||||
end
|
||||
|
||||
if (cci_write_pending
|
||||
if (cci_write_wait
|
||||
&& cp2af_sRxPort.c1.rspValid)
|
||||
begin
|
||||
cci_write_ctr <= cci_write_ctr + 1;
|
||||
cci_write_pending <= 0;
|
||||
cci_write_ctr <= cci_write_ctr + 1;
|
||||
cci_write_wait <= 0;
|
||||
$display("%t: CCI Wr Rsp (%0d/%0d)", $time, cci_write_ctr + 1, csr_data_size);
|
||||
end
|
||||
end
|
||||
|
|
@ -514,15 +561,13 @@ end
|
|||
|
||||
always_ff @(posedge clk)
|
||||
begin
|
||||
if (SoftReset)
|
||||
begin
|
||||
if (SoftReset) begin
|
||||
vx_snp_req <= 0;
|
||||
vx_snoop_ctr <= 0;
|
||||
vx_snoop_delay <= 0;
|
||||
end
|
||||
else begin
|
||||
if (STATE_IDLE == state)
|
||||
begin
|
||||
if (STATE_IDLE == state) begin
|
||||
vx_snoop_ctr <= 0;
|
||||
vx_snoop_delay <= 0;
|
||||
end
|
||||
|
|
@ -532,14 +577,13 @@ begin
|
|||
if ((STATE_CLFLUSH == state)
|
||||
&& vx_snoop_ctr < csr_data_size
|
||||
&& vx_snp_req_ready)
|
||||
begin
|
||||
begin
|
||||
vx_snp_req_addr <= (csr_mem_addr + vx_snoop_ctr) << 6;
|
||||
vx_snp_req <= 1;
|
||||
vx_snoop_ctr <= vx_snoop_ctr + 1;
|
||||
end
|
||||
|
||||
if (vx_snoop_ctr == csr_data_size)
|
||||
begin
|
||||
if (vx_snoop_ctr == csr_data_size) begin
|
||||
vx_snoop_delay <= vx_snoop_delay + 1;
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -29,7 +29,12 @@
|
|||
if (!(cond)) $error(msg); \
|
||||
endgenerate
|
||||
|
||||
`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
|
||||
`define CLOG2(x) $clog2(x);
|
||||
`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > x) ? 1 : 0))
|
||||
`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
|
||||
|
||||
`define MIN(x, y) ((x < y) ? x : y);
|
||||
`define MAX(x, y) ((x > y) ? x : y);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,15 @@ module Vortex #(
|
|||
input wire [31:0] llc_snp_req_addr,
|
||||
output wire llc_snp_req_ready,
|
||||
|
||||
|
||||
// CSR request
|
||||
//input wire csr_read_valid;
|
||||
//input wire csr_write_valid;
|
||||
//input wire [`CSR_WIDTH-1:0 csr_index;
|
||||
//input wire csr_data_in;
|
||||
//output wire [15:0] csr_data_out;
|
||||
|
||||
|
||||
output wire ebreak
|
||||
);
|
||||
`DEBUG_BEGIN
|
||||
|
|
|
|||
|
|
@ -10,16 +10,16 @@ module VX_generic_queue #(
|
|||
input wire push,
|
||||
input wire pop,
|
||||
output wire empty,
|
||||
output wire full,
|
||||
output wire full,
|
||||
`IGNORE_WARNINGS_END
|
||||
input wire [DATAW-1:0] data_in,
|
||||
output wire [DATAW-1:0] data_out
|
||||
);
|
||||
if (SIZE == 0) begin
|
||||
|
||||
assign empty = 1;
|
||||
assign data_out = data_in;
|
||||
assign full = 0;
|
||||
assign empty = 1;
|
||||
assign data_out = data_in;
|
||||
assign full = 0;
|
||||
|
||||
end else begin // (SIZE > 0)
|
||||
|
||||
|
|
@ -56,10 +56,9 @@ module VX_generic_queue #(
|
|||
end
|
||||
end
|
||||
|
||||
assign data_out = head_r;
|
||||
assign empty = (size_r == 0);
|
||||
assign full = (size_r != 0) && !pop;
|
||||
|
||||
assign data_out = head_r;
|
||||
assign empty = (size_r == 0);
|
||||
assign full = (size_r != 0);
|
||||
end else begin // (SIZE > 1)
|
||||
|
||||
reg [DATAW-1:0] curr_r;
|
||||
|
|
@ -82,18 +81,21 @@ module VX_generic_queue #(
|
|||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
size_r <= 0;
|
||||
empty_r <= 1;
|
||||
empty_r <= 1;
|
||||
full_r <= 0;
|
||||
end else begin
|
||||
if (writing && !reading) begin
|
||||
size_r <= size_r + 1;
|
||||
empty_r <= 0;
|
||||
if (size_r == SIZE-1)
|
||||
if (size_r == SIZE-1) begin
|
||||
full_r <= 1;
|
||||
end else if (reading && !writing) begin
|
||||
end
|
||||
end else
|
||||
if (reading && !writing) begin
|
||||
size_r <= size_r - 1;
|
||||
if (size_r == 1)
|
||||
empty_r <= 1;
|
||||
if (size_r == 1) begin
|
||||
empty_r <= 1;
|
||||
end;
|
||||
full_r <= 0;
|
||||
end
|
||||
end
|
||||
|
|
@ -133,5 +135,5 @@ module VX_generic_queue #(
|
|||
assign full = full_r;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
19
hw/rtl/tex_unit/VX_tex_mgr.v
Normal file
19
hw/rtl/tex_unit/VX_tex_mgr.v
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
`include "VX_define.vh"
|
||||
|
||||
module VX_tex_mgr (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
);
|
||||
|
||||
//--
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
50
hw/rtl/tex_unit/VX_tex_unit.v
Normal file
50
hw/rtl/tex_unit/VX_tex_unit.v
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
`include "VX_define.vh"
|
||||
|
||||
module VX_tex_unit #(
|
||||
parameter TADDRW = 32,
|
||||
parameter MADDRW = 32,
|
||||
parameter DATAW = 32,
|
||||
parameter MAXWTW = 8,
|
||||
parameter MAXHTW = 8,
|
||||
parameter MAXFTW = 2,
|
||||
parameter MAXFMW = 1,
|
||||
parameter MAXAMW = 2,
|
||||
parameter TAGW = 16,
|
||||
|
||||
parameter NUMCRQS = 32,
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// Texture Request
|
||||
input wire tex_req_valid,
|
||||
input wire [TADDRW-1:0] tex_req_u,
|
||||
input wire [TADDRW-1:0] tex_req_v,
|
||||
input wire [MADDRW-1:0] tex_req_addr,
|
||||
input wire [MAXWTW-1:0] tex_req_width,
|
||||
input wire [MAXHTW-1:0] tex_req_height,
|
||||
input wire [MAXFTW-1:0] tex_req_format,
|
||||
input wire [MAXFMW-1:0] tex_req_filter,
|
||||
input wire [MAXAMW-1:0] tex_req_clamp,
|
||||
input wire [TAGW-1:0] tex_req_tag,
|
||||
output wire tex_req_ready,
|
||||
|
||||
// Texture Response
|
||||
output wire tex_rsp_valid,
|
||||
output wire [TAGW-1:0] tex_rsp_tag,
|
||||
input wire [DATAW-1:0] tex_rsp_data,
|
||||
input wire tex_rsp_ready,
|
||||
|
||||
// Cache Request
|
||||
output wire [NUMCRQS-1:0] cache_req_valids,
|
||||
output wire [NUMCRQS-1:0][MADDRW-1:0] cache_req_addrs,
|
||||
input wire cache_req_ready,
|
||||
|
||||
// Cache Response
|
||||
input wire cache_rsp_valid,
|
||||
input wire [MADDRW-1:0] cache_rsp_addr,
|
||||
input wire [DATAW-1:0] cache_rsp_data,
|
||||
output wire cache_rsp_ready
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue