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constant integration updates

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This commit is contained in:
Blaise Tine 2020-11-16 02:39:53 -08:00
parent 18ff70bc7f
commit 77bca2deca
11 changed files with 28 additions and 6 deletions
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5
.travis.yml
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@ -31,8 +31,9 @@ script:
- ci/blackbox.sh -run_2c - ci/blackbox.sh -run_2c
- ci/blackbox.sh -run_4c - ci/blackbox.sh -run_4c
- ci/blackbox.sh -run_4c_l2 - ci/blackbox.sh -run_4c_l2
- ci/blackbox.sh -run_8c_2l2 #- travis_wait 30 ci/blackbox.sh -run_8c_2l2
- ci/blackbox.sh -run_16c_4l2_l3 #- travis_wait 30 ci/blackbox.sh -run_4c_2l2_l3
#- travis_wait 30 ci/blackbox.sh -run_8c_4l2_l3
after_success: after_success:
# Gather code coverage # Gather code coverage

3
ci/blackbox.sh
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@ -1,5 +1,8 @@
#!/bin/sh #!/bin/sh
# exit when any command fails
set -e
run_1c() run_1c()
{ {
# test single core # test single core

3
ci/prebuilt.sh
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@ -1,5 +1,8 @@
#!/bin/bash #!/bin/bash
# exit when any command fails
set -e
OS_DIR=ubuntu/bionic OS_DIR=ubuntu/bionic
SRCDIR=/opt SRCDIR=/opt
DESTDIR=. DESTDIR=.

3
ci/test_driver.sh
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@ -1,3 +1,6 @@
#!/bin/bash #!/bin/bash
# exit when any command fails
set -e
make -C driver/tests run make -C driver/tests run

3
ci/test_opencl.sh
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@ -1,3 +1,6 @@
#!/bin/sh #!/bin/sh
# exit when any command fails
set -e
make -C benchmarks/opencl run make -C benchmarks/opencl run

3
ci/test_riscv_isa.sh
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@ -1,3 +1,6 @@
#!/bin/bash #!/bin/bash
# exit when any command fails
set -e
make -C hw/simulate run make -C hw/simulate run

3
ci/test_runtime.sh
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@ -1,3 +1,6 @@
#!/bin/bash #!/bin/bash
# exit when any command fails
set -e
make -C runtime/tests run make -C runtime/tests run

3
ci/toolchain_install.sh
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@ -1,5 +1,8 @@
#!/bin/bash #!/bin/bash
# exit when any command fails
set -e
REPOSITORY=https://github.com/vortexgpgpu/vortex-toolchain-prebuilt/raw/master REPOSITORY=https://github.com/vortexgpgpu/vortex-toolchain-prebuilt/raw/master
riscv() riscv()

2
driver/rtlsim/Makefile
View file

@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CACHE_REQ_INFO DBG_FLAGS += -DDBG_CACHE_REQ_INFO
#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 #CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1
#CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1

4
hw/rtl/cache/VX_bank.v vendored
View file

@ -860,8 +860,8 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK `ifdef DBG_PRINT_CACHE_BANK
always @(posedge clk) begin always @(posedge clk) begin
if (miss_st3 && (incoming_st0_fill_st3 || incoming_st1_fill_st3 || incoming_st2_fill_st3)) begin if (miss_st3 && incoming_fill) begin
$display("%t: incoming fill - addr=%0h, st0=%b, st1=%b, st2=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_st0_fill_st3, incoming_st1_fill_st3, incoming_st2_fill_st3); $display("%t: incoming fill - addr=%0h, st3=%b, dfp=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_fill_st3, incoming_fill_dfp_st3);
assert(!is_msrq_st3); assert(!is_msrq_st3);
end end
if (pipeline_stall) begin if (pipeline_stall) begin