minor update

hw/rtl/tex_unit/VX_tex_sat.sv

@@ -11,9 +11,9 @@ module VX_tex_sat #(
     `STATIC_ASSERT(((OUT_W+1) < IN_W), ("invalid parameter"))
 
     if (MODEL == 1) begin
-        wire [OUT_W-1:0] underflow_mask = {OUT_W{~data_in[IN_W-1]}};        
+        wire [OUT_W-1:0] underflow_mask = {OUT_W{~data_in[IN_W-1]}};
         wire [OUT_W-1:0] overflow_mask = {OUT_W{(| data_in[IN_W-2:OUT_W])}};
-        assign data_out = (data_in[OUT_W-1:0] | overflow_mask) & underflow_mask;        
+        assign data_out = (data_in[OUT_W-1:0] & underflow_mask) | overflow_mask;
     end else begin
         assign data_out = data_in[IN_W-1] ? OUT_W'(0) : ((data_in > {OUT_W{1'b1}}) ? {OUT_W{1'b1}} : OUT_W'(data_in));
     end

hw/syn/altera/.gitignore

@@ -0,0 +1 @@
+ip_cache/*

hw/syn/altera/opae/.gitignore

@@ -1 +1 @@
-build_*/
+build_*/*

third_party/cocogfx

@@ -1 +1 @@
-Subproject commit e4656d62878e517e743e891d22628c9191dca6bc
+Subproject commit 6448e68330ca00a64ab3184e3c5c95b59fe8b62a