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Packing data wires + ALU module

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This commit is contained in:
felsabbagh3 2019-03-26 19:17:11 -04:00
parent 6901208a54
commit 7a528c5ef2
34 changed files with 1274 additions and 1012 deletions
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4
rtl/Makefile
View file

@ -5,10 +5,10 @@ all: RUNFILE
VERILATOR:
verilator -Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp
verilator -Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp
RUNFILE: VERILATOR
(cd obj_dir && make -j -f Vvortex.mk)
(cd obj_dir && make -j -f VVortex.mk)

78
rtl/VX_alu.v Normal file
View file

@ -0,0 +1,78 @@
`include "VX_define.v"
module VX_alu(
input wire[31:0] in_reg_data[1:0],
input wire in_rs2_src,
input wire[31:0] in_itype_immed,
input wire[19:0] in_upper_immed,
input wire[4:0] in_alu_op,
input wire[31:0] in_csr_data, // done
input wire[31:0] in_curr_PC,
output reg[31:0] out_alu_result
);
wire which_in2;
wire[31:0] ALU_in1;
wire[31:0] ALU_in2;
wire[31:0] upper_immed;
assign which_in2 = in_rs2_src == `RS2_IMMED;
assign ALU_in1 = in_reg_data[0];
assign ALU_in2 = which_in2 ? in_itype_immed : in_reg_data[1];
assign upper_immed = {in_upper_immed, {12{1'b0}}};
// always @(*) begin
// $display("EXECUTE CURR_PC: %h",in_curr_PC);
// end
/* verilator lint_off UNUSED */
wire[63:0] mult_unsigned_result = ALU_in1 * ALU_in2;
wire[63:0] mult_signed_result = $signed(ALU_in1) * $signed(ALU_in2);
wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
wire[63:0] mult_signed_un_result = alu_in1_signed * ALU_in2;
/* verilator lint_on UNUSED */
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
`SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
`SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`XOR: out_alu_result = ALU_in1 ^ ALU_in2;
`SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
`SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
`OR: out_alu_result = ALU_in1 | ALU_in2;
`AND: out_alu_result = ALU_in2 & ALU_in1;
`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`LUI_ALU: out_alu_result = upper_immed;
`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
`CSR_ALU_RW: out_alu_result = in_csr_data;
`CSR_ALU_RS: out_alu_result = in_csr_data;
`CSR_ALU_RC: out_alu_result = in_csr_data;
`MUL: out_alu_result = mult_signed_result[31:0];
`MULH: out_alu_result = mult_signed_result[63:32];
`MULHSU: out_alu_result = mult_signed_un_result[63:32];
`MULHU: out_alu_result = mult_unsigned_result[63:32];
`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2));
`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2;
`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2));
`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
default: out_alu_result = 32'h0;
endcase // in_alu_op
end
endmodule // VX_alu

25
rtl/VX_d_e_reg.v
View file

@ -6,9 +6,8 @@ module VX_d_e_reg (
input wire clk,
input wire[4:0] in_rd,
input wire[4:0] in_rs1,
input wire[31:0] in_rd1,
input wire[4:0] in_rs2,
input wire[31:0] in_rd2,
input wire[31:0] in_reg_data[1:0],
input wire[4:0] in_alu_op,
input wire[1:0] in_wb,
input wire in_rs2_src, // NEW
@ -34,9 +33,8 @@ module VX_d_e_reg (
output wire[31:0] out_csr_mask, // done
output wire[4:0] out_rd,
output wire[4:0] out_rs1,
output wire[31:0] out_rd1,
output wire[4:0] out_rs2,
output wire[31:0] out_rd2,
output wire[31:0] out_reg_data[1:0],
output wire[4:0] out_alu_op,
output wire[1:0] out_wb,
output wire out_rs2_src, // NEW
@ -55,9 +53,8 @@ module VX_d_e_reg (
reg[4:0] rd;
reg[4:0] rs1;
reg[31:0] rd1;
reg[4:0] rs2;
reg[31:0] rd2;
reg[31:0] reg_data[1:0];
reg[4:0] alu_op;
reg[1:0] wb;
reg[31:0] PC_next_out;
@ -79,9 +76,9 @@ module VX_d_e_reg (
initial begin
rd = 0;
rs1 = 0;
rd1 = 0;
reg_data[0] = 0;
reg_data[1] = 0;
rs2 = 0;
rd2 = 0;
alu_op = 0;
wb = `NO_WB;
PC_next_out = 0;
@ -106,9 +103,8 @@ module VX_d_e_reg (
assign out_rd = rd;
assign out_rs1 = rs1;
assign out_rd1 = rd1;
assign out_rs2 = rs2;
assign out_rd2 = rd2;
assign out_reg_data = reg_data;
assign out_alu_op = alu_op;
assign out_wb = wb;
assign out_PC_next = PC_next_out;
@ -127,13 +123,18 @@ module VX_d_e_reg (
assign out_valid = valid;
wire[31:0] reg_data_z[1:0];
assign reg_data_z[0] = 32'0;
assign reg_data_z[1] = 32'0;
always @(posedge clk) begin
if (in_freeze == 1'h0) begin
rd <= stalling ? 5'h0 : in_rd;
rs1 <= stalling ? 5'h0 : in_rs1;
rd1 <= stalling ? 32'h0 : in_rd1;
rs2 <= stalling ? 5'h0 : in_rs2;
rd2 <= stalling ? 32'h0 : in_rd2;
reg_data <= stalling ? reg_data_z : in_reg_data;
alu_op <= stalling ? `NO_ALU : in_alu_op;
wb <= stalling ? `NO_WB : in_wb;
PC_next_out <= stalling ? 32'h0 : in_PC_next;

36
rtl/VX_decode.v
View file

@ -18,22 +18,21 @@ module VX_decode(
input wire in_src2_fwd,
input wire[31:0] in_src2_fwd_data,
output wire[11:0] out_csr_address, // done
output wire out_is_csr, // done
output wire[31:0] out_csr_mask, // done
output wire[11:0] out_csr_address,
output wire out_is_csr,
output wire[31:0] out_csr_mask,
// Outputs
output wire[4:0] out_rd,
output wire[4:0] out_rs1,
output wire[31:0] out_rd1,
output wire[4:0] out_rs2,
output wire[31:0] out_rd2,
output wire[31:0] out_reg_data[1:0],
output wire[1:0] out_wb,
output wire[4:0] out_alu_op,
output wire out_rs2_src, // NEW
output reg[31:0] out_itype_immed, // new
output wire[2:0] out_mem_read, // NEW
output wire[2:0] out_mem_write, // NEW
output wire out_rs2_src,
output reg[31:0] out_itype_immed,
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output reg[2:0] out_branch_type,
output reg out_branch_stall,
output reg out_jal,
@ -98,6 +97,9 @@ module VX_decode(
reg[4:0] alu_op;
reg[4:0] mul_alu;
wire[31:0] internal_rd1;
wire[31:0] internal_rd2;
// always @(posedge clk) begin
// $display("Decode: curr_pc: %h", in_curr_PC);
// end
@ -148,20 +150,22 @@ module VX_decode(
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
assign out_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register));
assign internal_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register));
assign internal_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register;
assign out_reg_data[0] = internal_rd1;
assign out_reg_data[1] = internal_rd2;
// always @(negedge clk) begin
// if (in_curr_PC == 32'h800001f0) begin
// $display("IN DECODE: Going to write to: %d with val: %h [%h, %h, %h]", out_rd, out_rd1, in_curr_PC, in_src1_fwd_data, rd1_register);
// $display("IN DECODE: Going to write to: %d with val: %h [%h, %h, %h]", out_rd, internal_rd1, in_curr_PC, in_src1_fwd_data, rd1_register);
// end
// end
assign out_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register;
assign out_is_csr = is_csr;
assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_rd1;
assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : internal_rd1;
assign out_wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL :

19
rtl/VX_e_m_reg.v
View file

@ -9,9 +9,8 @@ module VX_e_m_reg (
input wire[4:0] in_rd,
input wire[1:0] in_wb,
input wire[4:0] in_rs1,
input wire[31:0] in_rd1,
input wire[4:0] in_rs2,
input wire[31:0] in_rd2,
input wire[31:0] in_reg_data[1:0],
input wire[2:0] in_mem_read, // NEW
input wire[2:0] in_mem_write, // NEW
input wire[31:0] in_PC_next,
@ -33,9 +32,8 @@ module VX_e_m_reg (
output wire[4:0] out_rd,
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[31:0] out_rd1,
output wire[31:0] out_rd2,
output wire[4:0] out_rs2,
output wire[31:0] out_reg_data[1:0],
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output wire[31:0] out_curr_PC,
@ -51,9 +49,8 @@ module VX_e_m_reg (
reg[31:0] alu_result;
reg[4:0] rd;
reg[4:0] rs1;
reg[31:0] rd1;
reg[4:0] rs2;
reg[31:0] rd2;
reg[31:0] reg_data[1:0];
reg[1:0] wb;
reg[31:0] PC_next;
reg[2:0] mem_read;
@ -73,9 +70,9 @@ module VX_e_m_reg (
alu_result = 0;
rd = 0;
rs1 = 0;
rd1 = 0;
rs2 = 0;
rd2 = 0;
reg_data[0] = 0;
reg_data[1] = 0;
wb = 0;
PC_next = 0;
mem_read = `NO_MEM_READ;
@ -101,8 +98,7 @@ module VX_e_m_reg (
assign out_PC_next = PC_next;
assign out_mem_read = mem_read;
assign out_mem_write = mem_write;
assign out_rd1 = rd1;
assign out_rd2 = rd2;
assign out_reg_data = reg_data;
assign out_csr_address = csr_address;
assign out_is_csr = is_csr;
assign out_csr_result = csr_result;
@ -124,8 +120,7 @@ module VX_e_m_reg (
PC_next <= in_PC_next;
mem_read <= in_mem_read;
mem_write <= in_mem_write;
rd1 <= in_rd1;
rd2 <= in_rd2;
reg_data <= in_reg_data;
csr_address <= in_csr_address;
is_csr <= in_is_csr;
csr_result <= in_csr_result;

76
rtl/VX_execute.v
View file

@ -4,9 +4,8 @@
module VX_execute (
input wire[4:0] in_rd,
input wire[4:0] in_rs1,
input wire[31:0] in_rd1,
input wire[4:0] in_rs2,
input wire[31:0] in_rd2,
input wire[31:0] in_reg_data[1:0],
input wire[4:0] in_alu_op,
input wire[1:0] in_wb,
input wire in_rs2_src, // NEW
@ -32,9 +31,8 @@ module VX_execute (
output wire[4:0] out_rd,
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[31:0] out_rd1,
output wire[4:0] out_rs2,
output wire[31:0] out_rd2,
output wire[31:0] out_reg_data[1:0],
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output wire out_jal,
@ -45,38 +43,23 @@ module VX_execute (
output wire out_valid
);
wire which_in2;
wire[31:0] ALU_in1;
wire[31:0] ALU_in2;
wire[31:0] upper_immed;
assign which_in2 = in_rs2_src == `RS2_IMMED;
assign ALU_in1 = in_rd1;
assign ALU_in2 = which_in2 ? in_itype_immed : in_rd2;
VX_alu vx_alu(
.in_reg_data (in_reg_data),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result)
);
assign upper_immed = {in_upper_immed, {12{1'b0}}};
assign out_jal_dest = $signed(in_rd1) + $signed(in_jal_offset);
assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset);
assign out_jal = in_jal;
// always @(*) begin
// $display("EXECUTE CURR_PC: %h",in_curr_PC);
// end
/* verilator lint_off UNUSED */
wire[63:0] mult_unsigned_result = ALU_in1 * ALU_in2;
wire[63:0] mult_signed_result = $signed(ALU_in1) * $signed(ALU_in2);
wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
wire[63:0] mult_signed_un_result = alu_in1_signed * ALU_in2;
/* verilator lint_on UNUSED */
always @(*) begin
case(in_alu_op)
@ -88,35 +71,7 @@ module VX_execute (
end
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
`SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
`SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`XOR: out_alu_result = ALU_in1 ^ ALU_in2;
`SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
`SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
`OR: out_alu_result = ALU_in1 | ALU_in2;
`AND: out_alu_result = ALU_in2 & ALU_in1;
`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`LUI_ALU: out_alu_result = upper_immed;
`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
`CSR_ALU_RW: out_alu_result = in_csr_data;
`CSR_ALU_RS: out_alu_result = in_csr_data;
`CSR_ALU_RC: out_alu_result = in_csr_data;
`MUL: out_alu_result = mult_signed_result[31:0];
`MULH: out_alu_result = mult_signed_result[63:32];
`MULHSU: out_alu_result = mult_signed_un_result[63:32];
`MULHU: out_alu_result = mult_unsigned_result[63:32];
`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2));
`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2;
`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2));
`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
default: out_alu_result = 32'h0;
endcase // in_alu_op
end
assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL;
@ -128,8 +83,7 @@ module VX_execute (
assign out_mem_read = in_mem_read;
assign out_mem_write = in_mem_write;
assign out_rs1 = in_rs1;
assign out_rd1 = in_rd1;
assign out_rd2 = in_rd2;
assign out_reg_data = in_reg_data;
assign out_rs2 = in_rs2;
assign out_PC_next = in_PC_next;
assign out_is_csr = in_is_csr;

38
rtl/vortex.v → rtl/Vortex.v
View file

@ -1,6 +1,4 @@
module Vortex(
input wire clk,
input wire reset,
@ -34,9 +32,8 @@ wire decode_is_csr;
wire[31:0] decode_csr_mask;
wire[4:0] decode_rd;
wire[4:0] decode_rs1;
wire[31:0] decode_rd1;
wire[4:0] decode_rs2;
wire[31:0] decode_rd2;
wire[31:0] decode_reg_data[1:0];
wire[1:0] decode_wb;
wire[4:0] decode_alu_op;
wire decode_rs2_src;
@ -56,9 +53,8 @@ wire d_e_is_csr;
wire[31:0] d_e_csr_mask;
wire[4:0] d_e_rd;
wire[4:0] d_e_rs1;
wire[31:0] d_e_rd1;
wire[4:0] d_e_rs2;
wire[31:0] d_e_rd2;
wire[31:0] d_e_reg_data[1:0];
wire[4:0] d_e_alu_op;
wire[1:0] d_e_wb;
wire d_e_rs2_src;
@ -83,9 +79,8 @@ reg[31:0] execute_alu_result;
wire[4:0] execute_rd;
wire[1:0] execute_wb;
wire[4:0] execute_rs1;
wire[31:0] execute_rd1;
wire[4:0] execute_rs2;
wire[31:0] execute_rd2;
wire[31:0] execute_reg_data[1:0];
wire[2:0] execute_mem_read;
wire[2:0] execute_mem_write;
wire execute_jal;
@ -106,9 +101,8 @@ wire[4:0] e_m_rd;
wire[1:0] e_m_wb;
wire[4:0] e_m_rs1;
/* verilator lint_off UNUSED */
wire[31:0] e_m_rd1;
wire[31:0] e_m_reg_data[1:0];
/* verilator lint_on UNUSED */
wire[31:0] e_m_rd2;
wire[4:0] e_m_rs2;
wire[2:0] e_m_mem_read;
wire[2:0] e_m_mem_write;
@ -174,7 +168,6 @@ assign debug = 1'b0;
assign interrupt = 1'b0;
assign total_freeze = fetch_delay || memory_delay;
VX_fetch vx_fetch(
.clk(clk),
@ -232,9 +225,8 @@ VX_decode vx_decode(
.out_rd(decode_rd),
.out_rs1(decode_rs1),
.out_rd1(decode_rd1),
.out_rs2(decode_rs2),
.out_rd2(decode_rd2),
.out_reg_data(decode_reg_data),
.out_wb(decode_wb),
.out_alu_op(decode_alu_op),
.out_rs2_src(decode_rs2_src),
@ -255,9 +247,8 @@ VX_d_e_reg vx_d_e_reg(
.clk(clk),
.in_rd(decode_rd),
.in_rs1(decode_rs1),
.in_rd1(decode_rd1),
.in_rs2(decode_rs2),
.in_rd2(decode_rd2),
.in_reg_data(decode_reg_data),
.in_alu_op(decode_alu_op),
.in_wb(decode_wb),
.in_rs2_src(decode_rs2_src),
@ -283,9 +274,8 @@ VX_d_e_reg vx_d_e_reg(
.out_csr_mask(d_e_csr_mask),
.out_rd(d_e_rd),
.out_rs1(d_e_rs1),
.out_rd1(d_e_rd1),
.out_rs2(d_e_rs2),
.out_rd2(d_e_rd2),
.out_reg_data(d_e_reg_data),
.out_alu_op(d_e_alu_op),
.out_wb(d_e_wb),
.out_rs2_src(d_e_rs2_src),
@ -304,9 +294,8 @@ VX_d_e_reg vx_d_e_reg(
VX_execute vx_execute(
.in_rd(d_e_rd),
.in_rs1(d_e_rs1),
.in_rd1(d_e_rd1),
.in_rs2(d_e_rs2),
.in_rd2(d_e_rd2),
.in_reg_data(d_e_reg_data),
.in_alu_op(d_e_alu_op),
.in_wb(d_e_wb),
.in_rs2_src(d_e_rs2_src),
@ -332,9 +321,8 @@ VX_execute vx_execute(
.out_rd(execute_rd),
.out_wb(execute_wb),
.out_rs1(execute_rs1),
.out_rd1(execute_rd1),
.out_rs2(execute_rs2),
.out_rd2(execute_rd2),
.out_reg_data(execute_reg_data),
.out_mem_read(execute_mem_read),
.out_mem_write(execute_mem_write),
.out_jal(execute_jal),
@ -352,9 +340,8 @@ VX_e_m_reg vx_e_m_reg(
.in_rd(execute_rd),
.in_wb(execute_wb),
.in_rs1(execute_rs1),
.in_rd1(execute_rd1),
.in_rs2(execute_rs2),
.in_rd2(execute_rd2),
.in_reg_data(execute_reg_data),
.in_mem_read(execute_mem_read),
.in_mem_write(execute_mem_write),
.in_PC_next(execute_PC_next),
@ -376,9 +363,8 @@ VX_e_m_reg vx_e_m_reg(
.out_rd(e_m_rd),
.out_wb(e_m_wb),
.out_rs1(e_m_rs1),
.out_rd1(e_m_rd1),
.out_rd2(e_m_rd2),
.out_rs2(e_m_rs2),
.out_reg_data(e_m_reg_data),
.out_mem_read(e_m_mem_read),
.out_mem_write(e_m_mem_write),
.out_curr_PC(e_m_curr_PC),
@ -398,7 +384,7 @@ VX_memory vx_memory(
.in_wb(e_m_wb),
.in_rs1(e_m_rs1),
.in_rs2(e_m_rs2),
.in_rd2(e_m_rd2),
.in_rd2(e_m_reg_data[1]),
.in_PC_next(e_m_PC_next),
.in_curr_PC(e_m_curr_PC),
.in_branch_offset(e_m_branch_offset),

BIN
rtl/obj_dir/VVortex Executable file
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1792
rtl/obj_dir/Vvortex.cpp → rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load diff

35
rtl/obj_dir/Vvortex.h → rtl/obj_dir/VVortex.h
View file

@ -83,7 +83,6 @@ VL_MODULE(VVortex) {
VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG(Vortex__DOT__decode_rd1,31,0);
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
VL_SIG(Vortex__DOT__execute_alu_result,31,0);
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
@ -98,19 +97,17 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd1,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd2,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_decode__DOT__internal_rd1,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__rd2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
@ -119,10 +116,17 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG(Vortex__DOT__decode_reg_data[2],31,0);
VL_SIG(Vortex__DOT__d_e_reg_data[2],31,0);
VL_SIG(Vortex__DOT__execute_reg_data[2],31,0);
VL_SIG(Vortex__DOT__e_m_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[2],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
@ -132,6 +136,14 @@ VL_MODULE(VVortex) {
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[2],31,0);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES
@ -166,7 +178,7 @@ VL_MODULE(VVortex) {
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
@ -178,12 +190,13 @@ VL_MODULE(VVortex) {
public:
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
static void _initial__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _initial__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__7(VVortex__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

2
rtl/obj_dir/Vvortex.mk → rtl/obj_dir/VVortex.mk
View file

@ -10,7 +10,7 @@ default: VVortex
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)

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0
rtl/obj_dir/Vvortex__ALLcls.cpp → rtl/obj_dir/VVortex__ALLcls.cpp
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3
rtl/obj_dir/VVortex__ALLcls.d Normal file
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@ -0,0 +1,3 @@
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h

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0
rtl/obj_dir/Vvortex__ALLsup.cpp → rtl/obj_dir/VVortex__ALLsup.cpp
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3
rtl/obj_dir/VVortex__ALLsup.d Normal file
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@ -0,0 +1,3 @@
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex.h

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rtl/obj_dir/VVortex__ALLsup.o
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0
rtl/obj_dir/Vvortex__Syms.cpp → rtl/obj_dir/VVortex__Syms.cpp
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0
rtl/obj_dir/Vvortex__Syms.h → rtl/obj_dir/VVortex__Syms.h
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1
rtl/obj_dir/VVortex__ver.d Normal file
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@ -0,0 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v

26
rtl/obj_dir/VVortex__verFiles.dat Normal file
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@ -0,0 +1,26 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 5163137 401094 1553636247 412576209 1553636247 412576209 "/usr/local/bin/verilator_bin"
S 2782 5518365 1553641993 611294425 1553641993 611294425 "VX_alu.v"
S 1495 5518326 1553635490 361093288 1553635490 361093288 "VX_csr_handler.v"
S 4603 5518327 1553640386 543770135 1553640386 543770135 "VX_d_e_reg.v"
S 9287 5518328 1553639887 889455624 1553639887 889455624 "VX_decode.v"
S 1503 5518330 1553635490 361093288 1553635490 361093288 "VX_define.v"
S 3547 5518331 1553641200 263546964 1553641200 263546964 "VX_e_m_reg.v"
S 2645 5518332 1553641998 83315687 1553641998 83315687 "VX_execute.v"
S 1120 5518333 1553635490 361093288 1553635490 361093288 "VX_f_d_reg.v"
S 3537 5518334 1553635490 361093288 1553635490 361093288 "VX_fetch.v"
S 5020 5518335 1553635490 361093288 1553635490 361093288 "VX_forwarding.v"
S 1578 5518336 1553635490 361093288 1553635490 361093288 "VX_m_w_reg.v"
S 2606 5518337 1553635490 361093288 1553635490 361093288 "VX_memory.v"
S 958 5518338 1553635490 361093288 1553635490 361093288 "VX_register_file.v"
S 806 5518339 1553635490 361093288 1553635490 361093288 "VX_writeback.v"
S 12732 5518364 1553641238 871726160 1553641238 871726160 "Vortex.v"
T 100811 5518343 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex.cpp"
T 8941 5518342 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex.h"
T 1777 5518345 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex.mk"
T 530 5518341 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex__Syms.cpp"
T 711 5518340 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex__Syms.h"
T 418 5518346 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex__ver.d"
T 0 0 1553642016 163401646 1553642016 163401646 "obj_dir/VVortex__verFiles.dat"
T 1159 5518344 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex_classes.mk"

0
rtl/obj_dir/Vvortex_classes.mk → rtl/obj_dir/VVortex_classes.mk
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rtl/obj_dir/Vvortex
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rtl/obj_dir/Vvortex__ALL.a
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4
rtl/obj_dir/Vvortex__ALLcls.d
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@ -1,4 +0,0 @@
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
VVortex__Syms.h

4
rtl/obj_dir/Vvortex__ALLsup.d
View file

@ -1,4 +0,0 @@
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
VVortex.h

1
rtl/obj_dir/Vvortex__ver.d
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@ -1 +0,0 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v

25
rtl/obj_dir/Vvortex__verFiles.dat
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@ -1,25 +0,0 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4626 12889079539 1553237386 0 1553237386 0 "VX_d_e_reg.v"
S 9200 12889063385 1553237914 0 1553237914 0 "VX_decode.v"
S 1503 12889079483 1553237629 0 1553237629 0 "VX_define.v"
S 3644 12889083963 1553196174 0 1553196174 0 "VX_e_m_reg.v"
S 4844 12889081819 1553242107 0 1553242107 0 "VX_execute.v"
S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v"
S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v"
S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v"
S 1578 12889085814 1553211072 0 1553211072 0 "VX_m_w_reg.v"
S 2606 12889084513 1553234474 0 1553234474 0 "VX_memory.v"
S 958 12889070228 1553234503 0 1553234503 0 "VX_register_file.v"
S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v"
S 12863 12889050092 1553237368 0 1553237368 0 "Vortex.v"
T 88166 12889102709 1553242391 0 1553242391 0 "obj_dir/VVortex.cpp"
T 8044 12889102708 1553242391 0 1553242391 0 "obj_dir/VVortex.h"
T 1800 12889102711 1553242391 0 1553242391 0 "obj_dir/VVortex.mk"
T 530 12889102707 1553242391 0 1553242391 0 "obj_dir/VVortex__Syms.cpp"
T 711 12889102706 1553242391 0 1553242391 0 "obj_dir/VVortex__Syms.h"
T 455 12889102712 1553242391 0 1553242391 0 "obj_dir/VVortex__ver.d"
T 0 0 1553242391 0 1553242391 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889102710 1553242391 0 1553242391 0 "obj_dir/VVortex_classes.mk"

5
rtl/obj_dir/test_bench.d
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@ -1,4 +1,3 @@
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
VVortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h
VVortex.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h

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17
rtl/obj_dir/verilated.d
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@ -1,9 +1,8 @@
verilated.o: \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_config.h

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92
rtl/results.txt
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@ -5,7 +5,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01843
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-addi.hex ****************
@ -14,7 +14,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03526
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-and.hex ****************
@ -23,7 +23,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01849
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-andi.hex ****************
@ -32,7 +32,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04472
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-auipc.hex ****************
@ -41,7 +41,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.16923
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-beq.hex ****************
@ -50,7 +50,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bge.hex ****************
@ -59,7 +59,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02355
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bgeu.hex ****************
@ -68,7 +68,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02236
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-blt.hex ****************
@ -77,7 +77,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bltu.hex ****************
@ -86,7 +86,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02412
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bne.hex ****************
@ -95,7 +95,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-jal.hex ****************
@ -104,7 +104,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.18033
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-jalr.hex ****************
@ -113,7 +113,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.07971
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lb.hex ****************
@ -122,7 +122,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03323
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lbu.hex ****************
@ -131,7 +131,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03323
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lh.hex ****************
@ -140,7 +140,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03245
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lhu.hex ****************
@ -149,7 +149,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03207
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lui.hex ****************
@ -158,7 +158,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.15068
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lw.hex ****************
@ -167,7 +167,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03179
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-or.hex ****************
@ -176,7 +176,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01839
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-ori.hex ****************
@ -185,7 +185,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04348
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sb.hex ****************
@ -194,7 +194,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01926
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sh.hex ****************
@ -203,7 +203,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01824
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-simple.hex ****************
@ -212,7 +212,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.2973
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sll.hex ****************
@ -221,7 +221,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01738
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slli.hex ****************
@ -230,7 +230,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03537
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slt.hex ****************
@ -239,7 +239,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01861
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slti.hex ****************
@ -248,7 +248,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03583
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sltiu.hex ****************
@ -257,7 +257,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03583
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sltu.hex ****************
@ -266,7 +266,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01861
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sra.hex ****************
@ -275,7 +275,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01682
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srai.hex ****************
@ -284,7 +284,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03374
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srl.hex ****************
@ -293,7 +293,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01698
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srli.hex ****************
@ -302,7 +302,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03438
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex ****************
@ -311,7 +311,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01874
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sw.hex ****************
@ -320,7 +320,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01797
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-xor.hex ****************
@ -329,7 +329,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01843
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-xori.hex ****************
@ -338,7 +338,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04314
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-div.hex ****************
@ -347,7 +347,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-divu.hex ****************
@ -356,7 +356,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09735
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mul.hex ****************
@ -365,7 +365,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01868
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulh.hex ****************
@ -374,7 +374,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulhsu.hex ****************
@ -383,7 +383,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulhu.hex ****************
@ -392,7 +392,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-rem.hex ****************
@ -401,7 +401,7 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-remu.hex ****************
@ -410,5 +410,5 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# time to simulate: 6.12641e-322 milliseconds
# GRADE: PASSING