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Chnaged opcodes of vote and SHFL

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This commit is contained in:
Rishabh Ravi 2024-11-01 09:38:46 -04:00
parent d13cdc3fc3
commit 7c37dc0d01
5 changed files with 36 additions and 39 deletions
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13
kernel/include/vx_intrinsics.h
View file

@ -36,9 +36,6 @@ extern "C" {
#define RISCV_CUSTOM1 0x2B
#define RISCV_CUSTOM2 0x5B
#define RISCV_CUSTOM3 0x7B
#define RISCV_VOTE 0x5A
#define RISCV_SHFL 0x5C
#define RISCV_TILE 0x5D
#define csr_read(csr) ({ \
size_t __r; \
@ -252,18 +249,18 @@ void vx_store(int val, int reg){
}
}
void vx_vote() {
inline void vx_vote() {
__asm__ volatile (
"addi a2, x0, 9\n\t" // Load immediate value 6 into a2(x12) register (membermask)
".insn i %0, 2, 0, x14, x13, 12" :: "i"(RISCV_VOTE));
//".insn i opcode6, func3, func7, rd, rs1, simm12"
".insn i %0, 2, x14, x13, 12" :: "i"(RISCV_CUSTOM1));
//".insn i opcode7, func3, func7, rd, rs1, simm12"
}
void vx_shfl() {
inline void vx_shfl() {
__asm__ volatile (
"addi a1, x0, 15\n\t" // Load immediate value 15 into a1(x11) register (membermask)
"addi a2, x0, 15\n\t" // Load immediate value 15 into a2(x12) register (c)
".insn i %0, 3, x14, x13, 1067" :: "i"(RISCV_SHFL)); //(c(01)+b(00001)+membermask(address(01011)))
".insn i %0, 3, x14, x13, 1067" :: "i"(RISCV_CUSTOM2)); //(c(01)+b(00001)+membermask(address(01011)))
//".insn i opcode6, func3, rd, rs1, simm12"
}

2
sim/simx/decode.cpp
View file

@ -48,7 +48,7 @@ static const std::unordered_map<Opcode, InstType> sc_instTable = {
{Opcode::FMNMADD, InstType::R4},
{Opcode::FMNMSUB, InstType::R4},
{Opcode::EXT1, InstType::R},
{Opcode::EXT2, InstType::R4},
// {Opcode::EXT2, InstType::R4},
{Opcode::R_W, InstType::R},
{Opcode::I_W, InstType::I},
{Opcode::VOTE, InstType::I},

50
sim/simx/execute.cpp
View file

@ -1414,31 +1414,31 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
std::abort();
}
} break;
case Opcode::EXT2: {
switch (func3) {
case 1:
switch (func2) {
case 0: { // CMOV
trace->fu_type = FUType::SFU;
trace->sfu_type = SfuType::CMOV;
trace->used_iregs.set(rsrc0);
trace->used_iregs.set(rsrc1);
trace->used_iregs.set(rsrc2);
for (uint32_t t = thread_start; t < num_threads; ++t) {
if (!warp.tmask.test(t))
continue;
rddata[t].i = rsdata[t][0].i ? rsdata[t][1].i : rsdata[t][2].i;
}
rd_write = true;
} break;
default:
std::abort();
}
break;
default:
std::abort();
}
} break;
// case Opcode::EXT2: {
// switch (func3) {
// case 1:
// switch (func2) {
// case 0: { // CMOV
// trace->fu_type = FUType::SFU;
// trace->sfu_type = SfuType::CMOV;
// trace->used_iregs.set(rsrc0);
// trace->used_iregs.set(rsrc1);
// trace->used_iregs.set(rsrc2);
// for (uint32_t t = thread_start; t < num_threads; ++t) {
// if (!warp.tmask.test(t))
// continue;
// rddata[t].i = rsdata[t][0].i ? rsdata[t][1].i : rsdata[t][2].i;
// }
// rd_write = true;
// } break;
// default:
// std::abort();
// }
// break;
// default:
// std::abort();
// }
// } break;
case Opcode::VOTE: {
bool check;
bool is_neg = (func3 >= 4);

8
sim/simx/instr.h
View file

@ -44,12 +44,12 @@ enum class Opcode {
I_W = 0x1b,
// Custom Extensions
EXT1 = 0x0b,
EXT2 = 0x2b,
EXT3 = 0x5b,
// EXT2 = 0x2b,
// EXT3 = 0x5b,
EXT4 = 0x7b,
// CUDA Vote Extension
VOTE = 0x5a,
SHFL = 0x5c
VOTE = 0x2b,
SHFL = 0x5b
};
enum class InstType {

2
tests/regression/shfl/kernel.cpp
View file

@ -26,7 +26,7 @@ void kernel_body(kernel_arg_t* __UNIFORM__ arg) {
vx_store(val,3);
vx_tmc(15);
vx_shfl();
}
}
int main() {
kernel_arg_t* arg = (kernel_arg_t*)csr_read(VX_CSR_MSCRATCH);