mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
This commit is contained in:
Blaise Tine
parent
50cfc48c0a
commit
7c4823e65c
13 changed files with 130 additions and 140 deletions
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@ -3,4 +3,4 @@
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# exit when any command fails
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set -e
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make -C hw/simulate run
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make -C benchmarks/riscv_tests/isa run
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@ -147,8 +147,8 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) {
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for (unsigned core_id = 0; core_id < num_cores; ++core_id) {
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uint64_t instrs_per_core, cycles_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MINSTRET, CSR_MINSTRET_H, &instrs_per_core);
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ret |= vx_csr_get_l(device, core_id, CSR_MCYCLE, CSR_MCYCLE_H, &cycles_per_core);
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ret |= vx_csr_get_l(device, core_id, CSR_INSTRET, CSR_INSTRET_H, &instrs_per_core);
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ret |= vx_csr_get_l(device, core_id, CSR_CYCLE, CSR_CYCLE_H, &cycles_per_core);
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float IPC = (float)(double(instrs_per_core) / double(cycles_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC);
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instrs += instrs_per_core;
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@ -158,10 +158,10 @@
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`define CSR_MEPC 12'h341
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// Machine Counter/Timers
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`define CSR_MCYCLE 12'hB00
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`define CSR_MCYCLE_H 12'hB80
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`define CSR_MINSTRET 12'hB02
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`define CSR_MINSTRET_H 12'hB82
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`define CSR_CYCLE 12'hC00
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`define CSR_CYCLE_H 12'hC80
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`define CSR_INSTRET 12'hC02
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`define CSR_INSTRET_H 12'hC82
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// Machine Performance-monitoring counters
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// PERF: pipeline
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@ -196,10 +196,10 @@ module VX_csr_data #(
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`CSR_PMPCFG0 : read_data_r = 32'(csr_pmpcfg[0]);
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`CSR_PMPADDR0 : read_data_r = 32'(csr_pmpaddr[0]);
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`CSR_MCYCLE : read_data_r = csr_cycle[31:0];
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`CSR_MCYCLE_H : read_data_r = csr_cycle[63:32];
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`CSR_MINSTRET : read_data_r = csr_instret[31:0];
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`CSR_MINSTRET_H: read_data_r = csr_instret[63:32];
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`CSR_CYCLE : read_data_r = csr_cycle[31:0];
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`CSR_CYCLE_H : read_data_r = csr_cycle[63:32];
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`CSR_INSTRET : read_data_r = csr_instret[31:0];
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`CSR_INSTRET_H : read_data_r = csr_instret[63:32];
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`CSR_MVENDORID : read_data_r = `VENDOR_ID;
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`CSR_MARCHID : read_data_r = `ARCHITECTURE_ID;
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@ -269,9 +269,7 @@ module VX_decode #(
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wire is_lsu = (is_ltype || is_stype || is_fl || is_fs);
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always @(*) begin
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lsu_op = {is_stype, func3};
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if (is_fl) lsu_op = `LSU_LW;
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if (is_fs) lsu_op = `LSU_SW;
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lsu_op = (is_fl || is_fs) ? `LSU_SW : func3;
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end
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// GPU
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@ -307,7 +305,8 @@ module VX_decode #(
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///////////////////////////////////////////////////////////////////////////
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assign decode_if.valid = ifetch_rsp_if.valid;
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assign decode_if.valid = ifetch_rsp_if.valid
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&& (decode_if.ex_type != `EX_NOP); // skip noop
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assign decode_if.wid = ifetch_rsp_if.wid;
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assign decode_if.tmask = ifetch_rsp_if.tmask;
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@ -54,14 +54,6 @@
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///////////////////////////////////////////////////////////////////////////////
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`define BYTEEN_SB 3'h0
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`define BYTEEN_SH 3'h1
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`define BYTEEN_SW 3'h2
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`define BYTEEN_UB 3'h4
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`define BYTEEN_UH 3'h5
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`define BYTEEN_BITS 3
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`define BYTEEN_TYPE(x) x[1:0]
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`define FRM_RNE 3'b000 // round to nearest even
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`define FRM_RTZ 3'b001 // round to zero
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`define FRM_RDN 3'b010 // round to -inf
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@ -130,19 +122,14 @@
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`define ALU_BR_OP(x) x[`ALU_BR_BITS-1:0]
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`define IS_BR_MOD(x) x[0]
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`define LSU_LB {1'b0, `BYTEEN_SB}
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`define LSU_LH {1'b0, `BYTEEN_SH}
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`define LSU_LW {1'b0, `BYTEEN_SW}
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`define LSU_LBU {1'b0, `BYTEEN_UB}
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`define LSU_LHU {1'b0, `BYTEEN_UH}
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`define LSU_SB {1'b1, `BYTEEN_SB}
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`define LSU_SH {1'b1, `BYTEEN_SH}
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`define LSU_SW {1'b1, `BYTEEN_SW}
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`define LSU_SBU {1'b1, `BYTEEN_UB}
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`define LSU_SHU {1'b1, `BYTEEN_UH}
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`define LSU_BITS 4
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`define LSU_RW(x) x[3]
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`define LSU_BE(x) x[2:0]
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`define LSU_SB 3'h0
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`define LSU_SH 3'h1
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`define LSU_SW 3'h2
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`define LSU_UB 3'h4
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`define LSU_UH 3'h5
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`define LSU_BITS 3
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`define LSU_WSIZE(x) x[1:0]
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`define LSU_OP(x) x[`LSU_BITS-1:0]
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`define CSR_RW 2'h0
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`define CSR_RS 2'h1
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@ -14,6 +14,9 @@ module VX_gpr_stage #(
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VX_gpr_rsp_if gpr_rsp_if
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);
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`UNUSED_VAR (reset)
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// ensure r0 never gets written, which can happen before the reset
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wire write_enable = writeback_if.valid && (writeback_if.rd != 0);
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`ifdef EXT_F_ENABLE
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localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS;
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@ -31,7 +34,7 @@ module VX_gpr_stage #(
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.DEPTH (RAM_DEPTH)
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) gpr_ram_f (
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.clk (clk),
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.wren (writeback_if.valid && writeback_if.tmask[i]),
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.wren (write_enable && writeback_if.tmask[i]),
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.waddr (waddr),
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.wdata (writeback_if.data[i]),
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.raddr1 (raddr1),
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@ -62,7 +65,7 @@ module VX_gpr_stage #(
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.DEPTH (RAM_DEPTH)
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) gpr_ram_i (
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.clk (clk),
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.wren (writeback_if.valid && writeback_if.tmask[i]),
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.wren (write_enable && writeback_if.tmask[i]),
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.waddr (waddr),
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.wdata (writeback_if.data[i]),
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.raddr1 (raddr1),
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@ -54,14 +54,14 @@ module VX_instr_demux (
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wire lsu_req_ready;
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
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) lsu_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (lsu_req_valid),
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.ready_in (lsu_req_ready),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_OP(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
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.valid_out (lsu_req_if.valid),
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.ready_out (lsu_req_if.ready)
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);
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@ -205,7 +205,7 @@ module VX_issue #(
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, alu_req_if.wid, alu_req_if.PC, alu_req_if.tmask, alu_req_if.rd, alu_req_if.rs1_data, alu_req_if.rs2_data);
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end
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if (lsu_req_if.valid && lsu_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, rw=%b, byteen=%b, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rd, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rd, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
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end
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if (csr_req_if.valid && csr_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=%0h", $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.rd, csr_req_if.csr_addr, csr_req_if.rs1_data);
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@ -19,14 +19,12 @@ module VX_lsu_unit #(
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VX_commit_if ld_commit_if,
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VX_commit_if st_commit_if
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);
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wire req_valid;
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wire [`NUM_THREADS-1:0] req_tmask;
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wire req_rw;
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wire [`NUM_THREADS-1:0][29:0] req_addr;
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wire [`NUM_THREADS-1:0][1:0] req_offset;
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wire [`NUM_THREADS-1:0][3:0] req_byteen;
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [1:0] req_sext;
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wire [`NUM_THREADS-1:0][31:0] req_addr;
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wire [`LSU_BITS-1:0] req_type;
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [`NR_BITS-1:0] req_rd;
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wire req_wb;
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wire [`NW_BITS-1:0] req_wid;
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@ -38,46 +36,13 @@ module VX_lsu_unit #(
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assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
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end
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reg [1:0] mem_req_sext;
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always @(*) begin
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case (lsu_req_if.byteen)
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`BYTEEN_SB: mem_req_sext = 2'h1;
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`BYTEEN_SH: mem_req_sext = 2'h2;
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default: mem_req_sext = 2'h0;
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endcase
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end
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wire [`NUM_THREADS-1:0][29:0] mem_req_addr;
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wire [`NUM_THREADS-1:0][1:0] mem_req_offset;
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wire [`NUM_THREADS-1:0][3:0] mem_req_byteen;
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wire [`NUM_THREADS-1:0][31:0] mem_req_data;
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reg [3:0] wmask;
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always @(*) begin
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case (`BYTEEN_TYPE(lsu_req_if.byteen))
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0: wmask = 4'b0001;
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1: wmask = 4'b0011;
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default: wmask = 4'b1111;
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endcase
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign mem_req_addr[i] = full_address[i][31:2];
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assign mem_req_offset[i] = full_address[i][1:0];
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assign mem_req_byteen[i] = wmask << full_address[i][1:0];
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assign mem_req_data[i] = lsu_req_if.store_data[i] << {full_address[i][1:0], 3'b0};
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end
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reg [`NUM_THREADS-2:0] addr_matches;
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always @(*) begin
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for (integer i = 1; i < `NUM_THREADS; i++) begin
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addr_matches[i-1] = (mem_req_addr[0] == mem_req_addr[i]) || ~lsu_req_if.tmask[i];
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end
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end
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wire is_dup_load = (0 == lsu_req_if.rw) && (& addr_matches);
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wire [`NUM_THREADS-2:0] addr_matches;
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for (genvar i = 1; i < `NUM_THREADS; i++) begin
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assign addr_matches[i-1] = (full_address[0][31:2] == full_address[i][31:2]) || ~lsu_req_if.tmask[i];
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end
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wire is_dup_load = lsu_req_if.wb && (& addr_matches);
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`IGNORE_WARNINGS_BEGIN
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wire [`NUM_THREADS-1:0][31:0] req_address;
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reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH-1:0] pending_tags;
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`IGNORE_WARNINGS_END
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@ -85,14 +50,14 @@ module VX_lsu_unit #(
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wire stall_in = ~ready_in & req_valid;
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VX_pipe_register #(
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.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))),
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.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) req_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_in),
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.data_in ({lsu_req_if.valid, is_dup_load, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.rd, lsu_req_if.wb, full_address, mem_req_sext, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data}),
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.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_rw, req_rd, req_wb, req_address, req_sext, req_addr, req_offset, req_byteen, req_data})
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.data_in ({lsu_req_if.valid, is_dup_load, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_address, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
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.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_type, req_rd, req_wb, req_data})
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);
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// Can accept new request?
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@ -102,8 +67,7 @@ module VX_lsu_unit #(
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wire [31:0] rsp_pc;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][1:0] rsp_offset;
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wire [1:0] rsp_sext;
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wire [`LSU_BITS-1:0] rsp_type;
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wire rsp_is_dup;
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reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask;
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@ -115,9 +79,14 @@ module VX_lsu_unit #(
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wire [`DCORE_TAG_ID_BITS-1:0] mbuf_waddr, mbuf_raddr;
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wire mbuf_full;
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wire [`NUM_THREADS-1:0][1:0] req_offset, rsp_offset;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign req_offset[i] = req_addr[i][1:0];
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end
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wire mbuf_push = (| (dcache_req_if.valid & dcache_req_if.ready))
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&& (0 == req_sent_mask) // first submission only
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&& (0 == req_rw); // loads only
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&& req_wb; // loads only
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wire mbuf_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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@ -126,7 +95,7 @@ module VX_lsu_unit #(
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assign mbuf_raddr = dcache_rsp_if.tag[0][`DCORE_TAG_ID_BITS-1:0];
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VX_index_buffer #(
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.DATAW (`NW_BITS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 2) + 2 + 1),
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.DATAW (`NW_BITS + 32 + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * 2) + 1),
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.SIZE (`LSUQ_SIZE),
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.FASTRAM (1)
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) req_metadata (
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@ -135,8 +104,8 @@ module VX_lsu_unit #(
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.write_addr (mbuf_waddr),
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.acquire_slot (mbuf_push),
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.read_addr (mbuf_raddr),
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.write_data ({req_wid, req_pc, req_rd, req_wb, req_offset, req_sext, req_is_dup}),
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.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_offset, rsp_sext, rsp_is_dup}),
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.write_data ({req_wid, req_pc, req_rd, req_wb, req_type, req_offset, req_is_dup}),
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.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup}),
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.release_addr (mbuf_raddr),
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.release_slot (mbuf_pop),
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.full (mbuf_full)
|
||||
|
|
@ -175,16 +144,45 @@ module VX_lsu_unit #(
|
|||
end
|
||||
end
|
||||
|
||||
wire req_ready_dep = (!req_rw && !mbuf_full) || (req_rw && st_commit_if.ready);
|
||||
wire req_ready_dep = (req_wb && ~mbuf_full) || (~req_wb && st_commit_if.ready);
|
||||
|
||||
wire [`NUM_THREADS-1:0] dup_mask = {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1};
|
||||
|
||||
// Core Request
|
||||
// DCache Request
|
||||
|
||||
reg [`NUM_THREADS-1:0][29:0] mem_req_addr;
|
||||
reg [`NUM_THREADS-1:0][3:0] mem_req_byteen;
|
||||
reg [`NUM_THREADS-1:0][31:0] mem_req_data;
|
||||
|
||||
always @(*) begin
|
||||
for (integer i = 0; i < `NUM_THREADS; i++) begin
|
||||
mem_req_byteen[i] = {4{req_wb}};
|
||||
case (`LSU_WSIZE(req_type))
|
||||
0: mem_req_byteen[i][req_offset[i]] = 1;
|
||||
1: begin
|
||||
mem_req_byteen[i][req_offset[i]] = 1;
|
||||
mem_req_byteen[i][{req_addr[i][1], 1'b1}] = 1;
|
||||
end
|
||||
default : mem_req_byteen[i] = {4{1'b1}};
|
||||
endcase
|
||||
|
||||
mem_req_data[i] = 'x;
|
||||
case (req_offset[i])
|
||||
1: mem_req_data[i][31:8] = req_data[i][23:0];
|
||||
2: mem_req_data[i][31:16] = req_data[i][15:0];
|
||||
3: mem_req_data[i][31:24] = req_data[i][7:0];
|
||||
default: mem_req_data[i] = req_data[i];
|
||||
endcase
|
||||
|
||||
mem_req_addr[i] = req_addr[i][31:2];
|
||||
end
|
||||
end
|
||||
|
||||
assign dcache_req_if.valid = {`NUM_THREADS{req_valid && req_ready_dep}} & req_tmask & dup_mask & ~req_sent_mask;
|
||||
assign dcache_req_if.rw = {`NUM_THREADS{req_rw}};
|
||||
assign dcache_req_if.byteen = req_byteen;
|
||||
assign dcache_req_if.addr = req_addr;
|
||||
assign dcache_req_if.data = req_data;
|
||||
assign dcache_req_if.rw = {`NUM_THREADS{~req_wb}};
|
||||
assign dcache_req_if.addr = mem_req_addr;
|
||||
assign dcache_req_if.byteen = mem_req_byteen;
|
||||
assign dcache_req_if.data = mem_req_data;
|
||||
|
||||
`ifdef DBG_CACHE_REQ_INFO
|
||||
assign dcache_req_if.tag = {`NUM_THREADS{{req_pc, req_wid, req_tag}}};
|
||||
|
|
@ -194,28 +192,9 @@ module VX_lsu_unit #(
|
|||
|
||||
assign ready_in = req_ready_dep && req_sent_all;
|
||||
|
||||
// load response formatting
|
||||
|
||||
reg [`NUM_THREADS-1:0][31:0] rsp_data;
|
||||
wire [`NUM_THREADS-1:0] rsp_tmask;
|
||||
|
||||
for (genvar i = 0; i < `NUM_THREADS; i++) begin
|
||||
wire [31:0] src_data = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i];
|
||||
wire [31:0] rsp_data_shifted = src_data >> {rsp_offset[i], 3'b0};
|
||||
always @(*) begin
|
||||
case (rsp_sext)
|
||||
1: rsp_data[i] = {{24{rsp_data_shifted[7]}}, rsp_data_shifted[7:0]};
|
||||
2: rsp_data[i] = {{16{rsp_data_shifted[15]}}, rsp_data_shifted[15:0]};
|
||||
default: rsp_data[i] = rsp_data_shifted;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
wire [`NUM_THREADS-1:0] rsp_tmask = rsp_is_dup ? rsp_rem_mask[mbuf_raddr] : dcache_rsp_if.valid;
|
||||
|
||||
// send store commit
|
||||
|
||||
wire is_store_rsp = req_valid && req_rw && req_sent_all;
|
||||
wire is_store_rsp = req_valid && ~req_wb && req_sent_all;
|
||||
|
||||
assign st_commit_if.valid = is_store_rsp;
|
||||
assign st_commit_if.wid = req_wid;
|
||||
|
|
@ -226,6 +205,34 @@ module VX_lsu_unit #(
|
|||
assign st_commit_if.eop = 1'b1;
|
||||
assign st_commit_if.data = 0;
|
||||
|
||||
// load response formatting
|
||||
|
||||
reg [`NUM_THREADS-1:0][31:0] rsp_data;
|
||||
wire [`NUM_THREADS-1:0] rsp_tmask;
|
||||
|
||||
for (genvar i = 0; i < `NUM_THREADS; i++) begin
|
||||
wire [31:0] src_data = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i];
|
||||
|
||||
reg [31:0] rsp_data_shifted;
|
||||
always @(*) begin
|
||||
rsp_data_shifted[31:16] = src_data[31:16];
|
||||
rsp_data_shifted[15:0] = rsp_offset[i][1] ? src_data[31:16] : src_data[15:0];
|
||||
rsp_data_shifted[7:0] = rsp_offset[i][0] ? rsp_data_shifted[15:8] : rsp_data_shifted[7:0];
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (rsp_type)
|
||||
`LSU_SB: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0]));
|
||||
`LSU_SH: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0]));
|
||||
`LSU_UB: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0]));
|
||||
`LSU_UH: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0]));
|
||||
default: rsp_data[i] = rsp_data_shifted;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
wire [`NUM_THREADS-1:0] rsp_tmask = rsp_is_dup ? rsp_rem_mask[mbuf_raddr] : dcache_rsp_if.valid;
|
||||
|
||||
// send load commit
|
||||
|
||||
wire is_load_rsp = (| dcache_rsp_if.valid);
|
||||
|
|
@ -250,8 +257,8 @@ module VX_lsu_unit #(
|
|||
`SCOPE_ASSIGN (dcache_req_fire, dcache_req_if.valid & dcache_req_if.ready);
|
||||
`SCOPE_ASSIGN (dcache_req_wid, req_wid);
|
||||
`SCOPE_ASSIGN (dcache_req_pc, req_pc);
|
||||
`SCOPE_ASSIGN (dcache_req_addr, req_address);
|
||||
`SCOPE_ASSIGN (dcache_req_rw, req_rw);
|
||||
`SCOPE_ASSIGN (dcache_req_addr, req_addr);
|
||||
`SCOPE_ASSIGN (dcache_req_rw, ~req_wb);
|
||||
`SCOPE_ASSIGN (dcache_req_byteen,dcache_req_if.byteen);
|
||||
`SCOPE_ASSIGN (dcache_req_data, dcache_req_if.data);
|
||||
`SCOPE_ASSIGN (dcache_req_tag, req_tag);
|
||||
|
|
@ -264,10 +271,10 @@ module VX_lsu_unit #(
|
|||
if ((| (dcache_req_if.valid & dcache_req_if.ready))) begin
|
||||
if (dcache_req_if.rw[0])
|
||||
$display("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, data=%0h",
|
||||
$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data);
|
||||
$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data);
|
||||
else
|
||||
$display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, rd=%0d, is_dup=%b",
|
||||
$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, req_rd, req_is_dup);
|
||||
$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, req_rd, req_is_dup);
|
||||
end
|
||||
if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
|
||||
$display("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h, is_dup=%b",
|
||||
|
|
|
|||
|
|
@ -61,17 +61,12 @@ task print_ex_op (
|
|||
end
|
||||
`EX_LSU: begin
|
||||
case (`LSU_BITS'(op_type))
|
||||
`LSU_LB: $write("LB");
|
||||
`LSU_LH: $write("LH");
|
||||
`LSU_LW: $write("LW");
|
||||
`LSU_LBU: $write("LBU");
|
||||
`LSU_LHU: $write("LHU");
|
||||
`LSU_SB: $write("SB");
|
||||
`LSU_SH: $write("SH");
|
||||
`LSU_SW: $write("SW");
|
||||
`LSU_SBU: $write("SBU");
|
||||
`LSU_SHU: $write("SHU");
|
||||
default: $write("?");
|
||||
`LSU_SB: $write("SB");
|
||||
`LSU_SH: $write("SH");
|
||||
`LSU_SW: $write("SW");
|
||||
`LSU_UB: $write("UB");
|
||||
`LSU_UH: $write("UH");
|
||||
default: $write("?");
|
||||
endcase
|
||||
end
|
||||
`EX_CSR: begin
|
||||
|
|
|
|||
|
|
@ -9,8 +9,7 @@ interface VX_lsu_req_if ();
|
|||
wire [`NW_BITS-1:0] wid;
|
||||
wire [`NUM_THREADS-1:0] tmask;
|
||||
wire [31:0] PC;
|
||||
wire rw;
|
||||
wire [`BYTEEN_BITS-1:0] byteen;
|
||||
wire [`LSU_BITS-1:0] op_type;
|
||||
wire [`NUM_THREADS-1:0][31:0] store_data;
|
||||
wire [`NUM_THREADS-1:0][31:0] base_addr;
|
||||
wire [31:0] offset;
|
||||
|
|
|
|||
|
|
@ -89,11 +89,11 @@ vx_num_cores:
|
|||
.type vx_num_cycles, @function
|
||||
.global vx_num_cycles
|
||||
vx_num_cycles:
|
||||
csrr a0, CSR_MCYCLE
|
||||
csrr a0, CSR_CYCLE
|
||||
ret
|
||||
|
||||
.type vx_num_instrs, @function
|
||||
.global vx_num_instrs
|
||||
vx_num_instrs:
|
||||
csrr a0, CSR_MINSTRET
|
||||
csrr a0, CSR_INSTRET
|
||||
ret
|
||||
Loading…
Add table
Add a link
Reference in a new issue