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reset relay refactory

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This commit is contained in:
Blaise Tine 2024-09-04 13:39:51 -07:00
parent 039e5e2ffc
commit 7ca9a5e87e
16 changed files with 42 additions and 102 deletions
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12
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -475,8 +475,6 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.TAG_WIDTH (AVS_REQ_TAGW)
) cci_vx_mem_bus_if[2]();
`RESET_RELAY (cci_adapter_reset, reset);
VX_mem_adapter #(
.SRC_DATA_WIDTH (CCI_DATA_WIDTH),
.DST_DATA_WIDTH (LMEM_DATA_WIDTH),
@ -488,7 +486,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.RSP_OUT_BUF (0)
) cci_mem_adapter (
.clk (clk),
.reset (cci_adapter_reset),
.reset (reset),
.mem_req_valid_in (cci_mem_req_valid),
.mem_req_addr_in (cci_mem_req_addr),
@ -527,8 +525,6 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
assign vx_mem_req_valid_qual = vx_mem_req_valid && ~vx_mem_is_cout;
`RESET_RELAY (vx_adapter_reset, reset);
VX_mem_adapter #(
.SRC_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
.DST_DATA_WIDTH (LMEM_DATA_WIDTH),
@ -540,7 +536,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.RSP_OUT_BUF (2)
) vx_mem_adapter (
.clk (clk),
.reset (vx_adapter_reset),
.reset (reset),
.mem_req_valid_in (vx_mem_req_valid_qual),
.mem_req_addr_in (vx_mem_req_addr),
@ -595,8 +591,6 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
//--
`RESET_RELAY (avs_adapter_reset, reset);
VX_avs_adapter #(
.DATA_WIDTH (LMEM_DATA_WIDTH),
.ADDR_WIDTH (LMEM_ADDR_WIDTH),
@ -608,7 +602,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.RSP_OUT_BUF (0)
) avs_adapter (
.clk (clk),
.reset (avs_adapter_reset),
.reset (reset),
// Memory request
.mem_req_valid (mem_bus_if[0].req_valid),

12
hw/rtl/cache/VX_cache.sv vendored
View file

@ -319,8 +319,6 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [`PERF_CTR_BITS-1:0] perf_collisions;
`endif
`RESET_RELAY (req_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_REQS),
.NUM_OUTPUTS (NUM_BANKS),
@ -330,7 +328,7 @@ module VX_cache import VX_gpu_pkg::*; #(
.OUT_BUF (REQ_XBAR_BUF)
) req_xbar (
.clk (clk),
.reset (req_xbar_reset),
.reset (reset),
`ifdef PERF_ENABLE
.collisions(perf_collisions),
`else
@ -369,8 +367,6 @@ module VX_cache import VX_gpu_pkg::*; #(
assign curr_bank_mem_rsp_valid = mem_rsp_valid_s && (`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s) == bank_id);
end
`RESET_RELAY (bank_reset, reset);
VX_cache_bank #(
.BANK_ID (bank_id),
.INSTANCE_ID ($sformatf("%s-bank%0d", INSTANCE_ID, bank_id)),
@ -392,7 +388,7 @@ module VX_cache import VX_gpu_pkg::*; #(
.MEM_OUT_REG (MEM_REQ_REG_DISABLE ? 0 : `TO_OUT_BUF_REG(MEM_OUT_BUF))
) bank (
.clk (clk),
.reset (bank_reset),
.reset (reset),
`ifdef PERF_ENABLE
.perf_read_misses (perf_read_miss_per_bank[bank_id]),
@ -455,8 +451,6 @@ module VX_cache import VX_gpu_pkg::*; #(
assign core_rsp_data_in[i] = {per_bank_core_rsp_data[i], per_bank_core_rsp_tag[i]};
end
`RESET_RELAY (rsp_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_BANKS),
.NUM_OUTPUTS (NUM_REQS),
@ -464,7 +458,7 @@ module VX_cache import VX_gpu_pkg::*; #(
.ARBITER ("R")
) rsp_xbar (
.clk (clk),
.reset (rsp_xbar_reset),
.reset (reset),
`UNUSED_PIN (collisions),
.valid_in (per_bank_core_rsp_valid),
.data_in (core_rsp_data_in),

5
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -139,9 +139,6 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
end
for (genvar i = 0; i < NUM_CACHES; ++i) begin : caches
`RESET_RELAY (cache_reset, reset);
VX_cache_wrap #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, i)),
.CACHE_SIZE (CACHE_SIZE),
@ -169,7 +166,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.cache_perf (perf_cache_unit[i]),
`endif
.clk (clk),
.reset (cache_reset),
.reset (reset),
.core_bus_if (arb_core_bus_if[i * NUM_REQS +: NUM_REQS]),
.mem_bus_if (cache_mem_bus_if[i])
);

8
hw/rtl/core/VX_alu_unit.sv
View file

@ -57,8 +57,6 @@ module VX_alu_unit #(
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alus
`RESET_RELAY_EN (block_reset, reset, (BLOCK_SIZE > 1));
VX_execute_if #(
.NUM_LANES (NUM_LANES)
) pe_execute_if[PE_COUNT]();
@ -82,7 +80,7 @@ module VX_alu_unit #(
.RSP_OUT_BUF (PARTIAL_BW ? 1 : 3)
) pe_switch (
.clk (clk),
.reset (block_reset),
.reset (reset),
.pe_sel (pe_select),
.execute_in_if (per_block_execute_if[block_idx]),
.commit_out_if (per_block_commit_if[block_idx]),
@ -96,7 +94,7 @@ module VX_alu_unit #(
.NUM_LANES (NUM_LANES)
) alu_int (
.clk (clk),
.reset (block_reset),
.reset (reset),
.execute_if (pe_execute_if[PE_IDX_INT]),
.branch_ctl_if (branch_ctl_if[block_idx]),
.commit_if (pe_commit_if[PE_IDX_INT])
@ -108,7 +106,7 @@ module VX_alu_unit #(
.NUM_LANES (NUM_LANES)
) muldiv_unit (
.clk (clk),
.reset (block_reset),
.reset (reset),
.execute_if (pe_execute_if[PE_IDX_MDV]),
.commit_if (pe_commit_if[PE_IDX_MDV])
);

14
hw/rtl/core/VX_fpu_unit.sv
View file

@ -57,8 +57,6 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
`UNUSED_VAR (per_block_execute_if[block_idx].data.tid)
`UNUSED_VAR (per_block_execute_if[block_idx].data.wb)
`RESET_RELAY_EN (block_reset, reset, (BLOCK_SIZE > 1));
// Store request info
wire fpu_req_valid, fpu_req_ready;
wire fpu_rsp_valid, fpu_rsp_ready;
@ -89,7 +87,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.SIZE (`FPUQ_SIZE)
) tag_store (
.clk (clk),
.reset (block_reset),
.reset (reset),
.acquire_en (execute_fire),
.write_addr (fpu_req_tag),
.write_data ({per_block_execute_if[block_idx].data.uuid, per_block_execute_if[block_idx].data.wid, per_block_execute_if[block_idx].data.tmask, per_block_execute_if[block_idx].data.PC, per_block_execute_if[block_idx].data.rd, per_block_execute_if[block_idx].data.pid, per_block_execute_if[block_idx].data.sop, per_block_execute_if[block_idx].data.eop}),
@ -132,7 +130,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) fpu_dpi (
.clk (clk),
.reset (block_reset),
.reset (reset),
.valid_in (fpu_req_valid),
.mask_in (per_block_execute_if[block_idx].data.tmask),
@ -161,7 +159,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) fpu_fpnew (
.clk (clk),
.reset (block_reset),
.reset (reset),
.valid_in (fpu_req_valid),
.mask_in (per_block_execute_if[block_idx].data.tmask),
@ -190,7 +188,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) fpu_dsp (
.clk (clk),
.reset (block_reset),
.reset (reset),
.valid_in (fpu_req_valid),
.mask_in (per_block_execute_if[block_idx].data.tmask),
@ -219,7 +217,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
if (PID_BITS != 0) begin
fflags_t fpu_rsp_fflags_r;
always @(posedge clk) begin
if (block_reset) begin
if (reset) begin
fpu_rsp_fflags_r <= '0;
end else if (fpu_rsp_fire) begin
fpu_rsp_fflags_r <= fpu_rsp_eop ? '0 : (fpu_rsp_fflags_r | fpu_rsp_fflags);
@ -253,7 +251,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.SIZE (0)
) rsp_buf (
.clk (clk),
.reset (block_reset),
.reset (reset),
.valid_in (fpu_rsp_valid),
.ready_in (fpu_rsp_ready),
.data_in ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_result, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}),

4
hw/rtl/core/VX_issue.sv
View file

@ -77,15 +77,13 @@ module VX_issue import VX_gpu_pkg::*; #(
assign decode_if.ibuf_pop[issue_id * PER_ISSUE_WARPS +: PER_ISSUE_WARPS] = per_issue_decode_if.ibuf_pop;
`endif
`RESET_RELAY_EN (slice_reset, reset, (`ISSUE_WIDTH > 1));
VX_issue_slice #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, issue_id)),
.ISSUE_ID (issue_id)
) issue_slice (
`SCOPE_IO_BIND(issue_id)
.clk (clk),
.reset (slice_reset),
.reset (reset),
`ifdef PERF_ENABLE
.issue_perf (per_issue_perf[issue_id]),
`endif

15
hw/rtl/core/VX_issue_slice.sv
View file

@ -36,16 +36,11 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
VX_scoreboard_if scoreboard_if();
VX_operands_if operands_if();
`RESET_RELAY (ibuf_reset, reset);
`RESET_RELAY (scoreboard_reset, reset);
`RESET_RELAY (operands_reset, reset);
`RESET_RELAY (dispatch_reset, reset);
VX_ibuffer #(
.INSTANCE_ID ($sformatf("%s-ibuffer", INSTANCE_ID))
) ibuffer (
.clk (clk),
.reset (ibuf_reset),
.reset (reset),
`ifdef PERF_ENABLE
.perf_stalls (issue_perf.ibf_stalls),
`endif
@ -57,7 +52,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
.INSTANCE_ID ($sformatf("%s-scoreboard", INSTANCE_ID))
) scoreboard (
.clk (clk),
.reset (scoreboard_reset),
.reset (reset),
`ifdef PERF_ENABLE
.perf_stalls (issue_perf.scb_stalls),
.perf_units_uses(issue_perf.units_uses),
@ -72,7 +67,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
.INSTANCE_ID ($sformatf("%s-operands", INSTANCE_ID))
) operands (
.clk (clk),
.reset (operands_reset),
.reset (reset),
`ifdef PERF_ENABLE
.perf_stalls (issue_perf.opd_stalls),
`endif
@ -85,7 +80,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
.INSTANCE_ID ($sformatf("%s-dispatch", INSTANCE_ID))
) dispatch (
.clk (clk),
.reset (dispatch_reset),
.reset (reset),
`ifdef PERF_ENABLE
`UNUSED_PIN (perf_stalls),
`endif
@ -105,7 +100,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
`UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1)
) scope_tap (
.clk (clk),
.reset (scope_reset),
.reset (reset),
.start (1'b0),
.stop (1'b0),
.triggers ({

4
hw/rtl/core/VX_lsu_slice.sv
View file

@ -311,8 +311,6 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
wire [LSU_TAG_WIDTH-1:0] lsu_mem_rsp_tag;
wire lsu_mem_rsp_ready;
`RESET_RELAY (mem_scheduler_reset, reset);
VX_mem_scheduler #(
.INSTANCE_ID ($sformatf("%s-scheduler", INSTANCE_ID)),
.CORE_REQS (NUM_LANES),
@ -330,7 +328,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
.CORE_OUT_BUF(0)
) mem_scheduler (
.clk (clk),
.reset (mem_scheduler_reset),
.reset (reset),
// Input request
.core_req_valid (mem_req_valid),

5
hw/rtl/core/VX_lsu_unit.sv
View file

@ -55,15 +55,12 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
) per_block_commit_if[BLOCK_SIZE]();
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsus
`RESET_RELAY_EN (slice_reset, reset, (BLOCK_SIZE > 1));
VX_lsu_slice #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, block_idx))
) lsu_slice(
`SCOPE_IO_BIND (block_idx)
.clk (clk),
.reset (slice_reset),
.reset (reset),
.execute_if (per_block_execute_if[block_idx]),
.commit_if (per_block_commit_if[block_idx]),
.lsu_mem_if (lsu_mem_if[block_idx])

11
hw/rtl/core/VX_mem_unit.sv
View file

@ -91,8 +91,6 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
end
end
`RESET_RELAY (lmem_reset, reset);
VX_local_mem #(
.INSTANCE_ID($sformatf("%s-lmem", INSTANCE_ID)),
.SIZE (1 << `LMEM_LOG_SIZE),
@ -105,7 +103,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.OUT_BUF (3)
) local_mem (
.clk (clk),
.reset (lmem_reset),
.reset (reset),
`ifdef PERF_ENABLE
.lmem_perf (lmem_perf),
`endif
@ -132,9 +130,6 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
if (LSU_WORD_SIZE != DCACHE_WORD_SIZE) begin : coalescer_if
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : coalescers
`RESET_RELAY (mem_coalescer_reset, reset);
VX_mem_coalescer #(
.INSTANCE_ID ($sformatf("%s-coalescer%0d", INSTANCE_ID, i)),
.NUM_REQS (`NUM_LSU_LANES),
@ -146,8 +141,8 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.UUID_WIDTH (`UUID_WIDTH),
.QUEUE_SIZE (`LSUQ_OUT_SIZE)
) mem_coalescer (
.clk (clk),
.reset (mem_coalescer_reset),
.clk (clk),
.reset (reset),
// Input request
.in_req_valid (lsu_dcache_if[i].req_valid),

8
hw/rtl/core/VX_operands.sv
View file

@ -99,8 +99,6 @@ module VX_operands import VX_gpu_pkg::*; #(
assign req_in_valid = {NUM_SRC_OPDS{scoreboard_if.valid}} & src_valid;
`RESET_RELAY (req_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_SRC_OPDS),
.NUM_OUTPUTS (NUM_BANKS),
@ -110,7 +108,7 @@ module VX_operands import VX_gpu_pkg::*; #(
.OUT_BUF (0) // no output buffering
) req_xbar (
.clk (clk),
.reset (req_xbar_reset),
.reset (reset),
`UNUSED_PIN(collisions),
.valid_in (req_in_valid),
.data_in (req_in_data),
@ -179,14 +177,12 @@ module VX_operands import VX_gpu_pkg::*; #(
wire pipe_valid2_st1 = pipe_valid_st1 && ~has_collision_st1;
`RESET_RELAY (pipe2_reset, reset); // needed for pipe_reg2's wide RESETW
VX_pipe_buffer #(
.DATAW (NUM_SRC_OPDS * REGS_DATAW + NUM_BANKS + META_DATAW + NUM_BANKS * REQ_SEL_WIDTH),
.RESETW (NUM_SRC_OPDS * REGS_DATAW)
) pipe_reg2 (
.clk (clk),
.reset (pipe2_reset),
.reset (reset),
.valid_in (pipe_valid2_st1),
.ready_in (pipe_ready_st1),
.data_in ({src_data_st1, gpr_rd_valid_st1, pipe_data_st1, gpr_rd_req_idx_st1}),

8
hw/rtl/core/VX_schedule.sv
View file

@ -289,13 +289,11 @@ module VX_schedule import VX_gpu_pkg::*; #(
// split/join handling
`RESET_RELAY (split_join_reset, reset);
VX_split_join #(
.INSTANCE_ID ($sformatf("%s-splitjoin", INSTANCE_ID))
) split_join (
.clk (clk),
.reset (split_join_reset),
.reset (reset),
.valid (warp_ctl_if.valid),
.wid (warp_ctl_if.wid),
.split (warp_ctl_if.split),
@ -377,15 +375,13 @@ module VX_schedule import VX_gpu_pkg::*; #(
wire [`NUM_WARPS-1:0] pending_warp_empty;
wire [`NUM_WARPS-1:0] pending_warp_alm_empty;
`RESET_RELAY (pending_instr_reset, reset);
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_sizes
VX_pending_size #(
.SIZE (4096),
.ALM_EMPTY (1)
) counter (
.clk (clk),
.reset (pending_instr_reset),
.reset (reset),
.incr (schedule_if_fire && (schedule_if.data.wid == `NW_WIDTH'(i))),
.decr (commit_sched_if.committed_warps[i]),
.empty (pending_warp_empty[i]),

8
hw/rtl/core/VX_sfu_unit.sv
View file

@ -98,28 +98,24 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
.commit_in_if (pe_commit_if)
);
`RESET_RELAY (wctl_reset, reset);
VX_wctl_unit #(
.INSTANCE_ID ($sformatf("%s-wctl", INSTANCE_ID)),
.NUM_LANES (NUM_LANES)
) wctl_unit (
.clk (clk),
.reset (wctl_reset),
.reset (reset),
.execute_if (pe_execute_if[PE_IDX_WCTL]),
.warp_ctl_if(warp_ctl_if),
.commit_if (pe_commit_if[PE_IDX_WCTL])
);
`RESET_RELAY (csr_reset, reset);
VX_csr_unit #(
.INSTANCE_ID ($sformatf("%s-csr", INSTANCE_ID)),
.CORE_ID (CORE_ID),
.NUM_LANES (NUM_LANES)
) csr_unit (
.clk (clk),
.reset (csr_reset),
.reset (reset),
.base_dcrs (base_dcrs),
.execute_if (pe_execute_if[PE_IDX_CSRS]),

16
hw/rtl/fpu/VX_fpu_dsp.sv
View file

@ -130,14 +130,12 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
wire is_neg = per_core_op_type[FPU_FMA][0];
wire is_sub = per_core_fmt[FPU_FMA][1];
`RESET_RELAY (fma_reset, reset);
VX_fpu_fma #(
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (TAG_WIDTH)
) fpu_fma (
.clk (clk),
.reset (fma_reset),
.reset (reset),
.valid_in (per_core_valid_in[FPU_FMA]),
.ready_in (per_core_ready_in[FPU_FMA]),
.mask_in (per_core_mask_in[FPU_FMA]),
@ -231,14 +229,12 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
`UNUSED_VAR (div_sqrt_datab)
`UNUSED_VAR (div_sqrt_datac)
`RESET_RELAY (div_sqrt_reset, reset);
VX_fpu_div #(
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (TAG_WIDTH)
) fpu_div (
.clk (clk),
.reset (div_sqrt_reset),
.reset (reset),
.valid_in (div_sqrt_valid_in[0]),
.ready_in (div_sqrt_ready_in[0]),
.mask_in (div_sqrt_mask_in[0]),
@ -313,14 +309,12 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
wire cvt_ret_int_in = ~is_itof;
wire cvt_ret_int_out;
`RESET_RELAY (cvt_reset, reset);
VX_fpu_cvt #(
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (1+TAG_WIDTH)
) fpu_cvt (
.clk (clk),
.reset (cvt_reset),
.reset (reset),
.valid_in (per_core_valid_in[FPU_CVT]),
.ready_in (per_core_ready_in[FPU_CVT]),
.mask_in (per_core_mask_in[FPU_CVT]),
@ -347,14 +341,12 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
wire ncp_ret_sext_in = `INST_FPU_IS_MVXW(per_core_op_type[FPU_NCP], per_core_frm[FPU_NCP]);
wire ncp_ret_sext_out;
`RESET_RELAY (ncp_reset, reset);
VX_fpu_ncp #(
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (TAG_WIDTH+2)
) fpu_ncp (
.clk (clk),
.reset (ncp_reset),
.reset (reset),
.valid_in (per_core_valid_in[FPU_NCP]),
.ready_in (per_core_ready_in[FPU_NCP]),
.mask_in (per_core_mask_in[FPU_NCP]),

6
hw/rtl/libs/VX_stream_unpack.sv
View file

@ -42,14 +42,14 @@ module VX_stream_unpack #(
wire [NUM_REQS-1:0] ready_out_w;
wire [NUM_REQS-1:0] rem_mask_n = rem_mask_r & ~ready_out_w;
wire sent_all = (mask_in & rem_mask_n) == '0;
wire sent_all = ~(| (mask_in & rem_mask_n));
always @(posedge clk) begin
if (reset) begin
rem_mask_r <= {NUM_REQS{1'b1}};
rem_mask_r <= '1;
end else begin
if (valid_in) begin
rem_mask_r <= {NUM_REQS{sent_all}} | rem_mask_n;
rem_mask_r <= sent_all ? '1 : rem_mask_n;
end
end
end

8
hw/rtl/mem/VX_local_mem.sv
View file

@ -116,8 +116,6 @@ module VX_local_mem import VX_gpu_pkg::*; #(
assign mem_bus_if[i].req_ready = req_ready_in[i];
end
`RESET_RELAY (req_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_REQS),
.NUM_OUTPUTS (NUM_BANKS),
@ -127,7 +125,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.OUT_BUF (3) // output should be registered for the data_store addressing
) req_xbar (
.clk (clk),
.reset (req_xbar_reset),
.reset (reset),
`ifdef PERF_ENABLE
.collisions (perf_collisions),
`else
@ -226,8 +224,6 @@ module VX_local_mem import VX_gpu_pkg::*; #(
wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out;
wire [NUM_REQS-1:0] rsp_ready_out;
`RESET_RELAY (rsp_xbar_reset, reset);
VX_stream_xbar #(
.NUM_INPUTS (NUM_BANKS),
.NUM_OUTPUTS (NUM_REQS),
@ -236,7 +232,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.OUT_BUF (OUT_BUF)
) rsp_xbar (
.clk (clk),
.reset (rsp_xbar_reset),
.reset (reset),
`UNUSED_PIN (collisions),
.sel_in (per_bank_rsp_idx),
.valid_in (per_bank_rsp_valid),