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reset network refactoring

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This commit is contained in:
Blaise Tine 2021-07-15 11:34:55 -07:00
parent 22cf698e69
commit 7d01be367c
11 changed files with 68 additions and 137 deletions
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19
hw/rtl/VX_cluster.v
View file

@ -44,24 +44,17 @@ module VX_cluster #(
wire [`NUM_CORES-1:0] per_core_busy;
wire [`NUM_CORES-1:0] core_reset;
VX_reset_relay #(
.DEPTH (`NUM_CORES > 1),
.NUM_NODES (`NUM_CORES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (core_reset)
);
for (genvar i = 0; i < `NUM_CORES; i++) begin
`RESET_RELAY (core_reset);
VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) core (
`SCOPE_BIND_VX_cluster_core(i)
.clk (clk),
.reset (core_reset[i]),
.reset (core_reset),
.mem_req_valid (per_core_mem_req_valid[i]),
.mem_req_rw (per_core_mem_req_rw [i]),
@ -87,6 +80,8 @@ module VX_cluster #(
VX_perf_cache_if perf_l2cache_if();
`endif
`RESET_RELAY (l2_reset);
VX_cache #(
.CACHE_ID (`L2CACHE_ID),
.CACHE_SIZE (`L2CACHE_SIZE),
@ -107,7 +102,7 @@ module VX_cluster #(
`SCOPE_BIND_VX_cluster_l2cache
.clk (clk),
.reset (reset),
.reset (l2_reset),
`ifdef PERF_ENABLE
.perf_cache_if (perf_l2cache_if),

15
hw/rtl/VX_execute.v
View file

@ -43,14 +43,10 @@ module VX_execute #(
wire[`NUM_WARPS-1:0] csr_pending;
wire[`NUM_WARPS-1:0] fpu_pending;
wire alu_reset, lsu_reset, csr_reset, fpu_reset, gpu_reset;
VX_reset_relay #(
.NUM_NODES (5)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o ({alu_reset, lsu_reset, csr_reset, fpu_reset, gpu_reset})
);
`RESET_RELAY (alu_reset);
`RESET_RELAY (lsu_reset);
`RESET_RELAY (csr_reset);
`RESET_RELAY (gpu_reset);
VX_alu_unit #(
.CORE_ID (CORE_ID)
@ -94,6 +90,8 @@ module VX_execute #(
);
`ifdef EXT_F_ENABLE
`RESET_RELAY (fpu_reset);
VX_fpu_unit #(
.CORE_ID (CORE_ID)
) fpu_unit (
@ -106,7 +104,6 @@ module VX_execute #(
.pending (fpu_pending)
);
`else
`UNUSED_VAR (fpu_reset)
`UNUSED_VAR (csr_pending)
`UNUSED_VAR (fpu_to_csr_if.read_frm)
assign fpu_req_if.ready = 0;

14
hw/rtl/VX_mem_unit.v
View file

@ -63,14 +63,8 @@ module VX_mem_unit # (
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_rsp_if();
wire icache_reset, dcache_reset, smem_reset;
VX_reset_relay #(
.NUM_NODES (3)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o ({icache_reset, dcache_reset, smem_reset})
);
`RESET_RELAY (icache_reset);
`RESET_RELAY (dcache_reset);
VX_cache #(
.CACHE_ID (`ICACHE_ID),
@ -214,6 +208,8 @@ module VX_mem_unit # (
.core_rsp_if (dcache_core_rsp_if)
);
`RESET_RELAY (smem_reset);
VX_shared_mem #(
.CACHE_ID (`SCACHE_ID),
.CACHE_SIZE (`SMEM_SIZE),
@ -249,8 +245,6 @@ module VX_mem_unit # (
.core_rsp_ready (smem_rsp_if.ready)
);
end else begin
`UNUSED_VAR (smem_reset)
// core to D-cache request
assign dcache_req_if.valid = dcache_core_req_if.valid;
assign dcache_req_if.addr = dcache_core_req_if.addr;

13
hw/rtl/VX_pipeline.v
View file

@ -132,14 +132,11 @@ module VX_pipeline #(
VX_perf_pipeline_if perf_pipeline_if();
`endif
wire fetch_reset, decode_reset, issue_reset, execute_reset, commit_reset;
VX_reset_relay #(
.NUM_NODES (5)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o ({fetch_reset, decode_reset, issue_reset, execute_reset, commit_reset})
);
`RESET_RELAY (fetch_reset);
`RESET_RELAY (decode_reset);
`RESET_RELAY (issue_reset);
`RESET_RELAY (execute_reset);
`RESET_RELAY (commit_reset);
VX_fetch #(
.CORE_ID(CORE_ID)

8
hw/rtl/VX_platform.vh
View file

@ -57,6 +57,14 @@
`define TRACING_ON /* verilator tracing_on */
`define TRACING_OFF /* verilator tracing_off */
`define RESET_RELAY(signal) \
wire signal; \
VX_reset_relay __``signal ( \
.clk (clk), \
.reset (reset), \
.reset_o (signal) \
)
///////////////////////////////////////////////////////////////////////////////
`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *)

19
hw/rtl/Vortex.v
View file

@ -42,24 +42,17 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
wire [`NUM_CLUSTERS-1:0] cluster_reset;
VX_reset_relay #(
.DEPTH (`NUM_CLUSTERS > 1),
.NUM_NODES (`NUM_CLUSTERS)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (cluster_reset)
);
for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
`RESET_RELAY (cluster_reset);
VX_cluster #(
.CLUSTER_ID(i)
) cluster (
`SCOPE_BIND_Vortex_cluster(i)
.clk (clk),
.reset (cluster_reset[i]),
.reset (cluster_reset),
.mem_req_valid (per_cluster_mem_req_valid [i]),
.mem_req_rw (per_cluster_mem_req_rw [i]),
@ -85,6 +78,8 @@ module Vortex (
VX_perf_cache_if perf_l3cache_if();
`endif
`RESET_RELAY (l3_reset);
VX_cache #(
.CACHE_ID (`L3CACHE_ID),
.CACHE_SIZE (`L3CACHE_SIZE),
@ -105,7 +100,7 @@ module Vortex (
`SCOPE_BIND_Vortex_l3cache
.clk (clk),
.reset (reset),
.reset (l3_reset),
`ifdef PERF_ENABLE
.perf_cache_if (perf_l3cache_if),

16
hw/rtl/fp_cores/VX_fp_div.v
View file

@ -33,18 +33,6 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
`ifndef VERILATOR
wire [LANES-1:0] fdiv_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
`endif
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
@ -67,9 +55,11 @@ module VX_fp_div #(
.data_out (result[i])
);
`else
`RESET_RELAY (fdiv_reset);
acl_fdiv fdiv (
.clk (clk),
.areset (fdiv_reset[i]),
.areset (fdiv_reset),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

16
hw/rtl/fp_cores/VX_fp_fma.v
View file

@ -39,18 +39,6 @@ module VX_fp_fma #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
`ifndef VERILATOR
wire [LANES-1:0] fma_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fma_reset)
);
`endif
for (genvar i = 0; i < LANES; i++) begin
reg [31:0] a, b, c;
@ -96,9 +84,11 @@ module VX_fp_fma #(
.data_out (result[i])
);
`else
`RESET_RELAY (fma_reset);
acl_fmadd fmadd (
.clk (clk),
.areset (fma_reset[i]),
.areset (fma_reset),
.en (enable),
.a (a),
.b (b),

16
hw/rtl/fp_cores/VX_fp_sqrt.v
View file

@ -32,18 +32,6 @@ module VX_fp_sqrt #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
`ifndef VERILATOR
wire [LANES-1:0] fsqrt_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
`endif
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
@ -66,9 +54,11 @@ module VX_fp_sqrt #(
.data_out (result[i])
);
`else
`RESET_RELAY (fsqrt_reset);
acl_fsqrt fsqrt (
.clk (clk),
.areset (fsqrt_reset[i]),
.areset (fsqrt_reset),
.en (enable),
.a (dataa[i]),
.q (result[i])

23
hw/rtl/fp_cores/VX_fpu_fpga.v
View file

@ -71,21 +71,18 @@ module VX_fpu_fpga #(
endcase
end
wire [NUM_FPC-1:0] fpu_reset;
VX_reset_relay #(
.NUM_NODES(NUM_FPC)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fpu_reset)
);
`RESET_RELAY (fma_reset);
`RESET_RELAY (div_reset);
`RESET_RELAY (sqrt_reset);
`RESET_RELAY (cvt_reset);
`RESET_RELAY (ncp_reset);
VX_fp_fma #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_fma (
.clk (clk),
.reset (fpu_reset[FPU_FMA]),
.reset (fma_reset),
.valid_in (valid_in && (core_select == FPU_FMA)),
.ready_in (per_core_ready_in[FPU_FMA]),
.tag_in (tag_in),
@ -109,7 +106,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_div (
.clk (clk),
.reset (fpu_reset[FPU_DIV]),
.reset (div_reset),
.valid_in (valid_in && (core_select == FPU_DIV)),
.ready_in (per_core_ready_in[FPU_DIV]),
.tag_in (tag_in),
@ -129,7 +126,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_sqrt (
.clk (clk),
.reset (fpu_reset[FPU_SQRT]),
.reset (sqrt_reset),
.valid_in (valid_in && (core_select == FPU_SQRT)),
.ready_in (per_core_ready_in[FPU_SQRT]),
.tag_in (tag_in),
@ -148,7 +145,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_cvt (
.clk (clk),
.reset (fpu_reset[FPU_CVT]),
.reset (cvt_reset),
.valid_in (valid_in && (core_select == FPU_CVT)),
.ready_in (per_core_ready_in[FPU_CVT]),
.tag_in (tag_in),
@ -169,7 +166,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_ncomp (
.clk (clk),
.reset (fpu_reset[FPU_NCP]),
.reset (ncp_reset),
.valid_in (valid_in && (core_select == FPU_NCP)),
.ready_in (per_core_ready_in[FPU_NCP]),
.tag_in (tag_in),

44
hw/rtl/libs/VX_reset_relay.v
View file

@ -1,46 +1,24 @@
`include "VX_platform.vh"
module VX_reset_relay #(
parameter NUM_NODES = 1,
parameter DEPTH = 1,
parameter ASYNC = 0
parameter ASYNC = 0
) (
input wire clk,
input wire reset,
output wire [NUM_NODES-1:0] reset_o
output wire reset_o
);
(* preserve *) reg reset_r;
if (DEPTH > 1) begin
`DISABLE_BRAM reg [NUM_NODES-1:0] reset_r [DEPTH-1:0];
if (ASYNC) begin
always @(posedge clk or posedge reset) begin
for (integer i = DEPTH-1; i > 0; --i)
reset_r[i] <= reset_r[i-1];
reset_r[0] <= {NUM_NODES{reset}};
end
end else begin
always @(posedge clk) begin
for (integer i = DEPTH-1; i > 0; --i)
reset_r[i] <= reset_r[i-1];
reset_r[0] <= {NUM_NODES{reset}};
end
if (ASYNC) begin
always @(posedge clk or posedge reset) begin
reset_r <= reset;
end
assign reset_o = reset_r[DEPTH-1];
end else if (DEPTH == 1) begin
reg [NUM_NODES-1:0] reset_r;
if (ASYNC) begin
always @(posedge clk or posedge reset) begin
reset_r <= {NUM_NODES{reset}};
end
end else begin
always @(posedge clk) begin
reset_r <= {NUM_NODES{reset}};
end
end
assign reset_o = reset_r;
end else begin
`UNUSED_VAR (clk)
assign reset_o = {NUM_NODES{reset}};
always @(posedge clk) begin
reset_r <= reset;
end
end
assign reset_o = reset_r;
endmodule