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minor update

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This commit is contained in:
Blaise Tine 2021-06-23 04:19:13 -07:00
parent 1a33c83e6e
commit 7e0dc81cee
3 changed files with 14 additions and 5 deletions
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15
hw/rtl/afu/VX_avs_wrapper.v
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@ -51,8 +51,13 @@ module VX_avs_wrapper #(
wire [NUM_BANKS-1:0] req_queue_going_full;
wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size;
wire [NUM_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_data_out;
wire [BANK_ADDRW-1:0] req_bank_sel = (NUM_BANKS >= 2) ? mem_req_addr[BANK_ADDRW-1:0] : '0;
wire [BANK_ADDRW-1:0] req_bank_sel;
if (NUM_BANKS >= 2) begin
assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0];
end else begin
assign req_bank_sel = 0;
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign avs_reqq_ready[i] = !req_queue_going_full[i] && !avs_waitrequest[i];
@ -100,7 +105,11 @@ module VX_avs_wrapper #(
assign avs_burstcount[i] = AVS_BURST_WIDTH'(1);
end
assign mem_req_ready = avs_reqq_ready[req_bank_sel];
if (NUM_BANKS >= 2) begin
assign mem_req_ready = avs_reqq_ready[req_bank_sel];
end else begin
assign mem_req_ready = avs_reqq_ready;
end
// Responses handling

2
hw/scripts/scope.json
View file

@ -74,7 +74,7 @@
"taps": {
"afu": {
"!cmd_type":3,
"!state":3,
"!state":2,
"?cci_sRxPort_c0_mmioRdValid":1,
"?cci_sRxPort_c0_mmioWrValid":1,
"mmio_hdr_address":16,

2
hw/simulate/simulator.cpp
View file

@ -173,7 +173,7 @@ void Simulator::eval_mem_bus() {
}
// select the memory bank
uint32_t req_bank = vortex_->mem_req_addr % MEMORY_BANKS;
uint32_t req_bank = (MEMORY_BANKS >= 2) ? (vortex_->mem_req_addr % MEMORY_BANKS) : 0;
// handle memory stalls
bool mem_stalled = false;