Add more 64b WARNING fixes

hw/rtl/VX_gpu_types.vh

@@ -69,7 +69,7 @@ localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(ICACHE_NUM_REQ
 ////////////////////////// Dcache Parameters //////////////////////////////////
 
 // Word size in bytes
-localparam DCACHE_WORD_SIZE	    = 4;
+localparam DCACHE_WORD_SIZE	    = (`XLEN/8);
 localparam DCACHE_ADDR_WIDTH	= (`XLEN - `CLOG2(DCACHE_WORD_SIZE));
 
 // Block size in bytes

hw/rtl/core/VX_csr_unit.sv

@@ -190,12 +190,12 @@ module VX_csr_unit #(
 
     // CSR read
 
-    wire [`NUM_THREADS-1:0][31:0] wtid, ltid, gtid;
+    wire [`NUM_THREADS-1:0][`XLEN-1:0] wtid, ltid, gtid;
 
     for (genvar i = 0; i < `NUM_THREADS; ++i) begin
-        assign wtid[i] = 32'(i);
-        assign ltid[i] = (32'(csr_req_if.wid) << `NT_BITS) + i;
-        assign gtid[i] = 32'((32'(CORE_ID) << (`NW_BITS + `NT_BITS)) + (32'(csr_req_if.wid) << `NT_BITS) + i);
+        assign wtid[i] = `XLEN'(i);
+        assign ltid[i] = (`XLEN'(csr_req_if.wid) << `NT_BITS) + i;
+        assign gtid[i] = `XLEN'((`XLEN'(CORE_ID) << (`NW_BITS + `NT_BITS)) + (`XLEN'(csr_req_if.wid) << `NT_BITS) + i);
     end  
 
     always @(*) begin
@@ -242,13 +242,13 @@ module VX_csr_unit #(
     end
 
     // send response
-    wire [`NUM_THREADS-1:0][31:0]   csr_commit_data;
+    wire [`NUM_THREADS-1:0][`XLEN-1:0]   csr_commit_data;
     for(genvar i = 0; i < `NUM_THREADS; ++i) begin
         assign csr_commit_if.data[i] = `XLEN'(csr_commit_data[i]);
     end
 
     VX_skid_buffer #(
-        .DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + `NUM_THREADS * 32)
+        .DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + `NUM_THREADS * `XLEN)
     ) rsp_sbuf (
         .clk       (clk),
         .reset     (reset),

hw/rtl/core/VX_lsu_unit.sv

@@ -107,7 +107,7 @@ module VX_lsu_unit #(
     wire                           mem_req_valid;
     wire [`NUM_THREADS-1:0]        mem_req_mask;
     wire                           mem_req_rw;  
-    wire [`NUM_THREADS-1:0][`XLEN-3:0]  mem_req_addr;
+    wire [`NUM_THREADS-1:0][`XLEN-REQ_ASHIFT-1:0]  mem_req_addr;
     reg  [`NUM_THREADS-1:0][DCACHE_WORD_SIZE-1:0]   mem_req_byteen;
     reg  [`NUM_THREADS-1:0][`XLEN-1:0]  mem_req_data;
     wire [TAG_WIDTH-1:0]           mem_req_tag;

hw/rtl/core/VX_warp_sched.sv

@@ -151,7 +151,7 @@ module VX_warp_sched #(
             end
 
             if (ifetch_req_fire) begin
-                warp_pcs[ifetch_req_if.wid] <= `XLEN'(ifetch_req_if.PC + 32'(4));
+                warp_pcs[ifetch_req_if.wid] <= `XLEN'(`XLEN'(ifetch_req_if.PC) + 4);
             end
 
             if (wrelease_if.valid) begin