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rtl refactoring

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This commit is contained in:
Blaise Tine 2020-05-05 16:28:14 -04:00
parent 5def6d0da6
commit 7e748e4e38
3 changed files with 29 additions and 27 deletions
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49
hw/simulate/simulator.cpp
View file

@ -8,8 +8,7 @@ double sc_time_stamp() {
return time_stamp;
}
Simulator::Simulator(RAM *ram)
: dram_stalled_(false) {
Simulator::Simulator(RAM *ram) {
ram_ = ram;
vortex_ = new VVortex_Socket();
@ -34,31 +33,45 @@ void Simulator::print_stats(std::ostream& out) {
}
void Simulator::dbus_driver() {
// handle DRAM response cycle
int dequeue_index = -1;
for (int i = 0; i < dram_req_vec_.size(); i++) {
if (dram_req_vec_[i].cycles_left > 0) {
dram_req_vec_[i].cycles_left -= 1;
for (int i = 0; i < dram_rsp_vec_.size(); i++) {
if (dram_rsp_vec_[i].cycles_left > 0) {
dram_rsp_vec_[i].cycles_left -= 1;
}
if ((dequeue_index == -1)
&& (dram_req_vec_[i].cycles_left == 0)) {
&& (dram_rsp_vec_[i].cycles_left == 0)) {
dequeue_index = i;
}
}
// handle DRAM response message
if ((dequeue_index != -1)
&& vortex_->dram_rsp_ready) {
vortex_->dram_rsp_valid = 1;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
vortex_->dram_rsp_data[i] = dram_rsp_vec_[dequeue_index].data[i];
}
vortex_->dram_rsp_tag = dram_req_vec_[dequeue_index].tag;
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
free(dram_rsp_vec_[dequeue_index].data);
dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
} else {
vortex_->dram_rsp_valid = 0;
}
if (!dram_stalled_) {
// handle DRAM stalls
bool dram_stalled = false;
#ifdef ENABLE_DRAM_STALLS
if (0 == ((time_stamp/2) % DRAM_STALLS_MODULO)) {
dram_stalled = true;
} else
if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled = true;
}
#endif
// handle DRAM requests
if (!dram_stalled) {
if (vortex_->dram_req_read) {
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
@ -72,7 +85,7 @@ void Simulator::dbus_driver() {
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
dram_req_vec_.push_back(dram_req);
dram_rsp_vec_.push_back(dram_req);
}
if (vortex_->dram_req_write) {
@ -85,17 +98,7 @@ void Simulator::dbus_driver() {
}
}
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == ((time_stamp/2) % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
vortex_->dram_req_ready = ~dram_stalled_;
vortex_->dram_req_ready = ~dram_stalled;
}
void Simulator::io_driver() {

5
hw/simulate/simulator.h
View file

@ -14,7 +14,7 @@
#include <ostream>
#include <vector>
//#define ENABLE_DRAM_STALLS
#define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 100
#define DRAM_RQ_SIZE 16
#define DRAM_STALLS_MODULO 16
@ -46,8 +46,7 @@ private:
void dbus_driver();
void io_driver();
bool dram_stalled_;
std::vector<dram_req_t> dram_req_vec_;
std::vector<dram_req_t> dram_rsp_vec_;
RAM *ram_;
VVortex_Socket *vortex_;

2
hw/simulate/testbench.cpp
View file

@ -10,7 +10,7 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv);
#define ALL_TESTS
//#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;