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Shared Memory Implemented
This commit is contained in:
Lyons, Ethan Tyler
GitHub Enterprise
parent
2994e607e3
commit
7f7d17d176
2 changed files with 100 additions and 42 deletions
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@ -2,8 +2,20 @@
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module VX_shared_memory
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#(
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parameter NB = 4,
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parameter BITS_PER_BANK = 3
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parameter SM_SIZE = 4096, // Bytes
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parameter SM_BANKS = 4,
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parameter SM_BYTES_PER_READ = 16,
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parameter SM_WORDS_PER_READ = 4,
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parameter SM_LOG_WORDS_PER_READ = 2,
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parameter SM_HEIGHT = 128, // Bytes
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parameter SM_BANK_OFFSET_START = 2,
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parameter SM_BANK_OFFSET_END = 4,
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parameter SM_BLOCK_OFFSET_START = 5,
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parameter SM_BLOCK_OFFSET_END = 6,
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parameter SM_INDEX_START = 7,
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parameter SM_INDEX_END = 13,
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parameter NUM_REQ = 4,
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parameter BITS_PER_BANK = 3
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)
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(
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//INPUTS
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@ -20,21 +32,29 @@ module VX_shared_memory
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output wire stall
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);
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reg[NB:0][31:0] temp_address;
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reg[NB:0][31:0] temp_in_data;
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reg[NB:0] temp_in_valid;
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//reg[NB:0][31:0] temp_address;
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//reg[NB:0][31:0] temp_in_data;
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//reg[NB:0] temp_in_valid;
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reg[SM_BANKS - 1:0][31:0] temp_address;
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reg[SM_BANKS - 1:0][31:0] temp_in_data;
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reg[SM_BANKS - 1:0] temp_in_valid;
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reg[`NT_M1:0] temp_out_valid;
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reg[`NT_M1:0][31:0] temp_out_data;
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reg [NB:0][6:0] block_addr;
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reg [NB:0][3:0][31:0] block_wdata;
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reg [NB:0][3:0][31:0] block_rdata;
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reg [NB:0][1:0] block_we;
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//reg [NB:0][6:0] block_addr;
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//reg [NB:0][3:0][31:0] block_wdata;
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//reg [NB:0][3:0][31:0] block_rdata;
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//reg [NB:0][1:0] block_we;
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reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr;
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reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata;
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reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata;
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reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ:0] block_we;
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wire send_data;
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reg[NB:0][1:0] req_num;
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//reg[NB:0][1:0] req_num;
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reg[SM_BANKS - 1:0][$clog2(NUM_REQ) - 1:0] req_num; // not positive about this
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wire [`NT_M1:0] orig_in_valid;
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@ -50,7 +70,8 @@ genvar f;
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endgenerate
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VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(
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//VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(
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VX_priority_encoder_sm #(.NB(SM_BANKS - 1), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(
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.clk(clk),
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.reset(reset),
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.in_valid(orig_in_valid),
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@ -70,11 +91,18 @@ VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_enc
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genvar j;
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integer i;
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generate
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for(j=0; j<= NB; j=j+1) begin : sm_mem_block
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//for(j=0; j<= NB; j=j+1) begin : sm_mem_block
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for(j=0; j<= SM_BANKS - 1; j=j+1) begin
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wire shm_write = (mem_write != `NO_MEM_WRITE) && temp_in_valid[j];
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VX_shared_memory_block vx_shared_memory_block(
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VX_shared_memory_block#
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(
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.SMB_HEIGHT(SM_HEIGHT),
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.SMB_WORDS_PER_READ(SM_WORDS_PER_READ),
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.SMB_LOG_WORDS_PER_READ(SM_LOG_WORDS_PER_READ)
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) vx_shared_memory_block
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(
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.clk (clk),
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.reset (reset),
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.addr (block_addr[j]),
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@ -83,19 +111,20 @@ for(j=0; j<= NB; j=j+1) begin : sm_mem_block
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.shm_write(shm_write),
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.data_out (block_rdata[j])
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);
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end
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end
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always @(*) begin
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block_addr = 0;
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block_we = 0;
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block_wdata = 0;
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for(i = 0; i <= NB; i = i+1) begin
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//for(i = 0; i <= NB; i = i+1) begin
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for(i = 0; i <= SM_BANKS - 1; i = i+1) begin
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if(temp_in_valid[i] == 1'b1) begin
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//1. Check if the request is actually to the shared memory
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if((temp_address[i][31:24]) == 8'hFF) begin
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// STORES
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if(mem_write != `NO_MEM_WRITE) begin
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if(mem_write != `NO_MEM_WRITE) begin
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if(mem_write == `SB_MEM_WRITE) begin
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//TODO
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end
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@ -103,13 +132,16 @@ always @(*) begin
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//TODO
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end
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else if(mem_write == `SW_MEM_WRITE) begin
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block_addr[i] = temp_address[i][13:7];
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block_we[i] = temp_address[i][6:5];
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block_wdata[i][temp_address[i][6:5]] = temp_in_data[i];
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//block_addr[i] = temp_address[i][13:7];
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//block_we[i] = temp_address[i][6:5];
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//block_wdata[i][temp_address[i][6:5]] = temp_in_data[i];
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block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START];
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block_we[i] = temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START];
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block_wdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]] = temp_in_data[i];
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end
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end
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//LOADS
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else if(mem_read != `NO_MEM_READ) begin
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else if(mem_read != `NO_MEM_READ) begin
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if(mem_read == `LB_MEM_READ) begin
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//TODO
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end
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@ -119,8 +151,11 @@ always @(*) begin
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end
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else if (mem_read == `LW_MEM_READ)
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begin
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block_addr[i] = temp_address[i][13:7];
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temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]];
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//block_addr[i] = temp_address[i][13:7];
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//temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]];
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//temp_out_valid[req_num[i]] = 1'b1;
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block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START];
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temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]];
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temp_out_valid[req_num[i]] = 1'b1;
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end
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else if (mem_read == `LBU_MEM_READ)
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@ -140,4 +175,4 @@ end
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endgenerate
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endmodule
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endmodule
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@ -1,50 +1,73 @@
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module VX_shared_memory_block (
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module VX_shared_memory_block
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#(
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parameter SMB_SIZE = 4096, // Bytes
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parameter SMB_BYTES_PER_READ = 16,
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parameter SMB_WORDS_PER_READ = 4,
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parameter SMB_LOG_WORDS_PER_READ = 2,
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parameter SMB_HEIGHT = 128, // Bytes
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parameter BITS_PER_BANK = 3
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)
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(
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input wire clk, // Clock
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input wire reset,
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input wire[6:0] addr,
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input wire[3:0][31:0] wdata,
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input wire[1:0] we,
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input wire shm_write,
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//input wire[6:0] addr,
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//input wire[3:0][31:0] wdata,
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//input wire[1:0] we,
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//input wire shm_write,
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//output wire[3:0][31:0] data_out
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input wire[$clog2(SMB_HEIGHT) - 1:0] addr,
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input wire[SMB_WORDS_PER_READ-1:0][31:0] wdata,
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input wire[SMB_LOG_WORDS_PER_READ-1:0] we,
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input wire shm_write,
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output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out
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output wire[3:0][31:0] data_out
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);
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`ifndef SYN
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reg[3:0][31:0] shared_memory[127:0];
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//reg[3:0][31:0] shared_memory[127:0];
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reg[SMB_WORDS_PER_READ-1:0][31:0] shared_memory[SMB_HEIGHT-1:0];
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//wire need_to_write = (|we);
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integer curr_ind;
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
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//for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
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for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1)
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begin
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shared_memory[curr_ind] <= 0;
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end
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end else if(shm_write) begin
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if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
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if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
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if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
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if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
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shared_memory[addr][we][31:0] <= wdata[we][31:0]; // - Ethan's addition
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//if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
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//if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
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//if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
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//if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
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end
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end
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assign data_out = shm_write ? 0 : shared_memory[addr];
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`else
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`else
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wire cena = 0;
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wire cenb = !shm_write;
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wire[3:0][31:0] write_bit_mask;
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//wire[3:0][31:0] write_bit_mask;
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assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}};
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assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}};
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assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}};
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assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}};
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integer curr_word;
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for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1)
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begin
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assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}};
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end
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// Using ASIC MEM
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/* verilator lint_off PINCONNECTEMPTY */
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