mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
More 64b fixes in ALU, Verilator exit code and ISA tests
This commit is contained in:
Shashank Holla
Blaise Tine
parent
5bdff46810
commit
7fc9ad3f66
5 changed files with 330 additions and 139 deletions
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@ -6,15 +6,160 @@ set -e
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# ensure build
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make -s
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unittest()
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{
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make -C tests/unittest run
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}
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coverage()
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{
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echo "begin coverage tests..."
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echo "begin coverage tests..."
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make -C sim/simx clean
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XLEN=64 make -C sim/simx
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XLEN=64 make -C tests/riscv/isa run-simx
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#make -C sim/simx clean
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#XLEN=64 make -C sim/simx
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#XLEN=64 make -C tests/runtime run-simx
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#XLEN=64 make -C tests/riscv/isa run-simx
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#XLEN=64 make -C tests/regression run-simx
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#XLEN=64 make -C tests/opencl run-simx
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#make -C . clean
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#XLEN=64 make -C .
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XLEN=64 make -C tests/riscv/isa run-rtlsim
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# XLEN=64 make -C tests/runtime run-rtlsim
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# XLEN=64 make -C tests/regression run-rtlsim
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echo "coverage tests done!"
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echo "coverage tests done!"
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}
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tex()
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{
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echo "begin texture tests..."
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CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=vlsim --app=tex --args="XLEN=64 -isoccer.png -osoccer_result.png -g0"
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CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=simx --app=tex --args="XLNE=64 -isoccer.png -osoccer_result.png -g0"
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CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=rtlsim --app=tex --args="XLEN=64 -itoad.png -otoad_result.png -g1"
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CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=simx --app=tex --args="XLEN=64 -irainbow.png -orainbow_result.png -g2"
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CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=rtlsim --app=tex --args="XLEN=64 -itoad.png -otoad_result.png -g1" --perf
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CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=simx --app=tex --args="XLEN=64 -itoad.png -otoad_result.png -g1" --perf
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echo "coverage texture done!"
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}
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cluster()
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{
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echo "begin clustering tests..."
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# warp/threads configurations
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./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo --args="XLEN=64"
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./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo --args="XLEN=64"
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./ci/blackbox.sh --driver=simx --cores=1 --warps=8 --threads=16 --app=demo --args="XLEN=64"
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# cores clustering
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./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=rtlsim --cores=4 --clusters=1 --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=1 --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --app=demo --args="XLEN=64 -n1"
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# L2/L3
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./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --l2cache --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=4 --l2cache --l3cache --app=demo --args="XLEN=64 -n1"
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echo "clustering tests done!"
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}
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debug()
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{
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echo "begin debugging tests..."
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./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --perf --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --perf --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --debug --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --debug --app=demo --args="XLEN=64 -n1"
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./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="XLEN=64 -t0 -n1"
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echo "debugging tests done!"
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}
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config()
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{
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echo "begin configuration tests..."
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# disabling M extension
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CONFIGS=-DEXT_M_DISABLE ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext --args="XLEN=64"
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# disabling F extension
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CONFIGS=-DEXT_F_DISABLE ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext --args="XLEN=64"
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CONFIGS=-DEXT_F_DISABLE ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext --perf --args="XLEN=64"
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CONFIGS=-DEXT_F_DISABLE ./ci/blackbox.sh --driver=simx --cores=1 --app=no_mf_ext --perf --args="XLEN=64"
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# disable shared memory
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CONFIGS=-DSM_ENABLE=0 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_smem --args="XLEN=64"
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CONFIGS=-DSM_ENABLE=0 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_smem --perf --args="XLEN=64"
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CONFIGS=-DSM_ENABLE=0 ./ci/blackbox.sh --driver=simx --cores=1 --app=no_smem --perf --args="XLEN=64"
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# using Default FPU core
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FPU_CORE=FPU_DEFAULT ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=dogfood --args="XLEN=64"
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# using FPNEW FPU core
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FPU_CORE=FPU_FPNEW ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=dogfood --args="XLEN=64"
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# using AXI bus
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AXI_BUS=1 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo --args="XLEN=64"
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# adjust l1 block size to match l2
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CONFIGS="-DL1_BLOCK_SIZE=64" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr --args="XLEN=64 -n1"
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# test cache banking
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CONFIGS="-DDNUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr --args="XLEN=64"
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CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr --args="XLEN=64"
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CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=simx --cores=1 --app=io_addr --args="XLEN=64"
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# test cache multi-porting
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CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr --args="XLEN=64"
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CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo --debug --args="XLEN=64 -n1"
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CONFIGS="-DL2_NUM_PORTS=2 -DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr --args="XLEN=64"
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CONFIGS="-DL2_NUM_PORTS=4 -DDNUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache --app=io_addr --args="XLEN=64"
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CONFIGS="-DL2_NUM_PORTS=4 -DDNUM_PORTS=4" ./ci/blackbox.sh --driver=simx --cores=4 --l2cache --app=io_addr --args="XLEN=64"
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# test 128-bit MEM block
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CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo --args="XLEN=64"
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# test single-bank DRAM
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CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo --args="XLEN=64"
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# test 27-bit DRAM address
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CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo --args="XLEN=64"
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echo "configuration tests done!"
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}
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stress0()
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{
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echo "begin stress0 tests..."
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# test verilator reset values
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CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm --args="XLEN=64"
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CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm --args="XLEN=64"
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FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood --args="XLEN=64"
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FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood --args="XLEN=64"
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CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="XLEN=64"
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CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="XLEN=64"
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CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --app=printf --args="XLEN=64"
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CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --app=printf --args="XLEN=64"
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echo "stress0 tests done!"
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}
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stress1()
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{
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echo "begin stress1 tests..."
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./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="XLEN=64 -n256"
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echo "stress1 tests done!"
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}
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show_usage()
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@ -25,8 +170,34 @@ show_usage()
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while [ "$1" != "" ]; do
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case $1 in
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# Passed
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-unittest ) unittest
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;;
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# Under dev
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-coverage ) coverage
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;;
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# Still failing
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-tex ) tex
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;;
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# Passed
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-cluster ) cluster
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;;
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# Passed
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-debug ) debug
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;;
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# Passed
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-config ) config
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;;
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# Passed
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-stress0 ) stress0
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;;
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# Passed
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-stress1 ) stress1
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;;
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# Passed
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-stress ) stress0
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stress1
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;;
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-all ) coverage
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;;
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-h | --help ) show_usage
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@ -36,4 +207,4 @@ while [ "$1" != "" ]; do
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exit 1
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esac
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shift
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done
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done
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@ -13,132 +13,143 @@
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default: `TRACE(level, ("?")); \
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endcase
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`define TRACE_EX_OP(level, ex_type, op_type, op_mod) \
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case (ex_type) \
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`EX_ALU: begin \
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if (`INST_ALU_IS_BR(op_mod)) begin \
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case (`INST_BR_BITS'(op_type)) \
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`INST_BR_EQ: `TRACE(level, ("BEQ")); \
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`INST_BR_NE: `TRACE(level, ("BNE")); \
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`INST_BR_LT: `TRACE(level, ("BLT")); \
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`INST_BR_GE: `TRACE(level, ("BGE")); \
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`INST_BR_LTU: `TRACE(level, ("BLTU")); \
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`INST_BR_GEU: `TRACE(level, ("BGEU")); \
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`INST_BR_JAL: `TRACE(level, ("JAL")); \
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`INST_BR_JALR: `TRACE(level, ("JALR")); \
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`INST_BR_ECALL: `TRACE(level, ("ECALL")); \
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`INST_BR_EBREAK:`TRACE(level, ("EBREAK")); \
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`INST_BR_URET: `TRACE(level, ("URET")); \
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`INST_BR_SRET: `TRACE(level, ("SRET")); \
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`INST_BR_MRET: `TRACE(level, ("MRET")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end else if (`INST_ALU_IS_MUL(op_mod)) begin \
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case (`INST_MUL_BITS'(op_type)) \
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`INST_MUL_MUL: `TRACE(level, ("MUL")); \
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`INST_MUL_MULH: `TRACE(level, ("MULH")); \
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`INST_MUL_MULHSU:`TRACE(level, ("MULHSU")); \
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`INST_MUL_MULHU: `TRACE(level, ("MULHU")); \
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`INST_MUL_DIV: `TRACE(level, ("DIV")); \
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`INST_MUL_DIVU: `TRACE(level, ("DIVU")); \
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`INST_MUL_REM: `TRACE(level, ("REM")); \
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`INST_MUL_REMU: `TRACE(level, ("REMU")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end else begin \
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case (`INST_ALU_BITS'(op_type)) \
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`INST_ALU_ADD: `TRACE(level, ("ADD")); \
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`INST_ALU_SUB: `TRACE(level, ("SUB")); \
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`INST_ALU_SLL: `TRACE(level, ("SLL")); \
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`INST_ALU_SRL: `TRACE(level, ("SRL")); \
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`INST_ALU_SRA: `TRACE(level, ("SRA")); \
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`INST_ALU_SLT: `TRACE(level, ("SLT")); \
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`INST_ALU_SLTU: `TRACE(level, ("SLTU")); \
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`INST_ALU_XOR: `TRACE(level, ("XOR")); \
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`INST_ALU_OR: `TRACE(level, ("OR")); \
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`INST_ALU_AND: `TRACE(level, ("AND")); \
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`INST_ALU_LUI: `TRACE(level, ("LUI")); \
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`INST_ALU_AUIPC: `TRACE(level, ("AUIPC")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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end \
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`EX_LSU: begin \
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if (op_mod == 0) begin \
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case (`INST_LSU_BITS'(op_type)) \
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`INST_LSU_LB: `TRACE(level, ("LB")); \
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`INST_LSU_LH: `TRACE(level, ("LH")); \
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`INST_LSU_LW: `TRACE(level, ("LW")); \
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`INST_LSU_LBU:`TRACE(level, ("LBU")); \
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`INST_LSU_LHU:`TRACE(level, ("LHU")); \
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`INST_LSU_SB: `TRACE(level, ("SB")); \
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`INST_LSU_SH: `TRACE(level, ("SH")); \
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`INST_LSU_SW: `TRACE(level, ("SW")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end else if (op_mod == 1) begin \
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case (`INST_FENCE_BITS'(op_type)) \
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`INST_FENCE_D: `TRACE(level, ("DFENCE")); \
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`INST_FENCE_I: `TRACE(level, ("IFENCE")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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end \
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`EX_CSR: begin \
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case (`INST_CSR_BITS'(op_type)) \
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`INST_CSR_RW: `TRACE(level, ("CSRW")); \
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`INST_CSR_RS: `TRACE(level, ("CSRS")); \
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`INST_CSR_RC: `TRACE(level, ("CSRC")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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`EX_FPU: begin \
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case (`INST_FPU_BITS'(op_type)) \
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`INST_FPU_ADD: `TRACE(level, ("ADD")); \
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`INST_FPU_SUB: `TRACE(level, ("SUB")); \
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`INST_FPU_MUL: `TRACE(level, ("MUL")); \
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`INST_FPU_DIV: `TRACE(level, ("DIV")); \
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`INST_FPU_SQRT: `TRACE(level, ("SQRT")); \
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`INST_FPU_MADD: `TRACE(level, ("MADD")); \
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`INST_FPU_NMSUB: `TRACE(level, ("NMSUB")); \
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`INST_FPU_NMADD: `TRACE(level, ("NMADD")); \
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`INST_FPU_CVTWS: `TRACE(level, ("CVTWS")); \
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`INST_FPU_CVTWUS:`TRACE(level, ("CVTWUS")); \
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`INST_FPU_CVTSW: `TRACE(level, ("CVTSW")); \
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`INST_FPU_CVTSWU:`TRACE(level, ("CVTSWU")); \
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`INST_FPU_CLASS: `TRACE(level, ("CLASS")); \
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`INST_FPU_CMP: `TRACE(level, ("CMP")); \
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`INST_FPU_MISC: begin \
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case (op_mod) \
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0: `TRACE(level, ("SGNJ")); \
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1: `TRACE(level, ("SGNJN")); \
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2: `TRACE(level, ("SGNJX")); \
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3: `TRACE(level, ("MIN")); \
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4: `TRACE(level, ("MAX")); \
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5: `TRACE(level, ("MVXW")); \
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6: `TRACE(level, ("MVWX")); \
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endcase \
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end \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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`EX_GPU: begin \
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case (`INST_GPU_BITS'(op_type)) \
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`INST_GPU_TMC: `TRACE(level, ("TMC")); \
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`INST_GPU_WSPAWN:`TRACE(level, ("WSPAWN")); \
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`INST_GPU_SPLIT: `TRACE(level, ("SPLIT")); \
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`INST_GPU_JOIN: `TRACE(level, ("JOIN")); \
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`INST_GPU_BAR: `TRACE(level, ("BAR")); \
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`INST_GPU_PRED: `TRACE(level, ("PRED")); \
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`INST_GPU_TEX: `TRACE(level, ("TEX")); \
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`INST_GPU_RASTER:`TRACE(level, ("RASTER")); \
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`INST_GPU_ROP: `TRACE(level, ("ROP")); \
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`INST_GPU_IMADD: `TRACE(level, ("IMADD")); \
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default: `TRACE(level, ("?")); \
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endcase \
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end \
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default: `TRACE(level, ("?")); \
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endcase
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task trace_ex_op (
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input int level,
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input [`EX_BITS-1:0] ex_type,
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input [`INST_OP_BITS-1:0] op_type,
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input [`INST_MOD_BITS-1:0] op_mod
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);
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case (ex_type)
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`EX_ALU: begin
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if (`INST_ALU_IS_BR(op_mod)) begin
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case (`INST_BR_BITS'(op_type))
|
||||
`INST_BR_EQ: `TRACE(level, ("BEQ"));
|
||||
`INST_BR_NE: `TRACE(level, ("BNE"));
|
||||
`INST_BR_LT: `TRACE(level, ("BLT"));
|
||||
`INST_BR_GE: `TRACE(level, ("BGE"));
|
||||
`INST_BR_LTU: `TRACE(level, ("BLTU"));
|
||||
`INST_BR_GEU: `TRACE(level, ("BGEU"));
|
||||
`INST_BR_JAL: `TRACE(level, ("JAL"));
|
||||
`INST_BR_JALR: `TRACE(level, ("JALR"));
|
||||
`INST_BR_ECALL: `TRACE(level, ("ECALL"));
|
||||
`INST_BR_EBREAK:`TRACE(level, ("EBREAK"));
|
||||
`INST_BR_URET: `TRACE(level, ("URET"));
|
||||
`INST_BR_SRET: `TRACE(level, ("SRET"));
|
||||
`INST_BR_MRET: `TRACE(level, ("MRET"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end else if (`INST_ALU_IS_MUL(op_mod)) begin
|
||||
case (`INST_MUL_BITS'(op_type))
|
||||
`INST_MUL_MUL: `TRACE(level, ("MUL"));
|
||||
`INST_MUL_MULH: `TRACE(level, ("MULH"));
|
||||
`INST_MUL_MULHSU:`TRACE(level, ("MULHSU"));
|
||||
`INST_MUL_MULHU: `TRACE(level, ("MULHU"));
|
||||
`INST_MUL_DIV: `TRACE(level, ("DIV"));
|
||||
`INST_MUL_DIVU: `TRACE(level, ("DIVU"));
|
||||
`INST_MUL_REM: `TRACE(level, ("REM"));
|
||||
`INST_MUL_REMU: `TRACE(level, ("REMU"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end else begin
|
||||
case (`INST_ALU_BITS'(op_type))
|
||||
`INST_ALU_ADD: `TRACE(level, ("ADD"));
|
||||
`INST_ALU_SUB: `TRACE(level, ("SUB"));
|
||||
`INST_ALU_SLL: `TRACE(level, ("SLL"));
|
||||
`INST_ALU_SRL: `TRACE(level, ("SRL"));
|
||||
`INST_ALU_SRA: `TRACE(level, ("SRA"));
|
||||
`INST_ALU_SLT: `TRACE(level, ("SLT"));
|
||||
`INST_ALU_SLTU: `TRACE(level, ("SLTU"));
|
||||
`INST_ALU_XOR: `TRACE(level, ("XOR"));
|
||||
`INST_ALU_OR: `TRACE(level, ("OR"));
|
||||
`INST_ALU_AND: `TRACE(level, ("AND"));
|
||||
`INST_ALU_LUI: `TRACE(level, ("LUI"));
|
||||
`INST_ALU_AUIPC: `TRACE(level, ("AUIPC"));
|
||||
`INST_ALU_ADD_W: `TRACE(level, ("ADD_W"));
|
||||
`INST_ALU_SUB_W: `TRACE(level, ("SUB_W"));
|
||||
`INST_ALU_SLL_W: `TRACE(level, ("SLL_W"));
|
||||
`INST_ALU_SRL_W: `TRACE(level, ("SRL_W"));
|
||||
`INST_ALU_SRA_W: `TRACE(level, ("SRA_W"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end
|
||||
end
|
||||
`EX_LSU: begin
|
||||
if (op_mod == 0) begin
|
||||
case (`INST_LSU_BITS'(op_type))
|
||||
`INST_LSU_LB: `TRACE(level, ("LB"));
|
||||
`INST_LSU_LH: `TRACE(level, ("LH"));
|
||||
`INST_LSU_LW: `TRACE(level, ("LW"));
|
||||
`INST_LSU_LBU:`TRACE(level, ("LBU"));
|
||||
`INST_LSU_LHU:`TRACE(level, ("LHU"));
|
||||
`INST_LSU_SB: `TRACE(level, ("SB"));
|
||||
`INST_LSU_SH: `TRACE(level, ("SH"));
|
||||
`INST_LSU_SW: `TRACE(level, ("SW"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end else if (op_mod == 1) begin
|
||||
case (`INST_FENCE_BITS'(op_type))
|
||||
`INST_FENCE_D: `TRACE(level, ("DFENCE"));
|
||||
`INST_FENCE_I: `TRACE(level, ("IFENCE"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end
|
||||
end
|
||||
`EX_CSR: begin
|
||||
case (`INST_CSR_BITS'(op_type))
|
||||
`INST_CSR_RW: `TRACE(level, ("CSRW"));
|
||||
`INST_CSR_RS: `TRACE(level, ("CSRS"));
|
||||
`INST_CSR_RC: `TRACE(level, ("CSRC"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end
|
||||
`EX_FPU: begin
|
||||
case (`INST_FPU_BITS'(op_type))
|
||||
`INST_FPU_ADD: `TRACE(level, ("ADD"));
|
||||
`INST_FPU_SUB: `TRACE(level, ("SUB"));
|
||||
`INST_FPU_MUL: `TRACE(level, ("MUL"));
|
||||
`INST_FPU_DIV: `TRACE(level, ("DIV"));
|
||||
`INST_FPU_SQRT: `TRACE(level, ("SQRT"));
|
||||
`INST_FPU_MADD: `TRACE(level, ("MADD"));
|
||||
`INST_FPU_NMSUB: `TRACE(level, ("NMSUB"));
|
||||
`INST_FPU_NMADD: `TRACE(level, ("NMADD"));
|
||||
`INST_FPU_CVTWS: `TRACE(level, ("CVTWS"));
|
||||
`INST_FPU_CVTWUS:`TRACE(level, ("CVTWUS"));
|
||||
`INST_FPU_CVTSW: `TRACE(level, ("CVTSW"));
|
||||
`INST_FPU_CVTSWU:`TRACE(level, ("CVTSWU"));
|
||||
`INST_FPU_CLASS: `TRACE(level, ("CLASS"));
|
||||
`INST_FPU_CMP: `TRACE(level, ("CMP"));
|
||||
`INST_FPU_MISC: begin
|
||||
case (op_mod)
|
||||
0: `TRACE(level, ("SGNJ"));
|
||||
1: `TRACE(level, ("SGNJN"));
|
||||
2: `TRACE(level, ("SGNJX"));
|
||||
3: `TRACE(level, ("MIN"));
|
||||
4: `TRACE(level, ("MAX"));
|
||||
5: `TRACE(level, ("MVXW"));
|
||||
6: `TRACE(level, ("MVWX"));
|
||||
endcase
|
||||
end
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end
|
||||
`EX_GPU: begin
|
||||
case (`INST_GPU_BITS'(op_type))
|
||||
`INST_GPU_TMC: `TRACE(level, ("TMC"));
|
||||
`INST_GPU_WSPAWN:`TRACE(level, ("WSPAWN"));
|
||||
`INST_GPU_SPLIT: `TRACE(level, ("SPLIT"));
|
||||
`INST_GPU_JOIN: `TRACE(level, ("JOIN"));
|
||||
`INST_GPU_BAR: `TRACE(level, ("BAR"));
|
||||
`INST_GPU_PRED: `TRACE(level, ("PRED"));
|
||||
`INST_GPU_TEX: `TRACE(level, ("TEX"));
|
||||
`INST_GPU_RASTER:`TRACE(level, ("RASTER"));
|
||||
`INST_GPU_ROP: `TRACE(level, ("ROP"));
|
||||
`INST_GPU_IMADD: `TRACE(level, ("IMADD"));
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
end
|
||||
default: `TRACE(level, ("?"));
|
||||
endcase
|
||||
endtask
|
||||
|
||||
`define TRACE_BASE_DCR(level, addr) \
|
||||
case (addr) \
|
||||
|
|
|
|||
|
|
@ -116,11 +116,15 @@ module Vortex (
|
|||
`endif
|
||||
|
||||
wire sim_ebreak /* verilator public */;
|
||||
wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value /* verilator public */;
|
||||
wire [`NUM_REGS-1:0][31:0] sim_wb_value /* verilator public */;
|
||||
wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak;
|
||||
wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_cluster_sim_wb_value;
|
||||
assign sim_ebreak = per_cluster_sim_ebreak[0];
|
||||
assign sim_wb_value = per_cluster_sim_wb_value[0];
|
||||
// assign sim_wb_value = per_cluster_sim_wb_value[0];
|
||||
|
||||
for (genvar i = 0; i < `NUM_REGS; ++i) begin
|
||||
assign sim_wb_value[i] = per_cluster_sim_wb_value[0][i][31:0];
|
||||
end
|
||||
`UNUSED_VAR (per_cluster_sim_ebreak)
|
||||
`UNUSED_VAR (per_cluster_sim_wb_value)
|
||||
|
||||
|
|
|
|||
|
|
@ -130,10 +130,10 @@ module VX_alu_unit #(
|
|||
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_jal_result = is_jal ? {`NUM_THREADS{`XLEN'(alu_req_if.next_PC)}} : alu_result;
|
||||
|
||||
wire [`XLEN-1:0] br_dest = add_result[alu_req_if.tid][`XLEN-1:0];
|
||||
wire [32:0] cmp_result = sub_result[alu_req_if.tid][32:0];
|
||||
wire [`XLEN:0] cmp_result = sub_result[alu_req_if.tid][`XLEN:0];
|
||||
|
||||
wire is_less = cmp_result[32];
|
||||
wire is_equal = ~(| cmp_result[31:0]);
|
||||
wire is_less = cmp_result[`XLEN];
|
||||
wire is_equal = ~(| cmp_result[`XLEN-1:0]);
|
||||
|
||||
// output
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
XLEN ?= 32
|
||||
XLEN ?= 64
|
||||
|
||||
SIM_DIR=../../../sim
|
||||
|
||||
|
|
@ -44,7 +44,12 @@ run-simx-64: run-simx-32imfd run-simx-64imfd
|
|||
|
||||
run-simx: run-simx-$(XLEN)
|
||||
|
||||
run-rtlsim:
|
||||
run-rtlsim-32:
|
||||
$(foreach test, $(TESTS_32I) $(TESTS_32M) $(TESTS_32F), $(SIM_DIR)/rtlsim/rtlsim -r $(test) || exit;)
|
||||
|
||||
run-rtlsim-64:
|
||||
$(foreach test, $(TESTS_64I) $(TESTS_64M) $(TESTS_64F), $(SIM_DIR)/rtlsim/rtlsim -r $(test) || exit;)
|
||||
|
||||
run-rtlsim: run-rtlsim-$(XLEN)
|
||||
|
||||
clean:
|
||||
Loading…
Add table
Add a link
Reference in a new issue