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minor update

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This commit is contained in:
Blaise Tine 2021-07-20 21:23:31 -07:00
parent aa7b0da877
commit 8048796102
9 changed files with 81 additions and 81 deletions
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30
hw/rtl/VX_core.v
View file

@ -32,14 +32,14 @@ module VX_core #(
`endif
VX_mem_req_if #(
.MEM_LINE_WIDTH(`DMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH(`DMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH(`XMEM_TAG_WIDTH)
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_WIDTH (`XMEM_TAG_WIDTH)
) mem_req_if();
VX_mem_rsp_if #(
.MEM_LINE_WIDTH(`DMEM_LINE_WIDTH),
.MEM_TAG_WIDTH(`XMEM_TAG_WIDTH)
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.TAG_WIDTH (`XMEM_TAG_WIDTH)
) mem_rsp_if();
assign mem_req_valid = mem_req_if.valid;
@ -58,25 +58,25 @@ module VX_core #(
//--
VX_dcache_req_if #(
.NUM_REQS(`DNUM_REQS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_req_if();
VX_dcache_rsp_if #(
.NUM_REQS(`DNUM_REQS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_rsp_if();
VX_icache_req_if #(
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
.WORD_SIZE (`IWORD_SIZE),
.TAG_WIDTH (`ICORE_TAG_WIDTH)
) icache_req_if();
VX_icache_rsp_if #(
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
.WORD_SIZE (`IWORD_SIZE),
.TAG_WIDTH (`ICORE_TAG_WIDTH)
) icache_rsp_if();
VX_pipeline #(

44
hw/rtl/VX_mem_unit.v
View file

@ -30,37 +30,37 @@ module VX_mem_unit # (
`endif
VX_mem_req_if #(
.MEM_LINE_WIDTH (`IMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH (`IMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH (`IMEM_TAG_WIDTH)
.LINE_WIDTH (`IMEM_LINE_WIDTH),
.ADDR_WIDTH (`IMEM_ADDR_WIDTH),
.TAG_WIDTH (`IMEM_TAG_WIDTH)
) icache_mem_req_if();
VX_mem_rsp_if #(
.MEM_LINE_WIDTH (`IMEM_LINE_WIDTH),
.MEM_TAG_WIDTH (`IMEM_TAG_WIDTH)
.LINE_WIDTH (`IMEM_LINE_WIDTH),
.TAG_WIDTH (`IMEM_TAG_WIDTH)
) icache_mem_rsp_if();
VX_mem_req_if #(
.MEM_LINE_WIDTH (`DMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH)
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_WIDTH (`DMEM_TAG_WIDTH)
) dcache_mem_req_if();
VX_mem_rsp_if #(
.MEM_LINE_WIDTH (`DMEM_LINE_WIDTH),
.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH)
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.TAG_WIDTH (`DMEM_TAG_WIDTH)
) dcache_mem_rsp_if();
VX_dcache_req_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_req_tmp_if();
VX_dcache_rsp_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_rsp_tmp_if();
`RESET_RELAY (icache_reset);
@ -186,15 +186,15 @@ module VX_mem_unit # (
if (`SM_ENABLE) begin
VX_dcache_req_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) smem_req_if();
VX_dcache_rsp_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) smem_rsp_if();
VX_smem_arb smem_arb (

20
hw/rtl/VX_pipeline.v
View file

@ -49,9 +49,9 @@ module VX_pipeline #(
//
VX_dcache_req_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_req_if();
assign dcache_req_valid = dcache_req_if.valid;
@ -67,9 +67,9 @@ module VX_pipeline #(
//
VX_dcache_rsp_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_rsp_if();
assign dcache_rsp_if.valid = dcache_rsp_valid;
@ -83,8 +83,8 @@ module VX_pipeline #(
//
VX_icache_req_if #(
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
.WORD_SIZE (4),
.TAG_WIDTH (`ICORE_TAG_WIDTH)
) icache_req_if();
assign icache_req_valid = icache_req_if.valid;
@ -97,8 +97,8 @@ module VX_pipeline #(
//
VX_icache_rsp_if #(
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
.WORD_SIZE (4),
.TAG_WIDTH (`ICORE_TAG_WIDTH)
) icache_rsp_if();
assign icache_rsp_if.valid = icache_rsp_valid;

8
hw/rtl/interfaces/VX_dcache_req_if.v
View file

@ -4,9 +4,9 @@
`include "../cache/VX_cache_define.vh"
interface VX_dcache_req_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;
@ -14,7 +14,7 @@ interface VX_dcache_req_if #(
wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen;
wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
endinterface

8
hw/rtl/interfaces/VX_dcache_rsp_if.v
View file

@ -4,15 +4,15 @@
`include "../cache/VX_cache_define.vh"
interface VX_dcache_rsp_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [NUM_REQS-1:0] tmask;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [CORE_TAG_WIDTH-1:0] tag;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

6
hw/rtl/interfaces/VX_icache_req_if.v
View file

@ -4,13 +4,13 @@
`include "../cache/VX_cache_define.vh"
interface VX_icache_req_if #(
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`WORD_ADDR_WIDTH-1:0] addr;
wire [CORE_TAG_WIDTH-1:0] tag;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

12
hw/rtl/interfaces/VX_icache_rsp_if.v
View file

@ -4,14 +4,14 @@
`include "../cache/VX_cache_define.vh"
interface VX_icache_rsp_if #(
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`WORD_WIDTH-1:0] data;
wire [CORE_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire [`WORD_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

22
hw/rtl/interfaces/VX_mem_req_if.v
View file

@ -4,19 +4,19 @@
`include "../cache/VX_cache_define.vh"
interface VX_mem_req_if #(
parameter MEM_LINE_WIDTH = 1,
parameter MEM_ADDR_WIDTH = 1,
parameter MEM_TAG_WIDTH = 1,
parameter MEM_LINE_SIZE = MEM_LINE_WIDTH / 8
parameter LINE_WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter LINE_SIZE = LINE_WIDTH / 8
) ();
wire valid;
wire rw;
wire [MEM_LINE_SIZE-1:0] byteen;
wire [MEM_ADDR_WIDTH-1:0] addr;
wire [MEM_LINE_WIDTH-1:0] data;
wire [MEM_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire rw;
wire [LINE_SIZE-1:0] byteen;
wire [ADDR_WIDTH-1:0] addr;
wire [LINE_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

12
hw/rtl/interfaces/VX_mem_rsp_if.v
View file

@ -4,14 +4,14 @@
`include "../cache/VX_cache_define.vh"
interface VX_mem_rsp_if #(
parameter MEM_LINE_WIDTH = 1,
parameter MEM_TAG_WIDTH = 1
parameter LINE_WIDTH = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [MEM_LINE_WIDTH-1:0] data;
wire [MEM_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire [LINE_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface