mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
Support exec multi-cycle for div/mul
This commit is contained in:
wgulian3
parent
c1bd731d7f
commit
8318aff69f
8 changed files with 100 additions and 58 deletions
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@ -3,7 +3,7 @@ all: RUNFILE
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# /rf2_256x128_wm1/
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BaseMEM=../models/memory/cln28hpm
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INCLUDE=-I. -Ishared_memory -Icache -I$(BaseMEM)/rf2_128x128_wm1/ -I$(BaseMEM)/rf2_256x128_wm1/ -I$(BaseMEM)/rf2_256x19_wm0/ -I$(BaseMEM)/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ -Isimulate
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INCLUDE=-I. -Ishared_memory -Icache -I$(BaseMEM)/rf2_128x128_wm1/ -I$(BaseMEM)/rf2_256x128_wm1/ -I$(BaseMEM)/rf2_256x19_wm0/ -I$(BaseMEM)/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
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FILE=Vortex.v
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@ -49,4 +49,4 @@ w: VERILATORnoWarnings
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$(MAKECPP)
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clean:
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rm obj_dir/*
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rm obj_dir/*
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42
rtl/VX_alu.v
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rtl/VX_alu.v
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@ -1,6 +1,8 @@
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`include "VX_define.v"
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module VX_alu(
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input wire clk,
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input wire reset,
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input wire[31:0] in_1,
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input wire[31:0] in_2,
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input wire in_rs2_src,
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@ -8,9 +10,11 @@ module VX_alu(
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input wire[19:0] in_upper_immed,
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input wire[4:0] in_alu_op,
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input wire[31:0] in_curr_PC,
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output reg[31:0] out_alu_result
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output reg[31:0] out_alu_result,
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output reg out_alu_stall
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);
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localparam div_pipeline_len = 3;
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`ifdef SYN_FUNC
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wire which_in2;
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@ -25,23 +29,25 @@ module VX_alu(
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wire[31:0] signed_div_result;
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wire[31:0] signed_rem_result;
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reg [15:0] inst_delay;
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reg [15:0] inst_delay_count;
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assign out_alu_stall = inst_delay != 0 || inst_delay_count != 0;
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assign which_in2 = in_rs2_src == `RS2_IMMED;
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assign ALU_in1 = in_1;
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assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
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assign upper_immed = {in_upper_immed, {12{1'b0}}};
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.SPEED("HIGHEST"),
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.PIPELINE(0)
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.PIPELINE(div_pipeline_len)
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) unsigned_div (
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.clk(0),
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.clock(clk),
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.aclr(0),
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.clken(1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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@ -56,9 +62,9 @@ module VX_alu(
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.NREP("SIGNED"),
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.DREP("SIGNED"),
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.SPEED("HIGHEST"),
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.PIPELINE(0)
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.PIPELINE(div_pipeline_len)
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) signed_div (
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.clk(0),
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.clock(clk),
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.aclr(0),
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.clken(1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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@ -101,6 +107,7 @@ module VX_alu(
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`MULH: out_alu_result = mult_result[63:32];
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`MULHSU: out_alu_result = mult_result[63:32];
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`MULHU: out_alu_result = mult_result[63:32];
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// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
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`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
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`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
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`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
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@ -109,6 +116,25 @@ module VX_alu(
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endcase // in_alu_op
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end
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always @(*) begin
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case(in_alu_op)
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`DIV,
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`DIVU,
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`REM,
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`REMU: inst_delay = div_pipeline_len;
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default: inst_delay = 0;
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endcase // in_alu_op
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end
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always @(posedge clk or posedge reset) begin
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if (reset)
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inst_delay_count <= 0;
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else if (inst_delay_count > 0)
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inst_delay_count <= inst_delay_count - 1;
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else if (inst_delay != 0)
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inst_delay_count <= inst_delay - 1;
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end
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`else
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wire which_in2;
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@ -169,4 +195,4 @@ module VX_alu(
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end
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`endif
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endmodule
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endmodule : VX_alu
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@ -6,6 +6,7 @@ module VX_back_end (
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input wire schedule_delay,
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output wire out_mem_delay,
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output wire out_exec_delay,
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output wire gpr_stage_delay,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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@ -32,7 +33,7 @@ assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
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VX_mw_wb_inter VX_mw_wb();
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wire no_slot_mem;
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wire no_slot_mem, no_slot_exec;
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VX_mem_req_inter VX_exe_mem_req();
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@ -69,6 +70,7 @@ VX_gpr_stage VX_gpr_stage(
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.VX_csr_req (VX_csr_req),
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// End new
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.memory_delay (out_mem_delay),
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.exec_delay (out_exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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@ -91,7 +93,9 @@ VX_execute_unit VX_execUnit(
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp)
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.VX_branch_rsp (VX_branch_rsp),
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.out_delay (out_exec_delay),
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.no_slot_exec (no_slot_exec)
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);
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@ -113,7 +117,8 @@ VX_writeback VX_wb(
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.VX_csr_wb (VX_csr_wb),
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.VX_writeback_inter(VX_writeback_temp),
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.no_slot_mem (no_slot_mem)
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.no_slot_mem (no_slot_mem),
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.no_slot_exec (no_slot_exec)
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);
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endmodule
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@ -12,7 +12,10 @@ module VX_execute_unit (
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// JAL Response
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VX_jal_response_inter VX_jal_rsp,
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// Branch Response
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VX_branch_response_inter VX_branch_rsp
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VX_branch_response_inter VX_branch_rsp,
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input wire no_slot_exec,
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output wire out_delay
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);
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@ -41,10 +44,13 @@ module VX_execute_unit (
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wire[`NT_M1:0][31:0] alu_result;
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wire[`NT_M1:0] alu_stall;
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genvar index_out_reg;
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generate
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for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin : alu_defs
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VX_alu vx_alu(
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.clk(clk),
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.reset(reset),
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// .in_reg_data (in_reg_data[1:0]),
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.in_1 (in_a_reg_data[index_out_reg]),
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.in_2 (in_b_reg_data[index_out_reg]),
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@ -53,11 +59,17 @@ module VX_execute_unit (
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.in_upper_immed(in_upper_immed),
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.in_alu_op (in_alu_op),
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.in_curr_PC (in_curr_PC),
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.out_alu_result(alu_result[index_out_reg])
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.out_alu_result(alu_result[index_out_reg]),
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.out_alu_stall(alu_stall[index_out_reg])
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);
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end
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endgenerate
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wire internal_stall;
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assign internal_stall = |alu_stall;
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assign out_delay = no_slot_exec || internal_stall;
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wire [$clog2(`NT)-1:0] jal_branch_use_index;
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wire jal_branch_found_valid;
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@ -103,7 +115,7 @@ module VX_execute_unit (
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// Actual Writeback
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assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
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assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid && !internal_stall;
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assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num;
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assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result;
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@ -163,4 +175,4 @@ module VX_execute_unit (
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// assign out_is_csr = VX_exec_unit_req.is_csr;
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// assign out_csr_address = VX_exec_unit_req.csr_address;
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endmodule
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endmodule : VX_execute_unit
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@ -7,6 +7,7 @@ module VX_gpr_stage (
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input wire schedule_delay,
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input wire memory_delay,
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input wire exec_delay,
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output wire gpr_stage_delay,
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// inputs
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@ -93,7 +94,10 @@ module VX_gpr_stage (
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wire stall_lsu = memory_delay;
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wire flush_lsu = schedule_delay && !stall_lsu;
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assign gpr_stage_delay = stall_lsu;
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wire stall_exec = exec_delay;
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wire flush_exec = schedule_delay && !stall_exec;
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assign gpr_stage_delay = stall_lsu || stall_exec;
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`ifdef ASIC
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wire delayed_lsu_last_cycle;
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@ -145,8 +149,8 @@ module VX_gpr_stage (
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VX_generic_register #(.N(224 + `NW_M1 + 1 + (`NT))) exec_unit_reg(
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.clk (clk),
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.reset(reset),
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.stall(stall_rest),
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.flush(flush_rest),
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.stall(stall_exec),
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.flush(flush_exec),
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.in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}),
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.out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask })
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);
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@ -193,8 +197,8 @@ module VX_gpr_stage (
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VX_generic_register #(.N(224 + `NW_M1 + 1 + 65*(`NT))) exec_unit_reg(
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.clk (clk),
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.reset(reset),
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.stall(stall_rest),
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.flush(flush_rest),
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.stall(stall_exec),
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.flush(flush_exec),
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.in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.a_reg_data, VX_exec_unit_req_temp.b_reg_data, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}),
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.out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.a_reg_data , VX_exec_unit_req.b_reg_data , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask })
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);
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@ -219,4 +223,4 @@ module VX_gpr_stage (
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`endif
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endmodule
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endmodule : VX_gpr_stage
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@ -6,6 +6,7 @@ module VX_scheduler (
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input wire clk,
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input wire reset,
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input wire memory_delay,
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input wire exec_delay,
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input wire gpr_stage_delay,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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VX_wb_inter VX_writeback_inter,
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@ -27,7 +28,11 @@ module VX_scheduler (
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wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE);
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wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ);
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// classify our next instruction.
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wire is_mem = is_store || is_load;
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wire is_gpu = (VX_bckE_req.is_wspawn || VX_bckE_req.is_tmc || VX_bckE_req.is_barrier || VX_bckE_req.is_split);
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wire is_csr = VX_bckE_req.is_csr;
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wire is_exec = !is_mem && !is_gpu && !is_csr;
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wire rs1_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs1)));
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@ -44,8 +49,10 @@ module VX_scheduler (
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wire rename_valid = rs1_rename_qual || rs2_rename_qual ;
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assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) || (memory_delay && (is_mem)) || (gpr_stage_delay && is_mem);
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assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid))
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|| (memory_delay && is_mem)
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|| (gpr_stage_delay && (is_mem || is_exec))
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|| (exec_delay && is_exec);
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integer i;
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integer w;
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@ -14,10 +14,10 @@ module VX_writeback (
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// Actual WB to GPR
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VX_wb_inter VX_writeback_inter,
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output wire no_slot_mem
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output wire no_slot_mem,
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output wire no_slot_exec
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);
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VX_wb_inter VX_writeback_tempp();
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wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
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@ -25,38 +25,39 @@ module VX_writeback (
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wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid);
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assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
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assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
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assign no_slot_exec = exec_wb && (csr_wb);
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assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
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csr_wb ? VX_csr_wb.csr_result :
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assign VX_writeback_tempp.write_data = csr_wb ? VX_csr_wb.csr_result :
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exec_wb ? VX_inst_exec_wb.alu_result :
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mem_wb ? VX_mem_wb.loaded_data :
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0;
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assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid :
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csr_wb ? VX_csr_wb.valid :
|
||||
assign VX_writeback_tempp.wb_valid = csr_wb ? VX_csr_wb.valid :
|
||||
exec_wb ? VX_inst_exec_wb.wb_valid :
|
||||
mem_wb ? VX_mem_wb.wb_valid :
|
||||
0;
|
||||
|
||||
assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd :
|
||||
csr_wb ? VX_csr_wb.rd :
|
||||
assign VX_writeback_tempp.rd = csr_wb ? VX_csr_wb.rd :
|
||||
exec_wb ? VX_inst_exec_wb.rd :
|
||||
mem_wb ? VX_mem_wb.rd :
|
||||
0;
|
||||
|
||||
assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb :
|
||||
csr_wb ? VX_csr_wb.wb :
|
||||
assign VX_writeback_tempp.wb = csr_wb ? VX_csr_wb.wb :
|
||||
exec_wb ? VX_inst_exec_wb.wb :
|
||||
mem_wb ? VX_mem_wb.wb :
|
||||
0;
|
||||
|
||||
assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
|
||||
csr_wb ? VX_csr_wb.warp_num :
|
||||
assign VX_writeback_tempp.wb_warp_num = csr_wb ? VX_csr_wb.warp_num :
|
||||
exec_wb ? VX_inst_exec_wb.wb_warp_num :
|
||||
mem_wb ? VX_mem_wb.wb_warp_num :
|
||||
0;
|
||||
|
||||
|
||||
|
||||
assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc :
|
||||
csr_wb ? 32'hdeadbeef :
|
||||
assign VX_writeback_tempp.wb_pc = csr_wb ? 32'hdeadbeef :
|
||||
exec_wb ? VX_inst_exec_wb.exec_wb_pc :
|
||||
mem_wb ? VX_mem_wb.mem_wb_pc :
|
||||
32'hdeadbeef;
|
||||
|
||||
|
|
@ -65,17 +66,6 @@ module VX_writeback (
|
|||
|
||||
wire[`NT-1:0][31:0] use_wb_data;
|
||||
|
||||
reg prev_is_mem;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
prev_is_mem = 0;
|
||||
end begin
|
||||
prev_is_mem = mem_wb && !no_slot_mem;
|
||||
end
|
||||
end
|
||||
|
||||
VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register(
|
||||
.clk (clk),
|
||||
.reset(reset),
|
||||
|
|
@ -85,14 +75,9 @@ module VX_writeback (
|
|||
.out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
|
||||
);
|
||||
|
||||
`ifdef SYN
|
||||
assign VX_writeback_inter.write_data = prev_is_mem ? VX_writeback_tempp.write_data : use_wb_data;
|
||||
`else
|
||||
assign VX_writeback_inter.write_data = use_wb_data;
|
||||
`endif
|
||||
assign VX_writeback_inter.write_data = use_wb_data;
|
||||
|
||||
|
||||
endmodule // VX_writeback
|
||||
endmodule : VX_writeback // VX_writeback
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ module Vortex
|
|||
|
||||
|
||||
wire memory_delay;
|
||||
wire exec_delay;
|
||||
wire gpr_stage_delay;
|
||||
wire schedule_delay;
|
||||
|
||||
|
|
@ -179,6 +180,7 @@ VX_scheduler schedule(
|
|||
.clk (clk),
|
||||
.reset (reset),
|
||||
.memory_delay (memory_delay),
|
||||
.exec_delay (exec_delay),
|
||||
.gpr_stage_delay (gpr_stage_delay),
|
||||
.VX_bckE_req (VX_bckE_req),
|
||||
.VX_writeback_inter(VX_writeback_inter),
|
||||
|
|
@ -197,6 +199,7 @@ VX_back_end vx_back_end(
|
|||
.VX_dcache_req (VX_dcache_req),
|
||||
.VX_writeback_inter (VX_writeback_inter),
|
||||
.out_mem_delay (memory_delay),
|
||||
.out_exec_delay (exec_delay),
|
||||
.gpr_stage_delay (gpr_stage_delay)
|
||||
);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue