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minor update
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This commit is contained in:
tinebp
parent
347889c504
commit
83ba1cc3dc
2 changed files with 188 additions and 122 deletions
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@ -31,10 +31,10 @@
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`RAM_INITIALIZATION \
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reg [ADDRW-1:0] raddr_r; \
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always @(posedge clk) begin \
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if (__re || __we) begin \
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if (__we) begin \
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ram[__wa] <= wdata; \
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end \
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if (__we) begin \
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ram[__wa] <= wdata; \
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end \
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if (__re) begin \
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raddr_r <= __ra; \
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end \
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end \
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@ -45,14 +45,14 @@
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`RAM_INITIALIZATION \
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reg [ADDRW-1:0] raddr_r; \
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always @(posedge clk) begin \
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if (__re || __we) begin \
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if (__we) begin \
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for (integer i = 0; i < WRENW; ++i) begin \
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if (wren[i]) begin \
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ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
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end \
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if (__we) begin \
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for (integer i = 0; i < WRENW; ++i) begin \
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if (wren[i]) begin \
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ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
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end \
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end \
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end \
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if (__re) begin \
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raddr_r <= __ra; \
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end \
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end \
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@ -63,10 +63,10 @@
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`RAM_INITIALIZATION \
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reg [DATAW-1:0] rdata_r; \
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always @(posedge clk) begin \
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if (__re || __we) begin \
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if (__we) begin \
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ram[__wa] <= wdata; \
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end \
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if (__we) begin \
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ram[__wa] <= wdata; \
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end \
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if (__re) begin \
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rdata_r <= ram[__ra]; \
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end \
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end \
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@ -77,14 +77,14 @@
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`RAM_INITIALIZATION \
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reg [DATAW-1:0] rdata_r; \
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always @(posedge clk) begin \
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if (__re || __we) begin \
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if (__we) begin \
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for (integer i = 0; i < WRENW; ++i) begin \
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if (wren[i]) begin \
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ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
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end \
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if (__we) begin \
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for (integer i = 0; i < WRENW; ++i) begin \
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if (wren[i]) begin \
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ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
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end \
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end \
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end \
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if (__re) begin \
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rdata_r <= ram[__ra]; \
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end \
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end \
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@ -122,6 +122,7 @@ module VX_async_ram_patch #(
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parameter DUAL_PORT = 0,
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parameter FORCE_BRAM = 0,
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parameter RADDR_REG = 0, // read address registered hint
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parameter RADDR_RESET = 0, // read address has reset
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parameter WRITE_FIRST = 0,
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parameter INIT_ENABLE = 0,
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parameter INIT_FILE = "",
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@ -143,16 +144,24 @@ module VX_async_ram_patch #(
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`UNUSED_VAR (reset)
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(* keep = "true" *) wire [ADDRW-1:0] raddr_w, raddr_s;
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(* keep = "true" *) wire read_s, is_raddr_reg;
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(* keep = "true" *) wire read_s;
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assign raddr_w = raddr;
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wire raddr_reset_w;
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if (RADDR_RESET) begin : g_raddr_reset
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(* keep = "true" *) wire raddr_reset;
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assign raddr_reset = 0;
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assign raddr_reset_w = raddr_reset;
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end else begin : g_no_raddr_reset
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assign raddr_reset_w = 0;
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end
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VX_placeholder #(
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.I (ADDRW),
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.O (ADDRW + 1 + 1)
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) placeholder (
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.in (raddr_w),
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.out ({raddr_s, read_s, is_raddr_reg})
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.I (ADDRW + 1),
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.O (ADDRW + 1)
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) placeholder1 (
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.in ({raddr_w, raddr_reset_w}),
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.out ({raddr_s, read_s})
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);
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wire [DATAW-1:0] rdata_s;
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@ -206,9 +215,15 @@ module VX_async_ram_patch #(
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end
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if (RADDR_REG) begin : g_raddr_reg
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`UNUSED_VAR (is_raddr_reg)
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assign rdata = rdata_s;
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end else begin : g_async_ram
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(* keep = "true" *) wire is_raddr_reg;
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VX_placeholder #(
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.O (1)
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) placeholder2 (
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.in (),
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.out (is_raddr_reg)
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);
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wire [DATAW-1:0] rdata_a;
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if (DUAL_PORT) begin : g_dp
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if (WRENW != 1) begin : g_wren
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@ -13,7 +13,6 @@
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namespace eval vortex {
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variable info 0
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variable debug 0
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proc print_error {msg {do_exit 1}} {
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@ -21,7 +20,8 @@ proc print_error {msg {do_exit 1}} {
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puts "ERROR: $msg"
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exit -1
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} else {
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puts "WARNING: $msg"
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variable debug
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if {$debug} {puts "WARNING: $msg"}
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}
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}
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@ -132,6 +132,17 @@ proc find_cell_nets {cell name_match {should_exist 1}} {
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return $matching_nets
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}
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proc find_cell_net {cell name_match {should_exist 1}} {
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set nets [find_cell_nets $cell $name_match $should_exist]
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if {[llength $nets] == 0} {
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return ""
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} elseif {[llength $nets] > 1} {
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puts "ERROR: Multiple matching nets found for '$cell' matching '$name_match'."
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exit -1
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}
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return [lindex $nets 0]
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}
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proc get_cell_net {cell name} {
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set net [get_nets -hierarchical -filter "PARENT_CELL == $cell && NAME == $name"]
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if {[llength $net] == 0} {
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@ -168,88 +179,52 @@ proc get_cell_pin {cell name} {
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}
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proc remove_cell_from_netlist {cell} {
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variable info
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variable debug
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# Disconnect all pins of the cell
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foreach pin [get_pins -quiet -of_objects $cell] {
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foreach net [get_nets -quiet -of_objects $pin] {
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disconnect_net -net $net -objects $pin
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if {$info} {puts "INFO: Disconnected net '$net' from pin '$pin'."}
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if {$debug} {puts "DEBUG: Disconnected net '$net' from pin '$pin'."}
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}
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}
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# Remove the cell
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remove_cell $cell
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if {$info} {puts "INFO: Cell '$cell' was removed successfully."}
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if {$debug} {puts "DEBUG: Cell '$cell' was removed successfully."}
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}
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proc replace_pin_source {pin source_pin} {
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variable debug
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# Disconnect existing net from pin
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set net [get_nets -of_objects $pin]
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if {[llength $net] == 1} {
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disconnect_net -net $net -objects $pin
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if {$debug} {puts "DEBUG: Disconnected net '$net' from pin '$pin'."}
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} elseif {[llength $net] > 1} {
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puts "ERROR: Multiple nets connected to pin '$pin'."
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exit -1
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} else {
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puts "WARNING: No net connected to pin '$pin'."
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}
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set source_net [get_nets -quiet -of_objects $source_pin]
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if {[llength $source_net] == 0} {
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# Create a new net if none exists
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set source_cell [get_cells -of_objects $source_pin]
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set net_name [unique_net_name "${source_cell}_net"]
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set source_net [create_net $net_name]
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if {$debug} {puts "DEBUG: Created source_net: '$source_net'"}
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# Connect the source pin to the new net
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connect_net -net $source_net -objects $source_pin -hierarchical
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if {$debug} {puts "DEBUG: Connected net '$source_net' to pin '$source_pin'."}
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} elseif {[llength $source_net] > 1} {
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puts "ERROR: Multiple nets connected to pin '$source_pin'."
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exit -1
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}
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# Connect pin to the new source net
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connect_net -net $source_net -objects $pin -hierarchical
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if {$debug} {puts "DEBUG: Connected net '$source_net' to pin '$pin'."}
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}
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proc find_net_driver {input_net {should_exist 1}} {
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set driverPins [get_pins -quiet -leaf -of_objects $input_net -filter {DIRECTION == "OUT"}]
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proc find_net_driver {taregt_net {should_exist 1}} {
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set driverPins [get_pins -quiet -leaf -of_objects $taregt_net -filter {DIRECTION == "OUT"}]
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if {[llength $driverPins] == 0} {
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set driverPorts [get_ports -quiet -of_objects $input_net -filter {DIRECTION == "IN"}]
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set driverPorts [get_ports -quiet -of_objects $taregt_net -filter {DIRECTION == "IN"}]
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if {[llength $driverPorts] == 0} {
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print_error "No driver found for '$input_net'." $should_exist
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print_error "No driver found for '$taregt_net'." $should_exist
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} elseif {[llength $driverPorts] > 1} {
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puts "WARNING: Multiple driver ports found for '$input_net'."
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puts "WARNING: Multiple driver ports found for '$taregt_net'."
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return [lindex $driverPorts 0]
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}
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return $driverPorts
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} elseif {[llength $driverPins] > 1} {
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puts "WARNING: Multiple driver pins found for '$input_net'."
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puts "WARNING: Multiple driver pins found for '$taregt_net'."
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return [lindex $driverPins 0]
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}
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return $driverPins
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}
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proc find_pin_driver {input_pin {should_exist 1}} {
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set net [get_nets -quiet -of_objects $input_pin]
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proc find_pin_driver {target_pin {should_exist 1}} {
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set net [get_nets -quiet -of_objects $target_pin]
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if {[llength $net] == 0} {
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print_error "No net connected to pin '$input_pin'." $should_exist
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print_error "No net connected to pin '$target_pin'." $should_exist
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return ""
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} elseif {[llength $net] > 1} {
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puts "ERROR: Multiple nets connected to pin '$input_pin'."
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puts "ERROR: Multiple nets connected to pin '$target_pin'."
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exit -1
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}
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return [find_net_driver $net]
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}
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proc create_register_next {parent reg_cell} {
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variable info
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proc create_register_next {parent reg_cell raddr_reset} {
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variable debug
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set hier_sep [get_hierarchy_separator]
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@ -273,6 +248,10 @@ proc create_register_next {parent reg_cell} {
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if {$debug} {puts "DEBUG: reg_d_src_pin: '$reg_d_src_pin'"}
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if {$raddr_reset == ""} {
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return $reg_d_src_pin
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}
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set reg_r_src_pin ""
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set register_type [get_property REF_NAME $reg_cell]
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@ -341,7 +320,7 @@ proc create_register_next {parent reg_cell} {
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# FDSE: O = I1 ? 1 : I0; where I0=D, I1=S
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set lut_name [unique_cell_name "${parent}${hier_sep}raddr_next"]
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set lut_cell [create_cell -reference LUT2 $lut_name]
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if {$info} {puts "INFO: Created lut cell: '$lut_cell'"}
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if {$debug} {puts "DEBUG: Created lut cell: '$lut_cell'"}
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if {$register_type == "FDRE"} {
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set_property INIT 4'b0010 $lut_cell
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@ -389,7 +368,6 @@ proc create_register_next {parent reg_cell} {
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}
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proc getOrCreateVCCPin {parent} {
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variable info
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variable debug
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set hier_sep [get_hierarchy_separator]
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@ -398,7 +376,7 @@ proc getOrCreateVCCPin {parent} {
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set vcc_cell [get_cells -quiet $cell_name]
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if {[llength $vcc_cell] == 0} {
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set vcc_cell [create_cell -reference VCC $cell_name]
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if {$info} {puts "INFO: Created VCC cell: '$vcc_cell'"}
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if {$debug} {puts "DEBUG: Created VCC cell: '$vcc_cell'"}
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} elseif {[llength $vcc_cell] > 1} {
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puts "ERROR: Multiple VCC cells found with name '$cell_name'."
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exit -1
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@ -417,7 +395,6 @@ proc getOrCreateVCCPin {parent} {
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}
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proc getOrCreateGNDPin {parent} {
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variable info
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variable debug
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set hier_sep [get_hierarchy_separator]
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@ -426,7 +403,7 @@ proc getOrCreateGNDPin {parent} {
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set gnd_cell [get_cells -quiet $cell_name]
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if {[llength $gnd_cell] == 0} {
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set gnd_cell [create_cell -reference GND $cell_name]
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if {$info} {puts "INFO: Created GND cell: '$gnd_cell'"}
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if {$debug} {puts "DEBUG: Created GND cell: '$gnd_cell'"}
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} elseif {[llength $gnd_cell] > 1} {
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puts "ERROR: Multiple GND cells found with name '$cell_name'."
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exit -1
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@ -444,16 +421,28 @@ proc getOrCreateGNDPin {parent} {
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return $gnd_pin
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}
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proc find_net_sinks {input_net {should_exist 1}} {
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proc find_net_sinks {source_net {should_exist 1}} {
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set sink_pins {}
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foreach pin [get_pins -quiet -leaf -of_objects $input_net -filter {DIRECTION == "IN"}] {
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lappend sink_pins $pin
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# Iterate through all pins connected to the source net
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foreach pin [get_pins -quiet -of_objects $source_net] {
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set direction [get_property DIRECTION $pin]
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# Input pins of nested cells
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if {$direction == "IN"} {
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lappend sink_pins $pin
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}
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# Output pins of the parent cell
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set pin_cell [get_cells -of_objects $pin]
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set is_primitive [get_property IS_PRIMITIVE $pin_cell]
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if {$direction == "OUT" && !$is_primitive} {
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lappend sink_pins $pin
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}
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}
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foreach port [get_ports -quiet -of_objects $input_net -filter {DIRECTION == "OUT"}] {
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# Add any top-module output ports connected to the source net
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foreach port [get_ports -quiet -of_objects $source_net -filter {DIRECTION == "OUT"}] {
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lappend sink_pins $port
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}
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if {[llength $sink_pins] == 0} {
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print_error "No sink found for '$input_net'." $should_exist
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print_error "No sink found for '$source_net'." $should_exist
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}
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return $sink_pins
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}
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@ -497,13 +486,49 @@ proc find_matching_pins {cell pins match repl} {
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}
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proc replace_net_source {net source_pin} {
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variable debug
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foreach pin [find_net_sinks $net 0] {
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replace_pin_source $pin $source_pin
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# disconnect net from pin
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disconnect_net -net $net -objects $pin
|
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if {$debug} {puts "DEBUG: Disconnected net '$net' from pin '$pin'."}
|
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|
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# find/create source net
|
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set source_net [get_nets -quiet -of_objects $source_pin]
|
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if {[llength $source_net] == 0} {
|
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# Create a new net (in source_cell's parent) if none exists
|
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set source_cell [get_cells -of_objects $source_pin]
|
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set net_name [unique_net_name "${source_cell}_tmp_net"]
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set source_net [create_net $net_name]
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if {$debug} {puts "DEBUG: Created source_net: '$source_net'"}
|
||||
# Connect the source pin to the new net
|
||||
connect_net -net $source_net -objects $source_pin -hierarchical
|
||||
if {$debug} {puts "DEBUG: Connected net '$source_net' to pin '$source_pin'."}
|
||||
} elseif {[llength $source_net] > 1} {
|
||||
puts "ERROR: Multiple nets connected to pin '$source_pin'."
|
||||
exit -1
|
||||
}
|
||||
|
||||
set external_net [get_nets -of_objects $pin]
|
||||
if {[llength $external_net] == 0} {
|
||||
# Connect pin to source net
|
||||
connect_net -net $source_net -objects $pin -hierarchical
|
||||
if {$debug} {puts "DEBUG: Connected net '$source_net' to pin '$pin'."}
|
||||
} elseif {[llength $external_net] == 1} {
|
||||
foreach external_pin [get_pins -of_objects $external_net] {
|
||||
# disconnect external net from pin
|
||||
disconnect_net -net $external_net -objects $pin
|
||||
if {$debug} {puts "DEBUG: Disconnected net '$external_net' from pin '$pin'."}
|
||||
# recurse-connect external net's pins to source_pin
|
||||
replace_net_source $external_net $source_pin
|
||||
}
|
||||
} else {
|
||||
puts "ERROR: Multiple nets connected to pin '$pin'."
|
||||
exit -1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc resolve_async_bram {inst} {
|
||||
variable info
|
||||
variable debug
|
||||
|
||||
puts "INFO: Resolving asynchronous BRAM patch: '$inst'."
|
||||
|
|
@ -511,20 +536,32 @@ proc resolve_async_bram {inst} {
|
|||
set hier_sep [get_hierarchy_separator]
|
||||
|
||||
set raddr_w_nets [find_cell_nets $inst "raddr_w(\\\[\\d+\\\])?$"]
|
||||
set read_s_net [find_cell_nets $inst "read_s$"]
|
||||
set is_raddr_reg_net [find_cell_nets $inst "is_raddr_reg$"]
|
||||
|
||||
set read_s_net [find_cell_net $inst "read_s$"]
|
||||
if {$debug} {puts "DEBUG: read_s_net: '$read_s_net'"}
|
||||
|
||||
set is_raddr_reg_net [find_cell_net $inst "g_async_ram.is_raddr_reg$" 0]
|
||||
if {$debug} {puts "DEBUG: is_raddr_reg_net: '$is_raddr_reg_net'"}
|
||||
|
||||
set raddr_s_nets [find_matching_nets $inst $raddr_w_nets "raddr_w(\\\[\\d+\\\])?$" "raddr_s\\1"]
|
||||
|
||||
set reg_next_pins {}
|
||||
set reg_ce_src_pin ""
|
||||
|
||||
set raddr_reset_net [find_cell_net $inst "raddr_reset$" 0]
|
||||
if {$debug} {puts "DEBUG: raddr_reset: '$raddr_reset_net'"}
|
||||
|
||||
# Process each raddr_w net
|
||||
foreach raddr_w_net $raddr_w_nets {
|
||||
if {$debug} {puts "DEBUG: Processing raddr_w net: '$raddr_w_net'"}
|
||||
|
||||
# Find raddr_w_net's driver pin
|
||||
set raddr_src_pin [find_net_driver $raddr_w_net]
|
||||
if {$debug} {puts "DEBUG: raddr_src_pin: '$raddr_src_pin'"}
|
||||
if {[get_ports -quiet $raddr_src_pin] ne ""} {
|
||||
puts "WARNING: Net '$raddr_w_net' is not registered, driver_type=port"
|
||||
break
|
||||
}
|
||||
|
||||
# Get the driver cell
|
||||
set raddr_src_cell [get_cells -of_objects $raddr_src_pin]
|
||||
|
|
@ -541,12 +578,12 @@ proc resolve_async_bram {inst} {
|
|||
if {$driver_type == "FDRE" || $driver_type == "FDSE"} {
|
||||
if {$debug} {puts "DEBUG: Net '$raddr_w_net' is registered, driver_type='$driver_type'"}
|
||||
} else {
|
||||
puts "WARNING: Net '$raddr_w_net' is not be registered, driver_type='$driver_type'"
|
||||
puts "WARNING: Net '$raddr_w_net' is not registered, driver_type='$driver_type'"
|
||||
break
|
||||
}
|
||||
|
||||
# Create register next cell and return output pin
|
||||
set reg_next_pin [create_register_next $inst $raddr_src_cell]
|
||||
set reg_next_pin [create_register_next $inst $raddr_src_cell $raddr_reset_net]
|
||||
if {$reg_next_pin == ""} {
|
||||
puts "ERROR: failed to create register next value for '$raddr_src_cell'."
|
||||
exit -1
|
||||
|
|
@ -576,61 +613,75 @@ proc resolve_async_bram {inst} {
|
|||
}
|
||||
}
|
||||
|
||||
set addr_width [llength $raddr_w_nets]
|
||||
|
||||
# do we have a fully registered read address?
|
||||
if {[llength $reg_next_pins] == [llength $raddr_w_nets]} {
|
||||
if {$info} {puts "INFO: Fully registered read address detected."}
|
||||
if {[llength $reg_next_pins] == $addr_width} {
|
||||
if {$debug} {puts "DEBUG: Fully registered read address detected."}
|
||||
|
||||
# Connect all reg_next_pins to all input pins attached to raddr_s_nets
|
||||
set addr_width [llength $raddr_w_nets]
|
||||
for {set addr_idx 0} {$addr_idx < $addr_width} {incr addr_idx} {
|
||||
set raddr_s_net [lindex $raddr_s_nets $addr_idx]
|
||||
set reg_next_pin [lindex $reg_next_pins $addr_idx]
|
||||
if {$info} {puts "INFO: Connecting pin '$reg_next_pin' to '$raddr_s_net's pins."}
|
||||
# Connect reg_next_pin to all input pins attached to raddr_s_net
|
||||
if {$debug} {puts "DEBUG: Connecting pin '$reg_next_pin' net to '$raddr_s_net's pins."}
|
||||
replace_net_source $raddr_s_net $reg_next_pin
|
||||
}
|
||||
|
||||
# Connect reg_ce_src_pin to all input pins attached to read_s_net
|
||||
if {$info} {puts "INFO: Connecting pin '$reg_ce_src_pin' to '$read_s_net's pins."}
|
||||
if {$debug} {puts "DEBUG: Connecting pin '$reg_ce_src_pin' net to '$read_s_net's pins."}
|
||||
replace_net_source $read_s_net $reg_ce_src_pin
|
||||
|
||||
# Create Const<1>'s pin
|
||||
set vcc_pin [getOrCreateVCCPin $inst]
|
||||
if {$is_raddr_reg_net != ""} {
|
||||
# Create Const<1>'s pin
|
||||
set vcc_pin [getOrCreateVCCPin $inst]
|
||||
|
||||
# Connect vcc_pin to all input pins attached to is_raddr_reg_net
|
||||
if {$info} {puts "INFO: Connecting pin '$vcc_pin' to '$is_raddr_reg_net's pins."}
|
||||
replace_net_source $is_raddr_reg_net $vcc_pin
|
||||
|
||||
# Remove all async_ram cells
|
||||
foreach cell [find_nested_cells $inst "g_async_ram.*" 0] {
|
||||
remove_cell_from_netlist $cell
|
||||
# Connect vcc_pin to all input pins attached to is_raddr_reg_net
|
||||
if {$debug} {puts "DEBUG: Connecting pin '$vcc_pin' to net '$is_raddr_reg_net's pins."}
|
||||
replace_net_source $is_raddr_reg_net $vcc_pin
|
||||
}
|
||||
} else {
|
||||
puts "WARNING: Not all read addresses are registered!"
|
||||
if {$is_raddr_reg_net == ""} {
|
||||
puts "ERROR: read address not fully registered!"
|
||||
exit -1
|
||||
} else {
|
||||
puts "WARNING: read address not fully registered!"
|
||||
}
|
||||
|
||||
# Create Const<0>'s pin
|
||||
set gnd_pin [getOrCreateGNDPin $inst]
|
||||
|
||||
# Connect gnd_pin to all input pins attached to is_raddr_reg_net
|
||||
if {$info} {puts "INFO: Connecting pin '$gnd_pin' to '$is_raddr_reg_net's pins."}
|
||||
replace_net_source $is_raddr_reg_net $gnd_pin
|
||||
|
||||
# Remove all sync_ram cells
|
||||
foreach cell [find_nested_cells $inst "g_sync_ram.*" 0] {
|
||||
remove_cell_from_netlist $cell
|
||||
# Connect GND to all input pins attached to raddr_s_nets
|
||||
for {set addr_idx 0} {$addr_idx < $addr_width} {incr addr_idx} {
|
||||
set raddr_s_net [lindex $raddr_s_nets $addr_idx]
|
||||
if {$debug} {puts "DEBUG: Connecting pin '$gnd_pin' net to '$raddr_s_net's pins."}
|
||||
replace_net_source $raddr_s_net $gnd_pin
|
||||
}
|
||||
|
||||
# Connect GND to all input pins attached to read_s_net
|
||||
if {$debug} {puts "DEBUG: Connecting pin '$gnd_pin' net to '$read_s_net's pins."}
|
||||
replace_net_source $read_s_net $gnd_pin
|
||||
|
||||
# Connect gnd_pin to all input pins attached to is_raddr_reg_net
|
||||
if {$debug} {puts "DEBUG: Connecting pin '$gnd_pin' to net '$is_raddr_reg_net's pins."}
|
||||
replace_net_source $is_raddr_reg_net $gnd_pin
|
||||
}
|
||||
|
||||
# Remove placeholder cell
|
||||
foreach cell [find_nested_cells $inst "placeholder$"] {
|
||||
# Remove placeholder cells
|
||||
foreach cell [find_nested_cells $inst "placeholder1$"] {
|
||||
remove_cell_from_netlist $cell
|
||||
}
|
||||
if {$is_raddr_reg_net != ""} {
|
||||
foreach cell [find_nested_cells $inst "g_async_ram.placeholder2$"] {
|
||||
remove_cell_from_netlist $cell
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc resolve_async_brams {} {
|
||||
variable debug
|
||||
set bram_patch_cells {}
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME =~ "*VX_async_ram_patch*"}] {
|
||||
puts "INFO: Found async BRAM patch cell: '$cell'."
|
||||
if {$debug} {puts "DEBUG: Found async BRAM patch cell: '$cell'."}
|
||||
lappend bram_patch_cells $cell
|
||||
}
|
||||
if {[llength $bram_patch_cells] != 0} {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue