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Create the memory blocks with CLN28HPM

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Lingjun Zhu 2019-10-17 15:38:48 -04:00
parent d164ebfbc6
commit 84d321a517
22 changed files with 300005 additions and 0 deletions
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.bitmap Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.cpf Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.ctl Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.lef Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.mdt Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.memlib Normal file
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/* logicvision_memcomp Version: c0.1.2-beta */
/* common_memcomp Version: c0.1.0-EAC */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// logicvision model for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x128_wm1
// Words: 32
// Bits: 128
// Mux: 2
// Drive: 6
// Write Mask: On
// Extra Margin Adjustment: On
// Redundant Rows: 0
// Redundant Columns: 2
// Test Muxes On
//
// Creation Date: Thu Oct 17 15:31:40 2019
// Version: r4p0
//
// Modeling Assumptions:
//
// Modeling Limitations: None
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
MemoryTemplate (rf2_32x128_wm1) {
Algorithm : SmarchChkbvcd;
DataOutStage : None;
LogicalPorts : 1R1W;
BitGrouping : 1;
MemoryType : SRAM;
MinHold : 0.5;
OperationSet : SyncWRvcd;
SelectDuringWriteThru : Off;
ShadowRead : On;
ShadowWrite : On;
TransparentMode : None;
ObservationLogic: On;
InternalScanLogic: On;
CellName : rf2_32x128_wm1;
NumberOfWords : 32;
AddressCounter{
Function (Address) {
LogicalAddressMap{
ColumnAddress[0] : Address[0];
RowAddress[3:0] : Address[4:1];
}
}
Function (ColumnAddress) {
CountRange [0:1];
}
Function (RowAddress) {
CountRange [0:15];
}
}
PhysicalAddressMap{
ColumnAddress[0] : c[0];
RowAddress[0] : r[0];
RowAddress[1] : r[1];
RowAddress[2] : r[2];
RowAddress[3] : r[3];
}
PhysicalDataMap{
Data[0] : NOT d[0];
Data[1] : NOT d[1];
Data[2] : NOT d[2];
Data[3] : NOT d[3];
Data[4] : NOT d[4];
Data[5] : NOT d[5];
Data[6] : NOT d[6];
Data[7] : NOT d[7];
Data[8] : NOT d[8];
Data[9] : NOT d[9];
Data[10] : NOT d[10];
Data[11] : NOT d[11];
Data[12] : NOT d[12];
Data[13] : NOT d[13];
Data[14] : NOT d[14];
Data[15] : NOT d[15];
Data[16] : NOT d[16];
Data[17] : NOT d[17];
Data[18] : NOT d[18];
Data[19] : NOT d[19];
Data[20] : NOT d[20];
Data[21] : NOT d[21];
Data[22] : NOT d[22];
Data[23] : NOT d[23];
Data[24] : NOT d[24];
Data[25] : NOT d[25];
Data[26] : NOT d[26];
Data[27] : NOT d[27];
Data[28] : NOT d[28];
Data[29] : NOT d[29];
Data[30] : NOT d[30];
Data[31] : NOT d[31];
Data[32] : NOT d[32];
Data[33] : NOT d[33];
Data[34] : NOT d[34];
Data[35] : NOT d[35];
Data[36] : NOT d[36];
Data[37] : NOT d[37];
Data[38] : NOT d[38];
Data[39] : NOT d[39];
Data[40] : NOT d[40];
Data[41] : NOT d[41];
Data[42] : NOT d[42];
Data[43] : NOT d[43];
Data[44] : NOT d[44];
Data[45] : NOT d[45];
Data[46] : NOT d[46];
Data[47] : NOT d[47];
Data[48] : NOT d[48];
Data[49] : NOT d[49];
Data[50] : NOT d[50];
Data[51] : NOT d[51];
Data[52] : NOT d[52];
Data[53] : NOT d[53];
Data[54] : NOT d[54];
Data[55] : NOT d[55];
Data[56] : NOT d[56];
Data[57] : NOT d[57];
Data[58] : NOT d[58];
Data[59] : NOT d[59];
Data[60] : NOT d[60];
Data[61] : NOT d[61];
Data[62] : NOT d[62];
Data[63] : NOT d[63];
Data[64] : d[64];
Data[65] : d[65];
Data[66] : d[66];
Data[67] : d[67];
Data[68] : d[68];
Data[69] : d[69];
Data[70] : d[70];
Data[71] : d[71];
Data[72] : d[72];
Data[73] : d[73];
Data[74] : d[74];
Data[75] : d[75];
Data[76] : d[76];
Data[77] : d[77];
Data[78] : d[78];
Data[79] : d[79];
Data[80] : d[80];
Data[81] : d[81];
Data[82] : d[82];
Data[83] : d[83];
Data[84] : d[84];
Data[85] : d[85];
Data[86] : d[86];
Data[87] : d[87];
Data[88] : d[88];
Data[89] : d[89];
Data[90] : d[90];
Data[91] : d[91];
Data[92] : d[92];
Data[93] : d[93];
Data[94] : d[94];
Data[95] : d[95];
Data[96] : d[96];
Data[97] : d[97];
Data[98] : d[98];
Data[99] : d[99];
Data[100] : d[100];
Data[101] : d[101];
Data[102] : d[102];
Data[103] : d[103];
Data[104] : d[104];
Data[105] : d[105];
Data[106] : d[106];
Data[107] : d[107];
Data[108] : d[108];
Data[109] : d[109];
Data[110] : d[110];
Data[111] : d[111];
Data[112] : d[112];
Data[113] : d[113];
Data[114] : d[114];
Data[115] : d[115];
Data[116] : d[116];
Data[117] : d[117];
Data[118] : d[118];
Data[119] : d[119];
Data[120] : d[120];
Data[121] : d[121];
Data[122] : d[122];
Data[123] : d[123];
Data[124] : d[124];
Data[125] : d[125];
Data[126] : d[126];
Data[127] : d[127];
}
Port (AA[4:0]) {
Function : Address;
LogicalPort : A;
EmbeddedTestLogic {
TestInput : TAA[4:0];
TestOutput : AYA[4:0];
}
}
Port (QA[127:0]) {
Function : Data;
Direction : output;
LogicalPort : A;
}
Port (CENA) {
Function : ReadEnable;
LogicalPort : A;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TCENA;
TestOutput : CENYA;
}
}
Port (TENA) {
Function : BISTOn;
Direction : Input;
LogicalPort : A;
Polarity : ActiveLow;
}
Port (CLKA) {
Function : Clock;
LogicalPort : A;
Polarity : ActiveHigh;
}
Port (EMAA[2:0]) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : A;
Polarity : ActiveHigh;
}
Port (EMASA) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : A;
Polarity : ActiveHigh;
}
port (SEA){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SIA[1:0]){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SOA[1:0]){
Function : None;
Direction : Output;
}
port (DFTRAMBYP){
Function : ScanTest;
Direction : Input;
Polarity : ActiveHigh;
}
Port (AB[4:0]) {
Function : Address;
LogicalPort : B;
EmbeddedTestLogic {
TestInput : TAB[4:0];
TestOutput : AYB[4:0];
}
}
Port (DB[127:0]) {
Function : Data;
Direction : input;
LogicalPort : B;
EmbeddedTestLogic {
TestInput : TDB[127:0];
}
}
Port (WENB[127:0]) {
Function : GroupWriteEnable;
BitsPerWriteEnable: 1;
LogicalPort : B;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TWENB[127:0];
TestOutput : WENYB[127:0];
}
}
Port (CENB) {
Function : WriteEnable;
LogicalPort : B;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TCENB;
TestOutput : CENYB;
}
}
Port (TENB) {
Function : BISTOn;
Direction : Input;
LogicalPort : B;
Polarity : ActiveLow;
}
Port (CLKB) {
Function : Clock;
LogicalPort : B;
Polarity : ActiveHigh;
}
Port (EMAB[2:0]) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : B;
Polarity : ActiveHigh;
}
Port (COLLDISN) {
Function : None;
SafeValue : 1;
Direction : Input;
Polarity : ActiveLow;
}
port (SEB){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SIB[1:0]){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SOB[1:0]){
Function : None;
Direction : Output;
}
port (RET1N){
Function : None;
Direction : Input;
SafeValue : 1;
Polarity : Activelow;
}
}

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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_125c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Thu Oct 17 15:29:13 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1
# Number of Words: 32
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_32x128_wm1 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 4506
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.99 0.99
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 5.89011e-05nF
VDDPE VSSE 6.00360e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 2.37212mA
VDDPE VSSE 8.16093mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 6.47912e-05nF
VDDPE VSSE 4.32324e-03nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 2.60933mA
VDDPE VSSE 51.02643mA
}
Cpd avm_read_write {
VDDCE VSSE 3.55697e-04nF
VDDPE VSSE 8.20194e-03nF
}
PEAK_I avm_read_write {
VDDCE VSSE 5.29939mA
VDDPE VSSE 66.82583mA
}
Cpd avm_read_desel {
VDDCE VSSE 9.34000e-05nF
VDDPE VSSE 3.67589e-03nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 1.90281mA
VDDPE VSSE 41.50860mA
}
Cpd avm_desel_write {
VDDCE VSSE 2.62297e-04nF
VDDPE VSSE 4.52606e-03nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 4.36243mA
VDDPE VSSE 63.64365mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.09457e-06nF
VDDPE VSSE 1.07376e-02nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.43640mA
VDDPE VSSE 39.07064mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.09457e-06nF
VDDPE VSSE 1.07376e-02nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.43640mA
VDDPE VSSE 39.07064mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.95501e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 2.17223e-05nF
}
LEAKAGE_I {
VDDCE VSSE 0.23098mA
VDDPE VSSE 1.17816mA
}
tsu 0.092778ns
ck2q_delay 0.530131ns
tr_q 0.01373ns
tf_q 0.01596ns
CHARACTERIZATION_MODE accurate
}

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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Thu Oct 17 15:29:37 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1
# Number of Words: 32
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name ff_0p99v_0p99v_125c
S N
geomx 21.1650
geomy 414.8600
volt 0.9900
temp 125.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.0917
ttcenacenya 0.0905
ttenacenyapu 0.1191
ttenacenyanu 0.1400
tdftrambypcenya 0.1299
taaaya 0.0751
ttaaaya 0.0751
ttenaayapu 0.1377
ttenaayanu 0.1338
tdftrambypaya 0.1197
tcenbcenyb 0.0947
ttcenbcenyb 0.0939
ttenbcenybpu 0.1236
ttenbcenybnu 0.1996
tdftrambypcenyb 0.1226
twenbwenyb 0.0927
ttwenbwenyb 0.0930
ttenbwenybpu 0.2539
ttenbwenybnu 0.2667
tdftrambypwenyb 0.1651
tabayb 0.0753
ttabayb 0.0779
ttenbaybpu 0.1929
ttenbaybnu 0.1969
tdftrambypayb 0.1194
taccqa_rd0 0.5293
taccqa_rd1 0.5288
taccqa_rd2 0.5295
taccqa_rd3 0.5301
taccqa_rd4 0.5711
taccqa_rd5 0.6083
taccqa_rd6 0.6469
taccqa_rd7 0.6841
taccqa_scan0 0.5293
taccqa_scan1 0.5288
taccqa_scan2 0.5295
taccqa_scan3 0.5301
taccqa_scan4 0.5711
taccqa_scan5 0.6083
taccqa_scan6 0.6469
taccqa_scan7 0.6841
tclkasoa_rd0 0.5408
tclkasoa_rd1 0.5402
tclkasoa_rd2 0.5410
tclkasoa_rd3 0.5416
tclkasoa_rd4 0.5826
tclkasoa_rd5 0.6198
tclkasoa_rd6 0.6584
tclkasoa_rd7 0.6955
tclkasoa_scan0 0.5408
tclkasoa_scan1 0.5402
tclkasoa_scan2 0.5410
tclkasoa_scan3 0.5416
tclkasoa_scan4 0.5826
tclkasoa_scan5 0.6198
tclkasoa_scan6 0.6584
tclkasoa_scan7 0.6955
tclkbsob 0.2275
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 1.7116
kload_aya 1.4236
kload_cenyb 1.6712
kload_wenyb 1.4498
kload_ayb 1.4006
kload_qa 0.5053
kload_soa 1.3720
kload_sob 1.4400
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.7407
tcyca_ema1 0.7401
tcyca_ema2 0.7410
tcyca_ema3 0.7415
tcyca_ema4 0.7832
tcyca_ema5 0.8209
tcyca_ema6 0.8601
tcyca_ema7 0.8978
tcycb_ema0 0.8193
tcycb_ema1 0.8263
tcycb_ema2 0.8338
tcycb_ema3 0.8472
tcycb_ema4 0.8976
tcycb_ema5 0.9345
tcycb_ema6 0.9817
tcycb_ema7 1.0185
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.5429
tcracwb_rd1 0.5424
tcracwb_rd2 0.5432
tcracwb_rd3 0.5437
tcracwb_rd4 0.5847
tcracwb_rd5 0.6219
tcracwb_rd6 0.6605
tcracwb_rd7 0.6977
tcwbcra_wr0 0.6171
tcwbcra_wr1 0.6240
tcwbcra_wr2 0.6314
tcwbcra_wr3 0.6446
tcwbcra_wr4 0.6942
tcwbcra_wr5 0.7306
tcwbcra_wr6 0.7771
tcwbcra_wr7 0.8134
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.0926
tckal 0.0897
tckbh 0.0958
tckbl 0.0907
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.0902
taas 0.0928
tcenbs 0.0960
twenbs 0.0150
tabs 0.0993
tdbs 0.0228
temaas 0.7668
temasas 0.7668
temabs 0.8724
ttenas 0.1737
ttcenas 0.0905
ttaas 0.0948
ttenbs 0.3774
ttcenbs 0.0965
ttwenbs 0.0151
ttabs 0.1030
ttdbs 0.0237
tsias 0.1911
tseas 0.1911
tdftrambypas 0.2243
tdftrambypbs 0.2243
tsibs 0.0228
tsebs 0.3774
tcolldisnas 0.7668
tcolldisnbs 0.8724
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0398
tcenaf_ret1nfh 0.8821
tcenaf_ret1nrh 0.3064
taah 0.0695
tcenbh 0.0422
tcenbf_ret1nfh 0.8821
tcenbf_ret1nrh 0.3064
twenbh 0.1736
tabh 0.0637
tdbh 0.1710
temaah 0.9921
temasah 0.9921
temabh 1.0535
ttenah 0.0764
ttcenah 0.0410
ttcenaf_ret1nfh 0.8821
ttcenaf_ret1nrh 0.3064
ttaah 0.0695
ttenbh 0.1918
ttcenbh 0.0435
ttcenbf_ret1nfh 0.8821
ttcenbf_ret1nrh 0.3064
ttwenbh 0.1743
ttabh 0.0637
ttdbh 0.1710
tret1nf_dftrambypfh 0.0241
tret1nr_dftrambypfh 0.8821
tret1nf_cenbrh 0.0241
tret1nf_cenarh 0.0226
tret1nf_tcenarh 0.0226
tret1nf_tcenbrh 0.0241
tret1nr_tcenbrh 0.8821
tret1nr_tcenarh 0.7765
tret1nr_cenbrh 0.8821
tret1nr_cenarh 0.7765
tsiah 0.0756
tseah 0.9921
tdftrambypah 0.9921
tdftrambypbh 0.8821
tdftrambypr_ret1nfh 0.8821
tdftrambypr_ret1nrh 0.3064
tsibh 0.1710
tsebh 0.1918
tcolldisnah 0.9921
tcolldisnbh 1.0535
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0105
icap_cena 0.0018
icap_aa 0.0012
icap_clkb 0.0106
icap_cenb 0.0015
icap_wenb 0.0017
icap_ab 0.0012
icap_db 0.0019
icap_emaa 0.0059
icap_emasa 0.0021
icap_emab 0.0057
icap_tena 0.0010
icap_tcena 0.0016
icap_taa 0.0014
icap_tenb 0.0012
icap_tcenb 0.0016
icap_twenb 0.0015
icap_tab 0.0014
icap_tdb 0.0016
icap_sia 0.0015
icap_sea 0.0019
icap_dftrambyp 0.0021
icap_sib 0.0056
icap_seb 0.0019
icap_colldisn 0.0024
icap_ret1n 0.0035
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 0.230985
icc_standby_p_chipdisable 1.178165
icc_standby_c_ret1 0.265746
icc_standby_p_ret1 0.111473
icc_standby_c_selective_precharge 0.227337
icc_standby_p_selective_precharge 1.096501
icc_c_rd0_a 9.188e-05
icc_c_rd1_a 9.229e-05
icc_c_rd2_a 9.229e-05
icc_c_rd3_a 9.247e-05
icc_c_rd4_a 9.517e-05
icc_c_rd5_a 9.683e-05
icc_c_rd6_a 9.809e-05
icc_c_rd7_a 9.975e-05
icc_p_rd0_a 3.638e-03
icc_p_rd1_a 3.638e-03
icc_p_rd2_a 3.638e-03
icc_p_rd3_a 3.639e-03
icc_p_rd4_a 3.653e-03
icc_p_rd5_a 3.669e-03
icc_p_rd6_a 3.674e-03
icc_p_rd7_a 3.674e-03
icc_c_wr0_b 2.591e-04
icc_c_wr1_b 2.595e-04
icc_c_wr2_b 2.595e-04
icc_c_wr3_b 2.597e-04
icc_c_wr4_b 2.624e-04
icc_c_wr5_b 2.640e-04
icc_c_wr6_b 2.653e-04
icc_c_wr7_b 2.670e-04
icc_p_wr0_b 4.479e-03
icc_p_wr1_b 4.479e-03
icc_p_wr2_b 4.479e-03
icc_p_wr3_b 4.481e-03
icc_p_wr4_b 4.494e-03
icc_p_wr5_b 4.511e-03
icc_p_wr6_b 4.516e-03
icc_p_wr7_b 4.516e-03
icc_c_desela 0.000e+00
icc_p_desela 6.071e-05
icc_c_deselb 0.000e+00
icc_p_deselb 1.156e-03
icc_c_peak 5.299387
icc_p_peak 66.825833
icc_c_inrush 2.617944
icc_p_inrush 51.02643

71102
models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_125c.lib Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_125c.ps Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v Normal file
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/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
/* common_memcomp Version: 4.0.5.2-amci */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x128_wm1_rtl_top
// Words: 32
// User Bits: 128
// Mux: 2
// Drive: 6
// Write Mask: On
// Extra Margin Adjustment: On
// Redundancy: off
// Redundant Rows: 0
// Redundant Columns: 2
// Test Muxes On
// Ser: none
// Retention: on
// Power Gating: off
//
// Creation Date: Thu Oct 17 15:32:14 2019
// Version: r4p0
//
// Verified
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
`timescale 1ns/1ps
module rf2_32x128_wm1_rtl_top (
CENYA,
AYA,
CENYB,
WENYB,
AYB,
QA,
SOA,
SOB,
CLKA,
CENA,
AA,
CLKB,
CENB,
WENB,
AB,
DB,
EMAA,
EMASA,
EMAB,
TENA,
TCENA,
TAA,
TENB,
TCENB,
TWENB,
TAB,
TDB,
RET1N,
SIA,
SEA,
DFTRAMBYP,
SIB,
SEB,
COLLDISN
);
output CENYA;
output [4:0] AYA;
output CENYB;
output [127:0] WENYB;
output [4:0] AYB;
output [127:0] QA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [4:0] AA;
input CLKB;
input CENB;
input [127:0] WENB;
input [4:0] AB;
input [127:0] DB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [4:0] TAA;
input TENB;
input TCENB;
input [127:0] TWENB;
input [4:0] TAB;
input [127:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
wire [127:0] QOA;
wire [127:0] DIB;
assign QA = QOA;
assign DIB = DB;
rf2_32x128_wm1_fr_top u0 (
.CENYA(CENYA),
.AYA(AYA),
.CENYB(CENYB),
.WENYB(WENYB),
.AYB(AYB),
.QOA(QOA),
.SOA(SOA),
.SOB(SOB),
.CLKA(CLKA),
.CENA(CENA),
.AA(AA),
.CLKB(CLKB),
.CENB(CENB),
.WENB(WENB),
.AB(AB),
.DIB(DIB),
.EMAA(EMAA),
.EMASA(EMASA),
.EMAB(EMAB),
.TENA(TENA),
.TCENA(TCENA),
.TAA(TAA),
.TENB(TENB),
.TCENB(TCENB),
.TWENB(TWENB),
.TAB(TAB),
.TDB(TDB),
.RET1N(RET1N),
.SIA(SIA),
.SEA(SEA),
.DFTRAMBYP(DFTRAMBYP),
.SIB(SIB),
.SEB(SEB),
.COLLDISN(COLLDISN)
);
endmodule
module rf2_32x128_wm1_fr_top (
CENYA,
AYA,
CENYB,
WENYB,
AYB,
QOA,
SOA,
SOB,
CLKA,
CENA,
AA,
CLKB,
CENB,
WENB,
AB,
DIB,
EMAA,
EMASA,
EMAB,
TENA,
TCENA,
TAA,
TENB,
TCENB,
TWENB,
TAB,
TDB,
RET1N,
SIA,
SEA,
DFTRAMBYP,
SIB,
SEB,
COLLDISN
);
output CENYA;
output [4:0] AYA;
output CENYB;
output [127:0] WENYB;
output [4:0] AYB;
output [127:0] QOA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [4:0] AA;
input CLKB;
input CENB;
input [127:0] WENB;
input [4:0] AB;
input [127:0] DIB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [4:0] TAA;
input TENB;
input TCENB;
input [127:0] TWENB;
input [4:0] TAB;
input [127:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
wire [127:0] DB;
wire [127:0] QA;
assign DB=DIB;
assign QOA=QA;
rf2_32x128_wm1 u0 (
.CENYA(CENYA),
.AYA(AYA),
.CENYB(CENYB),
.WENYB(WENYB),
.AYB(AYB),
.QA(QA),
.SOA(SOA),
.SOB(SOB),
.CLKA(CLKA),
.CENA(CENA),
.AA(AA),
.CLKB(CLKB),
.CENB(CENB),
.WENB(WENB),
.AB(AB),
.DB(DB),
.EMAA(EMAA),
.EMASA(EMASA),
.EMAB(EMAB),
.TENA(TENA),
.TCENA(TCENA),
.TAA(TAA),
.TENB(TENB),
.TCENB(TCENB),
.TWENB(TWENB),
.TAB(TAB),
.TDB(TDB),
.RET1N(RET1N),
.SIA(SIA),
.SEA(SEA),
.DFTRAMBYP(DFTRAMBYP),
.SIB(SIB),
.SEB(SEB),
.COLLDISN(COLLDISN)
);
endmodule // rf2_32x128_wm1_fr_top

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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Thu Oct 17 15:29:19 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1
# Number of Words: 32
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_32x128_wm1 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 4506
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.81 0.81
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 5.04933e-05nF
VDDPE VSSE 5.58322e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 0.76442mA
VDDPE VSSE 2.79191mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 5.55427e-05nF
VDDPE VSSE 4.44754e-03nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 0.84086mA
VDDPE VSSE 21.80573mA
}
Cpd avm_read_write {
VDDCE VSSE 2.70708e-04nF
VDDPE VSSE 7.50580e-03nF
}
PEAK_I avm_read_write {
VDDCE VSSE 1.66815mA
VDDPE VSSE 23.32566mA
}
Cpd avm_read_desel {
VDDCE VSSE 9.30272e-05nF
VDDPE VSSE 3.36233e-03nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 0.81027mA
VDDPE VSSE 15.06321mA
}
Cpd avm_desel_write {
VDDCE VSSE 1.77681e-04nF
VDDPE VSSE 4.14347e-03nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 1.27866mA
VDDPE VSSE 20.73249mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.14454e-06nF
VDDPE VSSE 9.88468e-03nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.14129mA
VDDPE VSSE 13.03296mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.14454e-06nF
VDDPE VSSE 9.88468e-03nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.14129mA
VDDPE VSSE 13.03296mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.69190e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.87989e-05nF
}
LEAKAGE_I {
VDDCE VSSE 1.86600e-04mA
VDDPE VSSE 3.12400e-04mA
}
tsu 0.25018ns
ck2q_delay 1.06727ns
tr_q 0.035168ns
tf_q 0.039641ns
CHARACTERIZATION_MODE accurate
}

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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.dat Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Thu Oct 17 15:29:41 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1
# Number of Words: 32
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name ss_0p81v_0p81v_m40c
S N
geomx 21.1650
geomy 414.8600
volt 0.8100
temp -40.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.2145
ttcenacenya 0.2108
ttenacenyapu 0.3026
ttenacenyanu 0.3541
tdftrambypcenya 0.3853
taaaya 0.2110
ttaaaya 0.2184
ttenaayapu 0.3904
ttenaayanu 0.3751
tdftrambypaya 0.3736
tcenbcenyb 0.2113
ttcenbcenyb 0.2108
ttenbcenybpu 0.3045
ttenbcenybnu 0.5445
tdftrambypcenyb 0.3738
twenbwenyb 0.2952
ttwenbwenyb 0.2956
ttenbwenybpu 0.6920
ttenbwenybnu 0.7096
tdftrambypwenyb 0.4014
tabayb 0.2105
ttabayb 0.2161
ttenbaybpu 0.5881
ttenbaybnu 0.5463
tdftrambypayb 0.3669
taccqa_rd0 1.0376
taccqa_rd1 1.0475
taccqa_rd2 1.0539
taccqa_rd3 1.0673
taccqa_rd4 1.1793
taccqa_rd5 1.3001
taccqa_rd6 1.4271
taccqa_rd7 1.5453
taccqa_scan0 1.0376
taccqa_scan1 1.0475
taccqa_scan2 1.0539
taccqa_scan3 1.0673
taccqa_scan4 1.1793
taccqa_scan5 1.3001
taccqa_scan6 1.4271
taccqa_scan7 1.5453
tclkasoa_rd0 1.1411
tclkasoa_rd1 1.1511
tclkasoa_rd2 1.1575
tclkasoa_rd3 1.1709
tclkasoa_rd4 1.2829
tclkasoa_rd5 1.4036
tclkasoa_rd6 1.5307
tclkasoa_rd7 1.6489
tclkasoa_scan0 1.1411
tclkasoa_scan1 1.1511
tclkasoa_scan2 1.1575
tclkasoa_scan3 1.1709
tclkasoa_scan4 1.2829
tclkasoa_scan5 1.4036
tclkasoa_scan6 1.5307
tclkasoa_scan7 1.6489
tclkbsob 0.5242
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 3.3060
kload_aya 2.7500
kload_cenyb 3.3440
kload_wenyb 3.0700
kload_ayb 2.7720
kload_qa 1.0935
kload_soa 2.7600
kload_sob 3.1660
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 1.5694
tcyca_ema1 1.5795
tcyca_ema2 1.5860
tcyca_ema3 1.5996
tcyca_ema4 1.7133
tcyca_ema5 1.8358
tcyca_ema6 1.9648
tcyca_ema7 2.0848
tcycb_ema0 1.7290
tcycb_ema1 1.7502
tcycb_ema2 1.7705
tcycb_ema3 1.8027
tcycb_ema4 1.9388
tcycb_ema5 2.0557
tcycb_ema6 2.2098
tcycb_ema7 2.3243
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.8419
tcracwb_rd1 0.8519
tcracwb_rd2 0.8583
tcracwb_rd3 0.8717
tcracwb_rd4 0.9837
tcracwb_rd5 1.1044
tcracwb_rd6 1.2315
tcracwb_rd7 1.3497
tcwbcra_wr0 1.1797
tcwbcra_wr1 1.2006
tcwbcra_wr2 1.2206
tcwbcra_wr3 1.2523
tcwbcra_wr4 1.3865
tcwbcra_wr5 1.5016
tcwbcra_wr6 1.6535
tcwbcra_wr7 1.7662
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.1790
tckal 0.1936
tckbh 0.1812
tckbl 0.1760
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.2125
taas 0.2502
tcenbs 0.2141
twenbs 0.0857
tabs 0.2561
tdbs 0.1681
temaas 1.6830
temasas 1.6830
temabs 1.8861
ttenas 0.4407
ttcenas 0.2138
ttaas 0.2589
ttenbs 0.7733
ttcenbs 0.2147
ttwenbs 0.0862
ttabs 0.2633
ttdbs 0.1738
tsias 0.4848
tseas 0.4848
tdftrambypas 0.6768
tdftrambypbs 0.6768
tsibs 0.1681
tsebs 0.7733
tcolldisnas 1.6830
tcolldisnbs 1.8861
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0854
tcenaf_ret1nfh 1.8669
tcenaf_ret1nrh 0.7170
taah 0.1392
tcenbh 0.0857
tcenbf_ret1nfh 1.8669
tcenbf_ret1nrh 0.7170
twenbh 0.3114
tabh 0.1263
tdbh 0.3013
temaah 2.3430
temasah 2.3430
temabh 2.3885
ttenah 0.1531
ttcenah 0.0871
ttcenaf_ret1nfh 1.8669
ttcenaf_ret1nrh 0.7170
ttaah 0.1392
ttenbh 0.3425
ttcenbh 0.0870
ttcenbf_ret1nfh 1.8669
ttcenbf_ret1nrh 0.7170
ttwenbh 0.3114
ttabh 0.1263
ttdbh 0.3013
tret1nf_dftrambypfh 0.0537
tret1nr_dftrambypfh 1.8669
tret1nf_cenbrh 0.0537
tret1nf_cenarh 0.0534
tret1nf_tcenarh 0.0534
tret1nf_tcenbrh 0.0537
tret1nr_tcenbrh 1.8669
tret1nr_tcenarh 1.6638
tret1nr_cenbrh 1.8669
tret1nr_cenarh 1.6638
tsiah 0.1246
tseah 2.3430
tdftrambypah 2.3430
tdftrambypbh 1.8669
tdftrambypr_ret1nfh 1.8669
tdftrambypr_ret1nrh 0.7170
tsibh 0.3013
tsebh 0.3425
tcolldisnah 2.3430
tcolldisnbh 2.3885
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0087
icap_cena 0.0014
icap_aa 0.0017
icap_clkb 0.0088
icap_cenb 0.0011
icap_wenb 0.0016
icap_ab 0.0015
icap_db 0.0018
icap_emaa 0.0056
icap_emasa 0.0021
icap_emab 0.0054
icap_tena 0.0008
icap_tcena 0.0012
icap_taa 0.0016
icap_tenb 0.0009
icap_tcenb 0.0012
icap_twenb 0.0014
icap_tab 0.0014
icap_tdb 0.0015
icap_sia 0.0011
icap_sea 0.0016
icap_dftrambyp 0.0016
icap_sib 0.0054
icap_seb 0.0017
icap_colldisn 0.0021
icap_ret1n 0.0032
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 1.866e-04
icc_standby_p_chipdisable 3.124e-04
icc_standby_c_ret1 1.865e-04
icc_standby_p_ret1 2.048e-06
icc_standby_c_selective_precharge 1.858e-04
icc_standby_p_selective_precharge 2.330e-04
icc_c_rd0_a 7.514e-05
icc_c_rd1_a 7.518e-05
icc_c_rd2_a 7.535e-05
icc_c_rd3_a 7.535e-05
icc_c_rd4_a 7.666e-05
icc_c_rd5_a 7.775e-05
icc_c_rd6_a 7.805e-05
icc_c_rd7_a 7.823e-05
icc_p_rd0_a 2.723e-03
icc_p_rd1_a 2.723e-03
icc_p_rd2_a 2.723e-03
icc_p_rd3_a 2.723e-03
icc_p_rd4_a 2.727e-03
icc_p_rd5_a 2.731e-03
icc_p_rd6_a 2.731e-03
icc_p_rd7_a 2.734e-03
icc_c_wr0_b 1.437e-04
icc_c_wr1_b 1.438e-04
icc_c_wr2_b 1.439e-04
icc_c_wr3_b 1.439e-04
icc_c_wr4_b 1.452e-04
icc_c_wr5_b 1.463e-04
icc_c_wr6_b 1.466e-04
icc_c_wr7_b 1.468e-04
icc_p_wr0_b 3.356e-03
icc_p_wr1_b 3.356e-03
icc_p_wr2_b 3.356e-03
icc_p_wr3_b 3.356e-03
icc_p_wr4_b 3.360e-03
icc_p_wr5_b 3.364e-03
icc_p_wr6_b 3.364e-03
icc_p_wr7_b 3.367e-03
icc_c_desela 0.000e+00
icc_p_desela 4.150e-05
icc_c_deselb 0.000e+00
icc_p_deselb 8.715e-04
icc_c_peak 1.668155
icc_p_peak 23.325655
icc_c_inrush 0.896531
icc_p_inrush 21.74526

71102
models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.lib Normal file
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5472
models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.ps Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p90v_0p90v_25c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Thu Oct 17 15:29:25 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1
# Number of Words: 32
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_32x128_wm1 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 4506
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.9 0.9
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 5.28788e-05nF
VDDPE VSSE 5.60810e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 1.42941mA
VDDPE VSSE 4.86744mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 5.81667e-05nF
VDDPE VSSE 4.59591e-03nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 1.57236mA
VDDPE VSSE 38.10373mA
}
Cpd avm_read_write {
VDDCE VSSE 3.14454e-04nF
VDDPE VSSE 7.77751e-03nF
}
PEAK_I avm_read_write {
VDDCE VSSE 2.96007mA
VDDPE VSSE 41.60165mA
}
Cpd avm_read_desel {
VDDCE VSSE 9.28639e-05nF
VDDPE VSSE 3.51267e-03nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 1.27545mA
VDDPE VSSE 25.44116mA
}
Cpd avm_desel_write {
VDDCE VSSE 2.21591e-04nF
VDDPE VSSE 4.26484e-03nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 2.47272mA
VDDPE VSSE 39.62062mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.56193e-06nF
VDDPE VSSE 1.02363e-02nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.27530mA
VDDPE VSSE 24.42748mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.56193e-06nF
VDDPE VSSE 1.02363e-02nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.27530mA
VDDPE VSSE 24.42748mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.77000e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.96666e-05nF
}
LEAKAGE_I {
VDDCE VSSE 1.67000e-03mA
VDDPE VSSE 7.54700e-03mA
}
tsu 0.126538ns
ck2q_delay 0.64031ns
tr_q 0.018851ns
tf_q 0.022205ns
CHARACTERIZATION_MODE accurate
}

334
models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p90v_0p90v_25c.dat Normal file
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@ -0,0 +1,334 @@
#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Thu Oct 17 15:29:45 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1
# Number of Words: 32
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name tt_0p90v_0p90v_25c
S N
geomx 21.1650
geomy 414.8600
volt 0.9000
temp 25.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.1187
ttcenacenya 0.1176
ttenacenyapu 0.1613
ttenacenyanu 0.1885
tdftrambypcenya 0.1900
taaaya 0.1038
ttaaaya 0.1082
ttenaayapu 0.1877
ttenaayanu 0.1835
tdftrambypaya 0.1776
tcenbcenyb 0.1195
ttcenbcenyb 0.1185
ttenbcenybpu 0.1658
ttenbcenybnu 0.2823
tdftrambypcenyb 0.1824
twenbwenyb 0.1351
ttwenbwenyb 0.1341
ttenbwenybpu 0.3463
ttenbwenybnu 0.3615
tdftrambypwenyb 0.2183
tabayb 0.1040
ttabayb 0.1062
ttenbaybpu 0.2796
ttenbaybnu 0.2792
tdftrambypayb 0.1779
taccqa_rd0 0.6329
taccqa_rd1 0.6338
taccqa_rd2 0.6380
taccqa_rd3 0.6403
taccqa_rd4 0.7004
taccqa_rd5 0.7503
taccqa_rd6 0.8086
taccqa_rd7 0.8592
taccqa_scan0 0.6329
taccqa_scan1 0.6338
taccqa_scan2 0.6380
taccqa_scan3 0.6403
taccqa_scan4 0.7004
taccqa_scan5 0.7503
taccqa_scan6 0.8086
taccqa_scan7 0.8592
tclkasoa_rd0 0.6665
tclkasoa_rd1 0.6674
tclkasoa_rd2 0.6716
tclkasoa_rd3 0.6739
tclkasoa_rd4 0.7340
tclkasoa_rd5 0.7839
tclkasoa_rd6 0.8422
tclkasoa_rd7 0.8928
tclkasoa_scan0 0.6665
tclkasoa_scan1 0.6674
tclkasoa_scan2 0.6716
tclkasoa_scan3 0.6739
tclkasoa_scan4 0.7340
tclkasoa_scan5 0.7839
tclkasoa_scan6 0.8422
tclkasoa_scan7 0.8928
tclkbsob 0.2946
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 2.0800
kload_aya 1.6620
kload_cenyb 1.9640
kload_wenyb 1.7940
kload_ayb 1.6740
kload_qa 0.6365
kload_soa 1.7020
kload_sob 1.8420
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.9287
tcyca_ema1 0.9295
tcyca_ema2 0.9338
tcyca_ema3 0.9362
tcyca_ema4 0.9972
tcyca_ema5 1.0478
tcyca_ema6 1.1069
tcyca_ema7 1.1583
tcycb_ema0 0.9633
tcycb_ema1 0.9742
tcycb_ema2 0.9854
tcycb_ema3 1.0011
tcycb_ema4 1.0743
tcycb_ema5 1.1236
tcycb_ema6 1.1945
tcycb_ema7 1.2454
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.5926
tcracwb_rd1 0.5935
tcracwb_rd2 0.5977
tcracwb_rd3 0.6000
tcracwb_rd4 0.6601
tcracwb_rd5 0.7100
tcracwb_rd6 0.7683
tcracwb_rd7 0.8189
tcwbcra_wr0 0.7392
tcwbcra_wr1 0.7499
tcwbcra_wr2 0.7610
tcwbcra_wr3 0.7764
tcwbcra_wr4 0.8486
tcwbcra_wr5 0.8972
tcwbcra_wr6 0.9670
tcwbcra_wr7 1.0172
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.1133
tckal 0.1135
tckbh 0.1158
tckbl 0.1131
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.1176
taas 0.1265
tcenbs 0.1240
twenbs 0.0225
tabs 0.1337
tdbs 0.0487
temaas 0.9759
temasas 0.9759
temabs 1.0408
ttenas 0.2339
ttcenas 0.1176
ttaas 0.1310
ttenbs 0.4547
ttcenbs 0.1252
ttwenbs 0.0225
ttabs 0.1373
ttdbs 0.0509
tsias 0.2573
tseas 0.2573
tdftrambypas 0.3272
tdftrambypbs 0.3272
tsibs 0.0487
tsebs 0.4547
tcolldisnas 0.9759
tcolldisnbs 1.0408
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0489
tcenaf_ret1nfh 1.0442
tcenaf_ret1nrh 0.3960
taah 0.0821
tcenbh 0.0492
tcenbf_ret1nfh 1.0442
tcenbf_ret1nrh 0.3960
twenbh 0.2057
tabh 0.0765
tdbh 0.1941
temaah 1.2848
temasah 1.2848
temabh 1.2886
ttenah 0.0903
ttcenah 0.0517
ttcenaf_ret1nfh 1.0442
ttcenaf_ret1nrh 0.3960
ttaah 0.0821
ttenbh 0.2271
ttcenbh 0.0507
ttcenbf_ret1nfh 1.0442
ttcenbf_ret1nrh 0.3960
ttwenbh 0.2065
ttabh 0.0765
ttdbh 0.1941
tret1nf_dftrambypfh 0.0313
tret1nr_dftrambypfh 1.0442
tret1nf_cenbrh 0.0313
tret1nf_cenarh 0.0294
tret1nf_tcenarh 0.0294
tret1nf_tcenbrh 0.0313
tret1nr_tcenbrh 1.0442
tret1nr_tcenarh 0.9793
tret1nr_cenbrh 1.0442
tret1nr_cenarh 0.9793
tsiah 0.0817
tseah 1.2848
tdftrambypah 1.2848
tdftrambypbh 1.0442
tdftrambypr_ret1nfh 1.0442
tdftrambypr_ret1nrh 0.3960
tsibh 0.1941
tsebh 0.2271
tcolldisnah 1.2848
tcolldisnbh 1.2886
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0091
icap_cena 0.0013
icap_aa 0.0016
icap_clkb 0.0097
icap_cenb 0.0013
icap_wenb 0.0014
icap_ab 0.0016
icap_db 0.0019
icap_emaa 0.0058
icap_emasa 0.0025
icap_emab 0.0056
icap_tena 0.0009
icap_tcena 0.0014
icap_taa 0.0015
icap_tenb 0.0010
icap_tcenb 0.0014
icap_twenb 0.0012
icap_tab 0.0016
icap_tdb 0.0016
icap_sia 0.0012
icap_sea 0.0016
icap_dftrambyp 0.0021
icap_sib 0.0058
icap_seb 0.0019
icap_colldisn 0.0021
icap_ret1n 0.0034
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 1.670e-03
icc_standby_p_chipdisable 7.547e-03
icc_standby_c_ret1 1.745e-03
icc_standby_p_ret1 4.462e-04
icc_standby_c_selective_precharge 1.641e-03
icc_standby_p_selective_precharge 7.003e-03
icc_c_rd0_a 8.332e-05
icc_c_rd1_a 8.351e-05
icc_c_rd2_a 8.351e-05
icc_c_rd3_a 8.358e-05
icc_c_rd4_a 8.580e-05
icc_c_rd5_a 8.714e-05
icc_c_rd6_a 8.820e-05
icc_c_rd7_a 8.931e-05
icc_p_rd0_a 3.154e-03
icc_p_rd1_a 3.154e-03
icc_p_rd2_a 3.161e-03
icc_p_rd3_a 3.161e-03
icc_p_rd4_a 3.183e-03
icc_p_rd5_a 3.183e-03
icc_p_rd6_a 3.183e-03
icc_p_rd7_a 3.187e-03
icc_c_wr0_b 1.992e-04
icc_c_wr1_b 1.994e-04
icc_c_wr2_b 1.994e-04
icc_c_wr3_b 1.994e-04
icc_c_wr4_b 2.016e-04
icc_c_wr5_b 2.030e-04
icc_c_wr6_b 2.041e-04
icc_c_wr7_b 2.052e-04
icc_p_wr0_b 3.831e-03
icc_p_wr1_b 3.831e-03
icc_p_wr2_b 3.838e-03
icc_p_wr3_b 3.838e-03
icc_p_wr4_b 3.859e-03
icc_p_wr5_b 3.859e-03
icc_p_wr6_b 3.859e-03
icc_p_wr7_b 3.864e-03
icc_c_desela 0.000e+00
icc_p_desela 4.837e-05
icc_c_deselb 0.000e+00
icc_p_deselb 9.985e-04
icc_c_peak 2.960067
icc_p_peak 41.601651
icc_c_inrush 1.662968
icc_p_inrush 38.103734

71102
models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p90v_0p90v_25c.lib Normal file
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models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p90v_0p90v_25c.ps Normal file
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