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code refactoring

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This commit is contained in:
Blaise Tine 2021-04-26 02:34:21 -07:00
parent 8410c49f53
commit 8543e3a8bf
7 changed files with 19 additions and 21 deletions
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2
driver/opae/vlsim/opae_sim.h
View file

@ -17,8 +17,6 @@
#include <list>
#include <unordered_map>
#define MEM_BLOCK_SIZE (PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8)
#define CACHE_BLOCK_SIZE 64
class opae_sim {

8
hw/rtl/VX_config.vh
View file

@ -33,11 +33,11 @@
`define SM_ENABLE 1
`endif
`ifndef GLOBAL_BLOCK_SIZE
`ifdef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH
`define GLOBAL_BLOCK_SIZE (`PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8)
`ifndef MEM_BLOCK_SIZE
`ifdef LOCAL_MEM_DATA_N_BYTES
`define MEM_BLOCK_SIZE `LOCAL_MEM_DATA_N_BYTES
`else
`define GLOBAL_BLOCK_SIZE 64
`define MEM_BLOCK_SIZE 64
`endif
`endif

8
hw/rtl/VX_define.vh
View file

@ -243,7 +243,7 @@
`define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0)
// Block size in bytes
`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE)
`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
// Word size in bytes
`define IWORD_SIZE 4
@ -275,7 +275,7 @@
`define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1)
// Block size in bytes
`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE)
`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
// Word size in bytes
`define DWORD_SIZE 4
@ -324,7 +324,7 @@
`define L2CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID)
// Block size in bytes
`define L2CACHE_LINE_SIZE `GLOBAL_BLOCK_SIZE
`define L2CACHE_LINE_SIZE `MEM_BLOCK_SIZE
// Word size in bytes
`define L2WORD_SIZE `DCACHE_LINE_SIZE
@ -350,7 +350,7 @@
`define L3CACHE_ID 0
// Block size in bytes
`define L3CACHE_LINE_SIZE `GLOBAL_BLOCK_SIZE
`define L3CACHE_LINE_SIZE `MEM_BLOCK_SIZE
// Word size in bytes
`define L3WORD_SIZE `L2CACHE_LINE_SIZE

8
hw/simulate/simulator.cpp
View file

@ -144,7 +144,7 @@ void Simulator::eval_mem_bus() {
if (!mem_rsp_active_) {
if (mem_rsp_it != mem_rsp_vec_.end()) {
vortex_->mem_rsp_valid = 1;
memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), GLOBAL_BLOCK_SIZE);
memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE);
vortex_->mem_rsp_tag = mem_rsp_it->tag;
mem_rsp_vec_.erase(mem_rsp_it);
mem_rsp_active_ = true;
@ -169,9 +169,9 @@ void Simulator::eval_mem_bus() {
if (vortex_->mem_req_valid) {
if (vortex_->mem_req_rw) {
uint64_t byteen = vortex_->mem_req_byteen;
unsigned base_addr = (vortex_->mem_req_addr * GLOBAL_BLOCK_SIZE);
unsigned base_addr = (vortex_->mem_req_addr * MEM_BLOCK_SIZE);
uint8_t* data = (uint8_t*)(vortex_->mem_req_data);
for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
(*ram_)[base_addr + i] = data[i];
}
@ -180,7 +180,7 @@ void Simulator::eval_mem_bus() {
mem_req_t mem_req;
mem_req.tag = vortex_->mem_req_tag;
mem_req.addr = vortex_->mem_req_addr;
ram_->read(vortex_->mem_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, mem_req.block.data());
ram_->read(vortex_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.block.data());
mem_req.cycles_left = MEM_LATENCY;
for (auto& rsp : mem_rsp_vec_) {
if (mem_req.addr == rsp.addr) {

2
hw/simulate/simulator.h
View file

@ -48,7 +48,7 @@ private:
typedef struct {
int cycles_left;
std::array<uint8_t, GLOBAL_BLOCK_SIZE> block;
std::array<uint8_t, MEM_BLOCK_SIZE> block;
uint32_t addr;
uint32_t tag;
} mem_req_t;

10
hw/unit_tests/cache/cachesim.cpp vendored
View file

@ -208,7 +208,7 @@ void CacheSim::eval_mem_bus() {
cache_->mem_rsp_valid = 1;
//copy data from the rsp queue to the cache module
memcpy((uint8_t*)cache_->mem_rsp_data, mem_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
memcpy((uint8_t*)cache_->mem_rsp_data, mem_rsp_vec_[dequeue_index].data, MEM_BLOCK_SIZE);
cache_->mem_rsp_tag = mem_rsp_vec_[dequeue_index].tag;
free(mem_rsp_vec_[dequeue_index].data); //take data out of the queue
@ -235,9 +235,9 @@ void CacheSim::eval_mem_bus() {
if (cache_->mem_req_valid) {
if (cache_->mem_req_rw) { //write = 1
uint64_t byteen = cache_->mem_req_byteen;
unsigned base_addr = (cache_->mem_req_addr * GLOBAL_BLOCK_SIZE);
unsigned base_addr = (cache_->mem_req_addr * MEM_BLOCK_SIZE);
uint8_t* data = (uint8_t*)(cache_->mem_req_data);
for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
(*ram_)[base_addr + i] = data[i];
}
@ -245,9 +245,9 @@ void CacheSim::eval_mem_bus() {
} else {
mem_req_t mem_req;
mem_req.cycles_left = MEM_LATENCY;
mem_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
mem_req.data = (uint8_t*)malloc(MEM_BLOCK_SIZE);
mem_req.tag = cache_->mem_req_tag;
ram_->read(cache_->mem_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, mem_req.data);
ram_->read(cache_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data);
mem_rsp_vec_.push_back(mem_req);
}
}

2
hw/unit_tests/cache/cachesim.h vendored
View file

@ -18,7 +18,7 @@
#define MEM_LATENCY 100
#define MEM_RQ_SIZE 16
#define MEM_STALLS_MODULO 16
#define GLOBAL_BLOCK_SIZE 16
#define MEM_BLOCK_SIZE 16
typedef struct {
int cycles_left;