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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
minor updates
This commit is contained in:
parent
78e7b9cf67
commit
86bf894a1d
8 changed files with 42 additions and 41 deletions
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@ -142,16 +142,16 @@
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end \
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`TRACE(lvl, ("}"))
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`define RESET_RELAY_EX(dst, src, depth) \
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wire dst; \
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VX_reset_relay #(.DEPTH(depth)) __``dst ( \
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.clk (clk), \
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.reset (src), \
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.reset_o (dst) \
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`define RESET_RELAY_EX(dst, src, size, fanout) \
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wire [size-1:0] dst; \
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VX_reset_relay #(.N(size), .MAX_FANOUT(fanout)) __``dst ( \
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.clk (clk), \
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.reset (src), \
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.reset_o (dst) \
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)
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`define RESET_RELAY(dst, src) \
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`RESET_RELAY_EX (dst, src, 1)
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`RESET_RELAY_EX (dst, src, 1, 0)
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`define POP_COUNT(out, in) \
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VX_popcount #( \
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2
hw/rtl/cache/VX_cache.sv
vendored
2
hw/rtl/cache/VX_cache.sv
vendored
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@ -110,7 +110,7 @@ module VX_cache #(
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
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wire [NUM_REQS-1:0] core_rsp_ready_s;
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`RESET_RELAY_EX (core_rsp_reset, reset, CORE_REQ_BUF_ENABLE && (CORE_OUT_REG != 0) && (NUM_REQS > 1));
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`RESET_RELAY_EX (core_rsp_reset, reset, 1, (NUM_REQS > 1) ? 0 : -1);
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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VX_generic_buffer #(
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4
hw/rtl/cache/VX_cache_cluster.sv
vendored
4
hw/rtl/cache/VX_cache_cluster.sv
vendored
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@ -104,7 +104,7 @@ module VX_cache_cluster #(
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.TAG_WIDTH (ARB_TAG_WIDTH)
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) arb_core_rsp_if[NUM_CACHES]();
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`RESET_RELAY_EX (cache_arb_reset, reset, (NUM_INPUTS != NUM_CACHES));
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`RESET_RELAY (cache_arb_reset, reset);
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VX_cache_arb #(
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.NUM_INPUTS (NUM_INPUTS),
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@ -183,7 +183,7 @@ module VX_cache_cluster #(
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);
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end
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`RESET_RELAY_EX (mem_arb_reset, reset, (NUM_CACHES > 1));
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`RESET_RELAY (mem_arb_reset, reset);
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VX_mem_arb #(
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.NUM_REQS (NUM_CACHES),
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2
hw/rtl/cache/VX_cache_wrap.sv
vendored
2
hw/rtl/cache/VX_cache_wrap.sv
vendored
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@ -120,7 +120,7 @@ module VX_cache_wrap #(
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
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wire [NUM_REQS-1:0] core_rsp_ready_s;
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`RESET_RELAY_EX (core_rsp_reset, reset, (NC_BYPASS && !DIRECT_PASSTHRU) && (CORE_OUT_REG != 0) && (NUM_REQS > 1));
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`RESET_RELAY_EX (core_rsp_reset, reset, 1, (NUM_REQS > 1) ? 0 : -1);
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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VX_generic_buffer #(
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@ -2,27 +2,23 @@
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`TRACING_OFF
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module VX_reset_relay #(
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parameter N = 1,
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parameter DEPTH = 1
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parameter N = 1,
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parameter MAX_FANOUT = 0
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) (
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input wire clk,
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input wire reset,
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output wire [N-1:0] reset_o
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);
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if (DEPTH > 1) begin
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`PRESERVE_REG `DISABLE_BRAM reg [N-1:0] reset_r [DEPTH-1:0];
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if (N > MAX_FANOUT && MAX_FANOUT > 0) begin
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localparam F = `UP(MAX_FANOUT);
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localparam R = N / F;
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reg [R-1:0] reset_r;
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always @(posedge clk) begin
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for (integer i = DEPTH-1; i > 0; --i)
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reset_r[i] <= reset_r[i-1];
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reset_r[0] <= {N{reset}};
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end
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assign reset_o = reset_r[DEPTH-1];
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end else if (DEPTH == 1) begin
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`PRESERVE_REG reg [N-1:0] reset_r;
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always @(posedge clk) begin
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reset_r <= {N{reset}};
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reset_r <= {R{reset}};
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end
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for (genvar i = 0; i < N; ++i) begin
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assign reset_o[i] = reset_r[i / F];
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end
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assign reset_o = reset_r;
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end else begin
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`UNUSED_VAR (clk)
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assign reset_o = {N{reset}};
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@ -34,7 +34,7 @@ module VX_stream_arb #(
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localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_INPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (BATCH_SIZE),
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@ -71,7 +71,7 @@ module VX_stream_arb #(
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localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_INPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (BATCH_SIZE),
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@ -162,7 +162,7 @@ module VX_stream_arb #(
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assign ready_in[i] = ready_out_r & {NUM_LANES{arb_onehot[i]}};
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end
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`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && NUM_LANES > MAX_FANOUT);
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`RESET_RELAY_EX (out_buf_reset, reset, NUM_LANES, MAX_FANOUT);
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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VX_skid_buffer #(
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@ -171,7 +171,7 @@ module VX_stream_arb #(
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.OUT_REG (BUFFERED > 1)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.reset (out_buf_reset[i]),
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.valid_in (valid_out_r[i]),
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.data_in (data_out_r[i]),
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.ready_in (ready_out_r[i]),
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@ -194,7 +194,7 @@ module VX_stream_arb #(
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localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_OUTPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (1),
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@ -251,7 +251,7 @@ module VX_stream_arb #(
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localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_OUTPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (1),
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@ -315,17 +315,18 @@ module VX_stream_arb #(
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assign arb_unlock = valid_in & ready_in;
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end
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`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_REQS * NUM_LANES) > MAX_FANOUT);
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`RESET_RELAY_EX (out_buf_reset, reset, (NUM_REQS * NUM_LANES), MAX_FANOUT);
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < NUM_LANES; ++j) begin
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localparam ii = i * NUM_LANES + j;
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VX_skid_buffer #(
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.DATAW (DATAW),
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.PASSTHRU (BUFFERED == 0),
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.OUT_REG (BUFFERED > 1)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.reset (out_buf_reset[ii]),
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.valid_in (valid_in[0][j] && arb_onehot[i]),
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.ready_in (ready_out_r[i][j]),
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.data_in (data_in[0][j]),
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end else begin
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`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
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`RESET_RELAY_EX (out_buf_reset, reset, (NUM_OUTPUTS * NUM_LANES), MAX_FANOUT);
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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for (genvar j = 0; j < NUM_LANES; ++j) begin
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localparam ii = i * NUM_LANES + j;
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VX_skid_buffer #(
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.DATAW (DATAW),
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.PASSTHRU (BUFFERED == 0),
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.OUT_REG (BUFFERED > 1)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.reset (out_buf_reset[ii]),
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.valid_in (valid_in[i][j]),
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.ready_in (ready_in[i][j]),
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.data_in (data_in[i][j]),
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@ -62,17 +62,18 @@ module VX_stream_switch #(
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end
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end
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`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
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`RESET_RELAY_EX (out_buf_reset, reset, (NUM_OUTPUTS * NUM_LANES), MAX_FANOUT);
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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for (genvar j = 0; j < NUM_LANES; ++j) begin
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localparam ii = i * NUM_LANES + j;
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VX_skid_buffer #(
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.DATAW (DATAW),
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.PASSTHRU (BUFFERED == 0),
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.OUT_REG (BUFFERED > 1)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.reset (out_buf_reset[ii]),
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.valid_in (valid_out_r[i][j]),
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.ready_in (ready_out_r[i][j]),
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.data_in (data_out_r[i][j]),
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assign ready_in[i] = ready_out_r[i][sel_in[i]];
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end
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`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
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`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, MAX_FANOUT);
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for (genvar i = 0; i < NUM_INPUTS; ++i) begin
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for (genvar j = 0; j < NUM_REQS; ++j) begin
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.OUT_REG (BUFFERED > 1)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.reset (out_buf_reset[ii]),
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.valid_in (valid_out_r[i][j][k]),
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.ready_in (ready_out_r[i][j][k]),
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.data_in (data_in[i][k]),
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`UNUSED_VAR (sel_in)
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`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
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`RESET_RELAY_EX (out_buf_reset, reset, (NUM_OUTPUTS * NUM_LANES), MAX_FANOUT);
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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for (genvar j = 0; j < NUM_LANES; ++j) begin
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localparam ii = i * NUM_LANES + j;
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VX_skid_buffer #(
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.DATAW (DATAW),
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.PASSTHRU (BUFFERED == 0),
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.OUT_REG (BUFFERED > 1)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.reset (out_buf_reset[ii]),
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.valid_in (valid_in[i][j]),
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.ready_in (ready_in[i][j]),
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.data_in (data_in[i][j]),
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@ -22,6 +22,7 @@ draw3d(){
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echo -e "\n**************************************\n" >> $LOG_FILE
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echo -e "draw3d $trace benchmark\n" >> $LOG_FILE
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CONFIGS="-DEXT_GFX_ENABLE" ./ci/blackbox.sh --driver=fpga --app=draw3d --args="-t$trace.cgltrace -w${WIDTH} -h${HEIGHT}" | grep 'Total elapsed time:' >> $LOG_FILE
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cp tests/regression/draw3d/output.png ${LOG_DIR}/perf_${TOKEN}_$trace.png
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done
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echo "draw3d tests done!"
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}
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