minor updates

This commit is contained in:
Blaise Tine 2022-08-17 21:02:13 -07:00
parent 78e7b9cf67
commit 86bf894a1d
8 changed files with 42 additions and 41 deletions

View file

@ -142,16 +142,16 @@
end \
`TRACE(lvl, ("}"))
`define RESET_RELAY_EX(dst, src, depth) \
wire dst; \
VX_reset_relay #(.DEPTH(depth)) __``dst ( \
.clk (clk), \
.reset (src), \
.reset_o (dst) \
`define RESET_RELAY_EX(dst, src, size, fanout) \
wire [size-1:0] dst; \
VX_reset_relay #(.N(size), .MAX_FANOUT(fanout)) __``dst ( \
.clk (clk), \
.reset (src), \
.reset_o (dst) \
)
`define RESET_RELAY(dst, src) \
`RESET_RELAY_EX (dst, src, 1)
`RESET_RELAY_EX (dst, src, 1, 0)
`define POP_COUNT(out, in) \
VX_popcount #( \

View file

@ -110,7 +110,7 @@ module VX_cache #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
wire [NUM_REQS-1:0] core_rsp_ready_s;
`RESET_RELAY_EX (core_rsp_reset, reset, CORE_REQ_BUF_ENABLE && (CORE_OUT_REG != 0) && (NUM_REQS > 1));
`RESET_RELAY_EX (core_rsp_reset, reset, 1, (NUM_REQS > 1) ? 0 : -1);
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_generic_buffer #(

View file

@ -104,7 +104,7 @@ module VX_cache_cluster #(
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_rsp_if[NUM_CACHES]();
`RESET_RELAY_EX (cache_arb_reset, reset, (NUM_INPUTS != NUM_CACHES));
`RESET_RELAY (cache_arb_reset, reset);
VX_cache_arb #(
.NUM_INPUTS (NUM_INPUTS),
@ -183,7 +183,7 @@ module VX_cache_cluster #(
);
end
`RESET_RELAY_EX (mem_arb_reset, reset, (NUM_CACHES > 1));
`RESET_RELAY (mem_arb_reset, reset);
VX_mem_arb #(
.NUM_REQS (NUM_CACHES),

View file

@ -120,7 +120,7 @@ module VX_cache_wrap #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
wire [NUM_REQS-1:0] core_rsp_ready_s;
`RESET_RELAY_EX (core_rsp_reset, reset, (NC_BYPASS && !DIRECT_PASSTHRU) && (CORE_OUT_REG != 0) && (NUM_REQS > 1));
`RESET_RELAY_EX (core_rsp_reset, reset, 1, (NUM_REQS > 1) ? 0 : -1);
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_generic_buffer #(

View file

@ -2,27 +2,23 @@
`TRACING_OFF
module VX_reset_relay #(
parameter N = 1,
parameter DEPTH = 1
parameter N = 1,
parameter MAX_FANOUT = 0
) (
input wire clk,
input wire reset,
output wire [N-1:0] reset_o
);
if (DEPTH > 1) begin
`PRESERVE_REG `DISABLE_BRAM reg [N-1:0] reset_r [DEPTH-1:0];
if (N > MAX_FANOUT && MAX_FANOUT > 0) begin
localparam F = `UP(MAX_FANOUT);
localparam R = N / F;
reg [R-1:0] reset_r;
always @(posedge clk) begin
for (integer i = DEPTH-1; i > 0; --i)
reset_r[i] <= reset_r[i-1];
reset_r[0] <= {N{reset}};
end
assign reset_o = reset_r[DEPTH-1];
end else if (DEPTH == 1) begin
`PRESERVE_REG reg [N-1:0] reset_r;
always @(posedge clk) begin
reset_r <= {N{reset}};
reset_r <= {R{reset}};
end
for (genvar i = 0; i < N; ++i) begin
assign reset_o[i] = reset_r[i / F];
end
assign reset_o = reset_r;
end else begin
`UNUSED_VAR (clk)
assign reset_o = {N{reset}};

View file

@ -34,7 +34,7 @@ module VX_stream_arb #(
localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_INPUTS);
localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (BATCH_SIZE),
@ -71,7 +71,7 @@ module VX_stream_arb #(
localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_INPUTS);
localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (BATCH_SIZE),
@ -162,7 +162,7 @@ module VX_stream_arb #(
assign ready_in[i] = ready_out_r & {NUM_LANES{arb_onehot[i]}};
end
`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && NUM_LANES > MAX_FANOUT);
`RESET_RELAY_EX (out_buf_reset, reset, NUM_LANES, MAX_FANOUT);
for (genvar i = 0; i < NUM_LANES; ++i) begin
VX_skid_buffer #(
@ -171,7 +171,7 @@ module VX_stream_arb #(
.OUT_REG (BUFFERED > 1)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
.reset (out_buf_reset[i]),
.valid_in (valid_out_r[i]),
.data_in (data_out_r[i]),
.ready_in (ready_out_r[i]),
@ -194,7 +194,7 @@ module VX_stream_arb #(
localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_OUTPUTS);
localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (1),
@ -251,7 +251,7 @@ module VX_stream_arb #(
localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_OUTPUTS);
localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
`RESET_RELAY_EX (slice_reset, reset, BUFFERED != 0);
`RESET_RELAY (slice_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (1),
@ -315,17 +315,18 @@ module VX_stream_arb #(
assign arb_unlock = valid_in & ready_in;
end
`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_REQS * NUM_LANES) > MAX_FANOUT);
`RESET_RELAY_EX (out_buf_reset, reset, (NUM_REQS * NUM_LANES), MAX_FANOUT);
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
localparam ii = i * NUM_LANES + j;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (BUFFERED == 0),
.OUT_REG (BUFFERED > 1)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
.reset (out_buf_reset[ii]),
.valid_in (valid_in[0][j] && arb_onehot[i]),
.ready_in (ready_out_r[i][j]),
.data_in (data_in[0][j]),
@ -339,17 +340,18 @@ module VX_stream_arb #(
end else begin
`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
`RESET_RELAY_EX (out_buf_reset, reset, (NUM_OUTPUTS * NUM_LANES), MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
localparam ii = i * NUM_LANES + j;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (BUFFERED == 0),
.OUT_REG (BUFFERED > 1)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
.reset (out_buf_reset[ii]),
.valid_in (valid_in[i][j]),
.ready_in (ready_in[i][j]),
.data_in (data_in[i][j]),

View file

@ -62,17 +62,18 @@ module VX_stream_switch #(
end
end
`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
`RESET_RELAY_EX (out_buf_reset, reset, (NUM_OUTPUTS * NUM_LANES), MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
localparam ii = i * NUM_LANES + j;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (BUFFERED == 0),
.OUT_REG (BUFFERED > 1)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
.reset (out_buf_reset[ii]),
.valid_in (valid_out_r[i][j]),
.ready_in (ready_out_r[i][j]),
.data_in (data_out_r[i][j]),
@ -95,7 +96,7 @@ module VX_stream_switch #(
assign ready_in[i] = ready_out_r[i][sel_in[i]];
end
`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
`RESET_RELAY_EX (out_buf_reset, reset, NUM_OUTPUTS, MAX_FANOUT);
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
@ -108,7 +109,7 @@ module VX_stream_switch #(
.OUT_REG (BUFFERED > 1)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
.reset (out_buf_reset[ii]),
.valid_in (valid_out_r[i][j][k]),
.ready_in (ready_out_r[i][j][k]),
.data_in (data_in[i][k]),
@ -128,17 +129,18 @@ module VX_stream_switch #(
`UNUSED_VAR (sel_in)
`RESET_RELAY_EX (out_buf_reset, reset, BUFFERED != 0 && (NUM_OUTPUTS * NUM_LANES) > MAX_FANOUT);
`RESET_RELAY_EX (out_buf_reset, reset, (NUM_OUTPUTS * NUM_LANES), MAX_FANOUT);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
localparam ii = i * NUM_LANES + j;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (BUFFERED == 0),
.OUT_REG (BUFFERED > 1)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
.reset (out_buf_reset[ii]),
.valid_in (valid_in[i][j]),
.ready_in (ready_in[i][j]),
.data_in (data_in[i][j]),

View file

@ -22,6 +22,7 @@ draw3d(){
echo -e "\n**************************************\n" >> $LOG_FILE
echo -e "draw3d $trace benchmark\n" >> $LOG_FILE
CONFIGS="-DEXT_GFX_ENABLE" ./ci/blackbox.sh --driver=fpga --app=draw3d --args="-t$trace.cgltrace -w${WIDTH} -h${HEIGHT}" | grep 'Total elapsed time:' >> $LOG_FILE
cp tests/regression/draw3d/output.png ${LOG_DIR}/perf_${TOKEN}_$trace.png
done
echo "draw3d tests done!"
}