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This commit is contained in:
Blaise Tine 2020-03-26 04:19:53 -04:00
commit 8763adf7bc
10 changed files with 402 additions and 145 deletions
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3
.gitignore vendored
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@ -4,5 +4,6 @@
./rtl/modelsim/*.vcd
*.vcd
.*
!.gitignore
*.pyc
__pycache__
__pycache__

4
rtl/.gitignore vendored Normal file
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@ -0,0 +1,4 @@
/simulate/VX_define.h
/simulate/VX_define_synth.h
/VX_define_synth.v
/results.txt

4
rtl/Makefile
View file

@ -30,6 +30,10 @@ MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
.PHONY: build_config
build_config:
./gen_config.py --rtl_locations
# -LDFLAGS '-lsystemc'
VERILATOR:
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW)

268
rtl/VX_define.v
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@ -3,6 +3,22 @@
`include "./VX_define_synth.v"
`ifndef NT
`define NT 4
`endif
`ifndef NW
`define NW 8
`endif
`ifndef NUMBER_CORES_PER_CLUSTER
`define NUMBER_CORES_PER_CLUSTER 2
`endif
`ifndef NUMBER_CLUSTERS
`define NUMBER_CLUSTERS 1
`endif
// `define QUEUE_FORCE_MLAB 1
// `define L3C 1
`define NT_M1 (`NT-1)
// NW_M1 is actually log2(NW)
@ -15,7 +31,9 @@
// `define ASIC 1
// `define SYN_FUNC 1
`ifndef NUM_BARRIERS
`define NUM_BARRIERS 4
`endif
`define R_INST 7'd51
`define L_INST 7'd3
@ -105,8 +123,8 @@
`define NO_STALL 1'h0
`define TAKEN 1'b1
`define NOT_TAKEN 1'b0
`define TAKEN 1'h1
`define NOT_TAKEN 1'h0
`define ZERO_REG 5'h0
@ -125,59 +143,105 @@
-199
`ifndef NUMBER_CORES
`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
`endif
//`define SINGLE_CORE_BENCH
// `define SINGLE_CORE_BENCH
`ifndef GLOBAL_BLOCK_SIZE_BYTES
`define GLOBAL_BLOCK_SIZE_BYTES 16
`endif
// ========================================= Dcache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef DCACHE_SIZE_BYTES
`define DCACHE_SIZE_BYTES 4096
`endif
// Size of line inside a bank in bytes
`ifndef DBANK_LINE_SIZE_BYTES
`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef DNUMBER_BANKS
`define DNUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef DWORD_SIZE_BYTES
`define DWORD_SIZE_BYTES 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef DNUMBER_REQUESTS
`define DNUMBER_REQUESTS `NT
`endif
// Number of cycles to complete stage 1 (read from memory)
`define DSTAGE_1_CYCLES 1
`ifndef DSTAGE_1_CYCLES
`define DSTAGE_1_CYCLES 2
`endif
// Function ID
`ifndef DFUNC_ID
`define DFUNC_ID 0
`endif
// Bank Number of words in a line
`ifndef DBANK_LINE_SIZE_WORDS
`define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES)
`endif
`ifndef DBANK_LINE_SIZE_RNG
`define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef DREQQ_SIZE
`define DREQQ_SIZE `NW
`endif
// Miss Reserv Queue Knob
`ifndef DMRVQ_SIZE
`define DMRVQ_SIZE (`NW*`NT)
`endif
// Dram Fill Rsp Queue Size
`ifndef DDFPQ_SIZE
`define DDFPQ_SIZE 2
`endif
// Snoop Req Queue
`ifndef DSNRQ_SIZE
`define DSNRQ_SIZE 8
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef DCWBQ_SIZE
`define DCWBQ_SIZE `DREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef DDWBQ_SIZE
`define DDWBQ_SIZE 4
`endif
// Dram Fill Req Queue Size
`ifndef DDFQQ_SIZE
`define DDFQQ_SIZE `DREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef DLLVQ_SIZE
`define DLLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`ifndef DFFSQ_SIZE
`define DFFSQ_SIZE 8
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`define DFILL_INVALIDAOR_SIZE 0
`ifndef DFILL_INVALIDAOR_SIZE
`define DFILL_INVALIDAOR_SIZE 16
`endif
// Dram knobs
`ifndef DSIMULATED_DRAM_LATENCY_CYCLES
`define DSIMULATED_DRAM_LATENCY_CYCLES 10
`endif
// ========================================= Dcache Configurable Knobs =========================================
@ -185,50 +249,92 @@
// ========================================= Icache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef ICACHE_SIZE_BYTES
`define ICACHE_SIZE_BYTES 1024
`endif
// Size of line inside a bank in bytes
`ifndef IBANK_LINE_SIZE_BYTES
`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef INUMBER_BANKS
`define INUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef IWORD_SIZE_BYTES
`define IWORD_SIZE_BYTES 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef INUMBER_REQUESTS
`define INUMBER_REQUESTS 1
`endif
// Number of cycles to complete stage 1 (read from memory)
`define ISTAGE_1_CYCLES 1
`ifndef ISTAGE_1_CYCLES
`define ISTAGE_1_CYCLES 2
`endif
// Function ID
`ifndef IFUNC_ID
`define IFUNC_ID 1
`endif
// Bank Number of words in a line
`ifndef IBANK_LINE_SIZE_WORDS
`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
`endif
`ifndef IBANK_LINE_SIZE_RNG
`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef IREQQ_SIZE
`define IREQQ_SIZE `NW
`endif
// Miss Reserv Queue Knob
`ifndef IMRVQ_SIZE
`define IMRVQ_SIZE `IREQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`ifndef IDFPQ_SIZE
`define IDFPQ_SIZE 2
`endif
// Snoop Req Queue
`ifndef ISNRQ_SIZE
`define ISNRQ_SIZE 8
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef ICWBQ_SIZE
`define ICWBQ_SIZE `IREQQ_SIZE
`endif
// Dram Writeback Queue Size
`define IDWBQ_SIZE 16
`ifndef IDWBQ_SIZE
`define IDWBQ_SIZE 0
`endif
// Dram Fill Req Queue Size
`ifndef IDFQQ_SIZE
`define IDFQQ_SIZE `IREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`define ILLVQ_SIZE 16
`ifndef ILLVQ_SIZE
`define ILLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`ifndef IFFSQ_SIZE
`define IFFSQ_SIZE 8
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`define IFILL_INVALIDAOR_SIZE 0
`ifndef IFILL_INVALIDAOR_SIZE
`define IFILL_INVALIDAOR_SIZE 16
`endif
// Dram knobs
`ifndef ISIMULATED_DRAM_LATENCY_CYCLES
`define ISIMULATED_DRAM_LATENCY_CYCLES 10
`endif
// ========================================= Icache Configurable Knobs =========================================
@ -236,51 +342,91 @@
// General Cache Knobs
// Size of cache in bytes
`ifndef SCACHE_SIZE_BYTES
`define SCACHE_SIZE_BYTES 1024
`endif
// Size of line inside a bank in bytes
`ifndef SBANK_LINE_SIZE_BYTES
`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef SNUMBER_BANKS
`define SNUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef SWORD_SIZE_BYTES
`define SWORD_SIZE_BYTES 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef SNUMBER_REQUESTS
`define SNUMBER_REQUESTS `NT
`endif
// Number of cycles to complete stage 1 (read from memory)
`define SSTAGE_1_CYCLES 1
`ifndef SSTAGE_1_CYCLES
`define SSTAGE_1_CYCLES 2
`endif
// Function ID
`ifndef SFUNC_ID
`define SFUNC_ID 2
`endif
// Bank Number of words in a line
`ifndef SBANK_LINE_SIZE_WORDS
`define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
`endif
`ifndef SBANK_LINE_SIZE_RNG
`define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef SREQQ_SIZE
`define SREQQ_SIZE `NW
`endif
// Miss Reserv Queue Knob
`ifndef SMRVQ_SIZE
`define SMRVQ_SIZE `SREQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`define SDFPQ_SIZE 16
`ifndef SDFPQ_SIZE
`define SDFPQ_SIZE 0
`endif
// Snoop Req Queue
`define SSNRQ_SIZE 16
`ifndef SSNRQ_SIZE
`define SSNRQ_SIZE 0
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef SCWBQ_SIZE
`define SCWBQ_SIZE `SREQQ_SIZE
`endif
// Dram Writeback Queue Size
`define SDWBQ_SIZE 16
`ifndef SDWBQ_SIZE
`define SDWBQ_SIZE 0
`endif
// Dram Fill Req Queue Size
`define SDFQQ_SIZE 16
`ifndef SDFQQ_SIZE
`define SDFQQ_SIZE 0
`endif
// Lower Level Cache Hit Queue Size
`define SLLVQ_SIZE 16
`ifndef SLLVQ_SIZE
`define SLLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`define SFFSQ_SIZE 16
`ifndef SFFSQ_SIZE
`define SFFSQ_SIZE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`define SFILL_INVALIDAOR_SIZE 0
`ifndef SFILL_INVALIDAOR_SIZE
`define SFILL_INVALIDAOR_SIZE 16
`endif
// Dram knobs
`ifndef SSIMULATED_DRAM_LATENCY_CYCLES
`define SSIMULATED_DRAM_LATENCY_CYCLES 10
`endif
// ========================================= SM Configurable Knobs =========================================
@ -289,50 +435,90 @@
// ========================================= L2cache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef LLCACHE_SIZE_BYTES
`define LLCACHE_SIZE_BYTES 1024
`endif
// Size of line inside a bank in bytes
`ifndef LLBANK_LINE_SIZE_BYTES
`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef LLNUMBER_BANKS
`define LLNUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef LLWORD_SIZE_BYTES
`define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES)
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef LLNUMBER_REQUESTS
`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER)
`endif
// Number of cycles to complete stage 1 (read from memory)
`define LLSTAGE_1_CYCLES 1
`ifndef LLSTAGE_1_CYCLES
`define LLSTAGE_1_CYCLES 2
`endif
// Function ID
`define LLFUNC_ID 3
// Bank Number of words in a line
`ifndef LLBANK_LINE_SIZE_WORDS
`define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES)
`endif
`ifndef LLBANK_LINE_SIZE_RNG
`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef LLREQQ_SIZE
`define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER)
`endif
// Miss Reserv Queue Knob
`ifndef LLMRVQ_SIZE
`define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER)
`endif
// Dram Fill Rsp Queue Size
`ifndef LLDFPQ_SIZE
`define LLDFPQ_SIZE 2
`endif
// Snoop Req Queue
`ifndef LLSNRQ_SIZE
`define LLSNRQ_SIZE 8
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef LLCWBQ_SIZE
`define LLCWBQ_SIZE `LLREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef LLDWBQ_SIZE
`define LLDWBQ_SIZE 4
`endif
// Dram Fill Req Queue Size
`ifndef LLDFQQ_SIZE
`define LLDFQQ_SIZE `LLREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`define LLLLVQ_SIZE 16
`ifndef LLLLVQ_SIZE
`define LLLLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`ifndef LLFFSQ_SIZE
`define LLFFSQ_SIZE 8
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`define LLFILL_INVALIDAOR_SIZE 0
`ifndef LLFILL_INVALIDAOR_SIZE
`define LLFILL_INVALIDAOR_SIZE 16
`endif
// Dram knobs
`ifndef LLSIMULATED_DRAM_LATENCY_CYCLES
`define LLSIMULATED_DRAM_LATENCY_CYCLES 10
`endif
// ========================================= L2cache Configurable Knobs =========================================
@ -340,51 +526,89 @@
// ========================================= L3cache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef L3CACHE_SIZE_BYTES
`define L3CACHE_SIZE_BYTES 1024
`endif
// Size of line inside a bank in bytes
`ifndef L3BANK_LINE_SIZE_BYTES
`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef L3NUMBER_BANKS
`define L3NUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef L3WORD_SIZE_BYTES
`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES)
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef L3NUMBER_REQUESTS
`define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS)
`endif
// Number of cycles to complete stage 1 (read from memory)
`define L3STAGE_1_CYCLES 1
`ifndef L3STAGE_1_CYCLES
`define L3STAGE_1_CYCLES 2
`endif
// Function ID
`define L3FUNC_ID 3
// Bank Number of words in a line
`ifndef L3BANK_LINE_SIZE_WORDS
`define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
`endif
`ifndef L3BANK_LINE_SIZE_RNG
`define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef L3REQQ_SIZE
`define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS)
`endif
// Miss Reserv Queue Knob
`ifndef L3MRVQ_SIZE
`define L3MRVQ_SIZE `LLREQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`ifndef L3DFPQ_SIZE
`define L3DFPQ_SIZE 2
`endif
// Snoop Req Queue
`ifndef L3SNRQ_SIZE
`define L3SNRQ_SIZE 8
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef L3CWBQ_SIZE
`define L3CWBQ_SIZE `L3REQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef L3DWBQ_SIZE
`define L3DWBQ_SIZE 4
`endif
// Dram Fill Req Queue Size
`ifndef L3DFQQ_SIZE
`define L3DFQQ_SIZE `L3REQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef L3LLVQ_SIZE
`define L3LLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`ifndef L3FFSQ_SIZE
`define L3FFSQ_SIZE 8
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`define L3FILL_INVALIDAOR_SIZE 0
`ifndef L3FILL_INVALIDAOR_SIZE
`define L3FILL_INVALIDAOR_SIZE 16
`endif
// Dram knobs
`ifndef L3SIMULATED_DRAM_LATENCY_CYCLES
`define L3SIMULATED_DRAM_LATENCY_CYCLES 10
`endif
// ========================================= L3cache Configurable Knobs =========================================

20
rtl/VX_define_synth.v
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@ -1,20 +0,0 @@
`ifndef VX_DEFINE_SYNTH
`define VX_DEFINE_SYNTH
`define NT 8
`define NW 8
`define NUMBER_CORES_PER_CLUSTER 1
`define NUMBER_CLUSTERS 1
`define DCACHE_SIZE_BYTES 4096
`define ICACHE_SIZE_BYTES 1024
// L2 Cache size
`define LLCACHE_SIZE_BYTES 8192
// `define QUEUE_FORCE_MLAB 1
// Use l3 cache (required for cluster behavior)
// `define L3C 1
`endif

139
rtl/gen_config.py Executable file
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@ -0,0 +1,139 @@
#!/usr/bin/env python3
# coding=utf-8
from __future__ import print_function
import os
import os.path as path
import re
import argparse
from datetime import datetime
rtl_root = path.dirname(path.realpath(__file__))
defines = {}
for k, v in os.environ.items():
if k.upper().startswith('V_'):
defines[k[2:]] = v
print('Custom params:', ', '.join(['='.join(x) for x in defines.items()]))
parser = argparse.ArgumentParser()
parser.add_argument('--outc', default='none', help='Output C header')
parser.add_argument('--outv', default='none', help='Output Verilog header')
parser.add_argument('--rtl_locations', action='store_true', help='use outc and outv for rtl and rtl/simulate')
args = parser.parse_args()
if args.rtl_locations:
args.outc = path.join(rtl_root, 'simulate/VX_define.h')
args.outv = path.join(rtl_root, 'VX_define_synth.v')
if args.outc == 'none' and args.outv == 'none':
print('Warning: not emitting any files. Specify arguments')
if args.outv != 'none':
with open(args.outv, 'w') as f:
print('''
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at {date}
`ifndef VX_DEFINE_SYNTH
`define VX_DEFINE_SYNTH
'''[1:].format(date=datetime.now()), file=f)
for k, v in defines.items():
print('`define {} {}'.format(k, v), file=f)
print('\n`endif', file=f)
if args.outc != 'none':
with open(args.outc, 'w') as f:
print('''
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at {date}
#ifndef VX_DEFINE_SYNTH
#define VX_DEFINE_SYNTH
'''[1:].format(date=datetime.now()), file=f)
for k, v in defines.items():
print('#define {} {}'.format(k, v), file=f)
print('\n#endif', file=f)
translation_rules = [
(re.compile(r'^$'), r''),
(re.compile(r'^( *)`ifndef ([^ ]+)$'), r'\1#ifndef \2'),
(re.compile(r'^( *)`define ([^ ]+)$'), r'\1#define \2'),
# (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r'\1#include "VX_define_synth.h"'),
(re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r''),
(re.compile(r'^( *)`define ([^ ]+) (.+)$'), r'\1#define \2 \3'),
(re.compile(r'^( *)`endif$'), r'\1#endif'),
(re.compile(r'^( *)// (.*)$'), r'\1// \2'),
]
post_rules = [
(re.compile(r"\d+'d(\d+)"), r'\1'),
# non-standard C but supported by GCC and Clang
(re.compile(r"\d+'b([01]+)"), r'0b\1'),
(re.compile(r"\d+'h([\da-fA-F]+)"), r'0x\1'),
# fix macro references (does not support escaped identifiers §5.6.1)
(re.compile(r"`([A-Za-z_][$_0-9A-Za-z]*)"), r'\1'),
]
def post_process_line(line):
for pat, repl in post_rules:
line = pat.sub(repl, line)
return line
in_expansion = False
if args.outc != 'none':
with open(args.outc, 'a') as f:
print('''
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at {date}
// Translated from VX_define.v:
'''[1:].format(date=datetime.now()), file=f)
with open(path.join(rtl_root, 'VX_define.v'), 'r') as r:
for line in r:
if in_expansion:
f.write(post_process_line(line))
if not line.strip().endswith('\\'):
in_expansion = False
else:
for pat, repl in translation_rules:
if pat.match(line):
if line.strip().endswith('\\'):
in_expansion = True
f.write(post_process_line(pat.sub(repl, line)))
break
else:
raise ValueError('failed to find rule for: ' + line)
print('''
// Misc
#define THREADS_PER_WARP NT
#define WARPS_PER_CORE NW
#define NUMBER_WI (NW * NT * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS)
// legacy
#define TOTAL_THREADS NUMBER_WI
#define TOTAL_WARPS (NW * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS)
// COLORS
#define GREEN "\\033[32m"
#define RED "\\033[31m"
#define DEFAULT "\\033[39m"
'''[1:], file=f)

100
rtl/simulate/VX_define.h
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@ -1,100 +0,0 @@
#define NT 4
#define NT_M1 (NT-1)
#define NW 8
#define CACHE_NUM_BANKS 8
#define CACHE_WORDS_PER_BLOCK 4
#define R_INST 51
#define L_INST 3
#define ALU_INST 19
#define S_INST 35
#define B_INST 99
#define LUI_INST 55
#define AUIPC_INST 23
#define JAL_INST 111
#define JALR_INST 103
#define SYS_INST 115
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
#define RS2_IMMED 1
#define RS2_REG 0
#define NO_MEM_READ 7
#define LB_MEM_READ 0
#define LH_MEM_READ 1
#define LW_MEM_READ 2
#define LBU_MEM_READ 4
#define LHU_MEM_READ 5
#define NO_MEM_WRITE 7
#define SB_MEM_WRITE 0
#define SH_MEM_WRITE 1
#define SW_MEM_WRITE 2
#define NO_BRANCH 0
#define BEQ 1
#define BNE 2
#define BLT 3
#define BGT 4
#define BLTU 5
#define BGTU 6
#define NO_ALU 15
#define ADD 0
#define SUB 1
#define SLLA 2
#define SLT 3
#define SLTU 4
#define XOR 5
#define SRL 6
#define SRA 7
#define OR 8
#define AND 9
#define SUBU 10
#define LUI_ALU 11
#define AUIPC_ALU 12
#define CSR_ALU_RW 13
#define CSR_ALU_RS 14
#define CSR_ALU_RC 15
// WRITEBACK
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
// JAL
#define JUMP 1
#define NO_JUMP 0
// STALLS
#define STALL 1
#define NO_STALL 0
#define TAKEN 1
#define NOT_TAKEN 0
#define ZERO_REG 0
// COLORS
#define GREEN "\033[32m"
#define RED "\033[31m"
#define DEFAULT "\033[39m"

1
runtime/.gitignore vendored Normal file
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@ -0,0 +1 @@
/config.h

6
runtime/Makefile Normal file
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@ -0,0 +1,6 @@
.PHONY: build_config
build_config:
../rtl/gen_config.py --outv none --outc ./config.h

2
runtime/config.h
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@ -1,2 +0,0 @@
#define TOTAL_THREADS 4
#define TOTAL_WARPS 4