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minor update
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parent
74368ab65a
commit
896aa6b2a1
5 changed files with 8 additions and 7 deletions
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@ -57,10 +57,10 @@ module VX_fcvt_unit import VX_fpu_pkg::*; #(
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// Input processing
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fclass_t fclass;
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VX_fpu_class #(
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VX_fp_classifier #(
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.EXP_BITS (EXP_BITS),
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.MAN_BITS (MAN_BITS)
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) fp_class (
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) fp_classifier (
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.exp_i (dataa[INT_WIDTH-2:MAN_BITS]),
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.man_i (dataa[MAN_BITS-1:0]),
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.clss_o (fclass)
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@ -218,7 +218,7 @@ module VX_fcvt_unit import VX_fpu_pkg::*; #(
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wire rounded_sign_s2;
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// Perform the rounding
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VX_fpu_rounding #(
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VX_fp_rounding #(
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.DAT_WIDTH (32)
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) fp_rounding (
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.abs_value_i (pre_round_abs_s2),
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@ -63,7 +63,7 @@ module VX_fncp_unit import VX_fpu_pkg::*; #(
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assign b_exponent = datab[30:23];
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assign b_mantissa = datab[22:0];
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VX_fpu_class #(
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VX_fp_classifier #(
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.EXP_BITS (EXP_BITS),
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.MAN_BITS (MAN_BITS)
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) fp_class_a (
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@ -72,7 +72,7 @@ module VX_fncp_unit import VX_fpu_pkg::*; #(
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.clss_o (a_fclass)
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);
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VX_fpu_class #(
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VX_fp_classifier #(
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.EXP_BITS (EXP_BITS),
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.MAN_BITS (MAN_BITS)
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) fp_class_b (
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@ -16,7 +16,7 @@
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`ifdef FPU_DSP
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module VX_fpu_class import VX_fpu_pkg::*; #(
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module VX_fp_classifier import VX_fpu_pkg::*; #(
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parameter MAN_BITS = 23,
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parameter EXP_BITS = 8
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) (
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@ -18,7 +18,7 @@
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/// Modified port of rouding module from fpnew Libray
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/// reference: https://github.com/pulp-platform/fpnew
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module VX_fpu_rounding #(
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module VX_fp_rounding #(
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parameter DAT_WIDTH = 2 // Width of the abolute value, without sign bit
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) (
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// inputs
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@ -134,6 +134,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
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.c (pe_data_in[i][64 +: 32]),
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.q (pe_data_out[i][0 +: 32])
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);
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assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x;
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end
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assign has_fflags = 0;
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