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mpm counters query fix

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This commit is contained in:
Blaise Tine 2024-05-01 17:21:37 -07:00
parent 4737cdabbd
commit 896aca0c62
4 changed files with 112 additions and 62 deletions
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64
runtime/opae/vortex.cpp
View file

@ -379,25 +379,6 @@ public:
return 0;
}
int dcr_write(uint32_t addr, uint32_t value) {
// write DCR value
CHECK_FPGA_ERR(api_.fpgaWriteMMIO64(fpga_, 0, MMIO_CMD_ARG0, addr), {
return -1;
});
CHECK_FPGA_ERR(api_.fpgaWriteMMIO64(fpga_, 0, MMIO_CMD_ARG1, value), {
return -1;
});
CHECK_FPGA_ERR(api_.fpgaWriteMMIO64(fpga_, 0, MMIO_CMD_TYPE, CMD_DCR_WRITE), {
return -1;
});
dcrs_.write(addr, value);
return 0;
}
int dcr_read(uint32_t addr, uint32_t* value) const {
return dcrs_.read(addr, value);
}
int start(uint64_t krnl_addr, uint64_t args_addr) {
// set kernel info
CHECK_ERR(this->dcr_write(VX_DCR_BASE_STARTUP_ADDR0, krnl_addr & 0xffffffff), {
@ -418,6 +399,9 @@ public:
return -1;
});
// clear mpm cache
mpm_cache_.clear();
return 0;
}
@ -478,6 +462,39 @@ public:
return 0;
}
int dcr_write(uint32_t addr, uint32_t value) {
// write DCR value
CHECK_FPGA_ERR(api_.fpgaWriteMMIO64(fpga_, 0, MMIO_CMD_ARG0, addr), {
return -1;
});
CHECK_FPGA_ERR(api_.fpgaWriteMMIO64(fpga_, 0, MMIO_CMD_ARG1, value), {
return -1;
});
CHECK_FPGA_ERR(api_.fpgaWriteMMIO64(fpga_, 0, MMIO_CMD_TYPE, CMD_DCR_WRITE), {
return -1;
});
dcrs_.write(addr, value);
return 0;
}
int dcr_read(uint32_t addr, uint32_t* value) const {
return dcrs_.read(addr, value);
}
int mpm_query(uint32_t addr, uint32_t core_id, uint64_t* value) {
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
if (mpm_cache_.count(core_id) == 0) {
uint64_t mpm_mem_addr = IO_MPM_ADDR + core_id * 32 * sizeof(uint64_t);
CHECK_ERR(this->download(mpm_cache_[core_id].data(), mpm_mem_addr, 32 * sizeof(uint64_t)), {
return err;
});
}
*value = mpm_cache_.at(core_id).at(offset);
return 0;
}
private:
int ensure_staging(uint64_t size) {
@ -517,6 +534,7 @@ private:
uint64_t staging_ioaddr_;
uint8_t* staging_ptr_;
uint64_t staging_size_;
std::unordered_map<uint32_t, std::array<uint64_t, 32>> mpm_cache_;
};
struct vx_buffer {
@ -821,17 +839,11 @@ extern int vx_mpm_query(vx_device_h hdevice, uint32_t addr, uint32_t core_id, ui
if (nullptr == hdevice)
return -1;
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
auto device = ((vx_device*)hdevice);
uint64_t mpm_mem_addr = IO_MPM_ADDR + (core_id * 32 + offset) * sizeof(uint64_t);
uint64_t _value;
CHECK_ERR(device->download(&_value, mpm_mem_addr, sizeof(uint64_t)), {
CHECK_ERR(device->mpm_query(addr, core_id, &_value), {
return err;
});

27
runtime/rtlsim/vortex.cpp
View file

@ -209,6 +209,10 @@ public:
future_ = std::async(std::launch::async, [&]{
processor_.run();
});
// clear mpm cache
mpm_cache_.clear();
return 0;
}
@ -240,6 +244,20 @@ public:
return dcrs_.read(addr, value);
}
int mpm_query(uint32_t addr, uint32_t core_id, uint64_t* value) {
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
if (mpm_cache_.count(core_id) == 0) {
uint64_t mpm_mem_addr = IO_MPM_ADDR + core_id * 32 * sizeof(uint64_t);
CHECK_ERR(this->download(mpm_cache_[core_id].data(), mpm_mem_addr, 32 * sizeof(uint64_t)), {
return err;
});
}
*value = mpm_cache_.at(core_id).at(offset);
return 0;
}
private:
RAM ram_;
@ -247,6 +265,7 @@ private:
MemoryAllocator global_mem_;
DeviceConfig dcrs_;
std::future<void> future_;
std::unordered_map<uint32_t, std::array<uint64_t, 32>> mpm_cache_;
};
struct vx_buffer {
@ -527,17 +546,11 @@ extern int vx_mpm_query(vx_device_h hdevice, uint32_t addr, uint32_t core_id, ui
if (nullptr == hdevice)
return -1;
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
auto device = ((vx_device*)hdevice);
uint64_t mpm_mem_addr = IO_MPM_ADDR + (core_id * 32 + offset) * sizeof(uint64_t);
uint64_t _value;
CHECK_ERR(device->download(&_value, mpm_mem_addr, sizeof(uint64_t)), {
CHECK_ERR(device->mpm_query(addr, core_id, &_value), {
return err;
});

26
runtime/simx/vortex.cpp
View file

@ -205,6 +205,9 @@ public:
processor_.run();
});
// clear mpm cache
mpm_cache_.clear();
return 0;
}
@ -236,6 +239,20 @@ public:
return dcrs_.read(addr, value);
}
int mpm_query(uint32_t addr, uint32_t core_id, uint64_t* value) {
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
if (mpm_cache_.count(core_id) == 0) {
uint64_t mpm_mem_addr = IO_MPM_ADDR + core_id * 32 * sizeof(uint64_t);
CHECK_ERR(this->download(mpm_cache_[core_id].data(), mpm_mem_addr, 32 * sizeof(uint64_t)), {
return err;
});
}
*value = mpm_cache_.at(core_id).at(offset);
return 0;
}
private:
Arch arch_;
RAM ram_;
@ -243,6 +260,7 @@ private:
MemoryAllocator global_mem_;
DeviceConfig dcrs_;
std::future<void> future_;
std::unordered_map<uint32_t, std::array<uint64_t, 32>> mpm_cache_;
};
struct vx_buffer {
@ -523,17 +541,11 @@ extern int vx_mpm_query(vx_device_h hdevice, uint32_t addr, uint32_t core_id, ui
if (nullptr == hdevice)
return -1;
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
auto device = ((vx_device*)hdevice);
uint64_t mpm_mem_addr = IO_MPM_ADDR + (core_id * 32 + offset) * sizeof(uint64_t);
uint64_t _value;
CHECK_ERR(device->download(&_value, mpm_mem_addr, sizeof(uint64_t)), {
CHECK_ERR(device->mpm_query(addr, core_id, &_value), {
return err;
});

57
runtime/xrt/vortex.cpp
View file

@ -148,6 +148,7 @@ public:
, xrtKernel_(kernel)
, platform_(platform)
, global_mem_(ALLOC_BASE_ADDR, GLOBAL_MEM_SIZE - ALLOC_BASE_ADDR, RAM_PAGE_SIZE, CACHE_BLOCK_SIZE)
, mpm_cache_(nullptr)
{}
#ifndef CPP_API
@ -486,21 +487,6 @@ public:
return 0;
}
int dcr_write(uint32_t addr, uint32_t value) {
CHECK_ERR(this->write_register(MMIO_DCR_ADDR, addr), {
return err;
});
CHECK_ERR(this->write_register(MMIO_DCR_ADDR + 4, value), {
return err;
});
dcrs_.write(addr, value);
return 0;
}
int dcr_read(uint32_t addr, uint32_t* value) const {
return dcrs_.read(addr, value);
}
int start(uint64_t krnl_addr, uint64_t args_addr) {
// set kernel info
CHECK_ERR(this->dcr_write(VX_DCR_BASE_STARTUP_ADDR0, krnl_addr & 0xffffffff), {
@ -521,6 +507,9 @@ public:
return err;
});
// clear mpm cache
mpm_cache_.clear();
return 0;
}
@ -552,6 +541,35 @@ public:
return 0;
}
int dcr_write(uint32_t addr, uint32_t value) {
CHECK_ERR(this->write_register(MMIO_DCR_ADDR, addr), {
return err;
});
CHECK_ERR(this->write_register(MMIO_DCR_ADDR + 4, value), {
return err;
});
dcrs_.write(addr, value);
return 0;
}
int dcr_read(uint32_t addr, uint32_t* value) const {
return dcrs_.read(addr, value);
}
int mpm_query(uint32_t addr, uint32_t core_id, uint64_t* value) {
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
if (mpm_cache_.count(core_id) == 0) {
uint64_t mpm_mem_addr = IO_MPM_ADDR + core_id * 32 * sizeof(uint64_t);
CHECK_ERR(this->download(mpm_cache_[core_id].data(), mpm_mem_addr, 32 * sizeof(uint64_t)), {
return err;
});
}
*value = mpm_cache_.at(core_id).at(offset);
return 0;
}
private:
xrt_device_t xrtDevice_;
@ -562,6 +580,7 @@ private:
uint64_t isa_caps_;
uint64_t global_mem_size_;
DeviceConfig dcrs_;
std::unordered_map<uint32_t, std::array<uint64_t, 32>> mpm_cache_;
#ifdef BANK_INTERLEAVE
@ -1093,17 +1112,11 @@ extern int vx_mpm_query(vx_device_h hdevice, uint32_t addr, uint32_t core_id, ui
if (nullptr == hdevice)
return -1;
uint32_t offset = addr - VX_CSR_MPM_BASE;
if (offset > 31)
return -1;
auto device = ((vx_device*)hdevice);
uint64_t mpm_mem_addr = IO_MPM_ADDR + (core_id * 32 + offset) * sizeof(uint64_t);
uint64_t _value;
CHECK_ERR(device->download(&_value, mpm_mem_addr, sizeof(uint64_t)), {
CHECK_ERR(device->mpm_query(addr, core_id, &_value), {
return err;
});