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Migrate muldiv to XLEN

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This commit is contained in:
Shashank Holla 2023-03-07 16:46:35 -05:00
parent 88d24c09e3
commit 89b947ccf9
1 changed files with 21 additions and 21 deletions
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42
hw/rtl/core/VX_muldiv.sv
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@ -12,8 +12,8 @@ module VX_muldiv (
input wire [31:0] PC_in,
input wire [`NR_BITS-1:0] rd_in,
input wire wb_in,
input wire [`NUM_THREADS-1:0][31:0] alu_in1,
input wire [`NUM_THREADS-1:0][31:0] alu_in2,
input wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in1,
input wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2,
// Outputs
output wire [`UP(`UUID_BITS)-1:0] uuid_out,
@ -22,7 +22,7 @@ module VX_muldiv (
output wire [31:0] PC_out,
output wire [`NR_BITS-1:0] rd_out,
output wire wb_out,
output wire [`NUM_THREADS-1:0][31:0] data_out,
output wire [`NUM_THREADS-1:0][`XLEN-1:0] data_out,
// handshake
input wire valid_in,
@ -35,7 +35,7 @@ module VX_muldiv (
wire is_div_op = `INST_MUL_IS_DIV(alu_op);
wire [`NUM_THREADS-1:0][31:0] mul_result;
wire [`NUM_THREADS-1:0][`XLEN-1:0] mul_result;
wire [UUID_WIDTH-1:0] mul_uuid_out;
wire [NW_WIDTH-1:0] mul_wid_out;
wire [`NUM_THREADS-1:0] mul_tmask_out;
@ -55,12 +55,12 @@ module VX_muldiv (
`ifdef IMUL_DPI
wire [`NUM_THREADS-1:0][31:0] mul_result_tmp;
wire [`NUM_THREADS-1:0][`XLEN-1:0] mul_result_tmp;
wire mul_fire_in = mul_valid_in && mul_ready_in;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire [31:0] mul_resultl, mul_resulth;
wire [`XLEN-1:0] mul_resultl, mul_resulth;
always @(*) begin
dpi_imul (mul_fire_in, alu_in1[i], alu_in2[i], is_signed_mul_a, is_signed_mul_b, mul_resultl, mul_resulth);
end
@ -68,7 +68,7 @@ module VX_muldiv (
end
VX_shift_register #(
.DATAW (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.DATAW (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * `XLEN)),
.DEPTH (`LATENCY_IMUL),
.RESETW (1)
) mul_shift_reg (
@ -84,16 +84,16 @@ module VX_muldiv (
wire is_mulh_out;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire [32:0] mul_in1 = {is_signed_mul_a && alu_in1[i][31], alu_in1[i]};
wire [32:0] mul_in2 = {is_signed_mul_b && alu_in2[i][31], alu_in2[i]};
wire [`XLEN:0] mul_in1 = {is_signed_mul_a && alu_in1[i][`XLEN-1], alu_in1[i]};
wire [`XLEN:0] mul_in2 = {is_signed_mul_b && alu_in2[i][`XLEN-1], alu_in2[i]};
`IGNORE_UNUSED_BEGIN
wire [65:0] mul_result_tmp;
wire [2*(`XLEN)+1:0] mul_result_tmp;
`IGNORE_UNUSED_END
VX_multiplier #(
.A_WIDTH (33),
.B_WIDTH (33),
.R_WIDTH (66),
.A_WIDTH (`XLEN+1),
.B_WIDTH (`XLEN+1),
.R_WIDTH (2*(`XLEN)+1),
.SIGNED (1),
.LATENCY (`LATENCY_IMUL)
) multiplier (
@ -104,7 +104,7 @@ module VX_muldiv (
.result (mul_result_tmp)
);
assign mul_result[i] = is_mulh_out ? mul_result_tmp[63:32] : mul_result_tmp[31:0];
assign mul_result[i] = is_mulh_out ? mul_result_tmp[2*(`XLEN)-1:`XLEN] : mul_result_tmp[`XLEN-1:0];
end
VX_shift_register #(
@ -123,7 +123,7 @@ module VX_muldiv (
///////////////////////////////////////////////////////////////////////////
wire [`NUM_THREADS-1:0][31:0] div_result;
wire [`NUM_THREADS-1:0][`XLEN-1:0] div_result;
wire [UUID_WIDTH-1:0] div_uuid_out;
wire [NW_WIDTH-1:0] div_wid_out;
wire [`NUM_THREADS-1:0] div_tmask_out;
@ -140,12 +140,12 @@ module VX_muldiv (
`ifdef IDIV_DPI
wire [`NUM_THREADS-1:0][31:0] div_result_tmp;
wire [`NUM_THREADS-1:0][`XLEN-1:0] div_result_tmp;
wire div_fire_in = div_valid_in && div_ready_in;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire [31:0] div_quotient, div_remainder;
wire [`XLEN-1:0] div_quotient, div_remainder;
always @(*) begin
dpi_idiv (div_fire_in, alu_in1[i], alu_in2[i], is_signed_div, div_quotient, div_remainder);
end
@ -153,7 +153,7 @@ module VX_muldiv (
end
VX_shift_register #(
.DATAW (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.DATAW (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * `XLEN)),
.DEPTH (`LATENCY_IMUL),
.RESETW (1)
) div_shift_reg (
@ -168,7 +168,7 @@ module VX_muldiv (
`else
wire [`NUM_THREADS-1:0][31:0] div_result_tmp, rem_result_tmp;
wire [`NUM_THREADS-1:0][`XLEN-1:0] div_result_tmp, rem_result_tmp;
wire is_rem_op_out;
VX_serial_div #(
@ -211,12 +211,12 @@ module VX_muldiv (
wire [31:0] rsp_PC = mul_valid_out ? mul_PC_out : div_PC_out;
wire [`NR_BITS-1:0] rsp_rd = mul_valid_out ? mul_rd_out : div_rd_out;
wire rsp_wb = mul_valid_out ? mul_wb_out : div_wb_out;
wire [`NUM_THREADS-1:0][31:0] rsp_data = mul_valid_out ? mul_result : div_result;
wire [`NUM_THREADS-1:0][`XLEN-1:0] rsp_data = mul_valid_out ? mul_result : div_result;
assign stall_out = ~ready_out && valid_out;
VX_pipe_register #(
.DATAW (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.DATAW (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * `XLEN)),
.RESETW (1)
) pipe_reg (
.clk (clk),