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texture memory bus refactoring

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This commit is contained in:
Blaise Tine 2022-02-09 04:12:26 -05:00
parent 367b2328c4
commit 8a3b9546a9
11 changed files with 191 additions and 245 deletions
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2
hw/rtl/VX_smem_arb.sv → hw/rtl/VX_cache_demux.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_smem_arb #(
module VX_cache_demux #(
parameter NUM_REQS = 1,
parameter LANES = 1,
parameter DATA_SIZE = 1,

2
hw/rtl/VX_cache_arb.sv → hw/rtl/VX_cache_mux.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_cache_arb #(
module VX_cache_mux #(
parameter NUM_REQS = 1,
parameter LANES = 1,
parameter DATA_SIZE = 1,

65
hw/rtl/VX_core.sv
View file

@ -78,6 +78,20 @@ module VX_core #(
.WORD_SIZE (`ICACHE_WORD_SIZE),
.TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
) icache_rsp_if();
`ifdef EXT_TEX_ENABLE
VX_dcache_req_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`DCACHE_TAG_WIDTH)
) tcache_req_if();
VX_dcache_rsp_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`DCACHE_TAG_WIDTH)
) tcache_rsp_if();
`endif
VX_pipeline #(
.CORE_ID(CORE_ID)
@ -87,39 +101,24 @@ module VX_core #(
.perf_memsys_if (perf_memsys_if),
`endif
.clk(clk),
.reset(reset),
.clk (clk),
.reset (reset),
// Dcache core request
.dcache_req_valid (dcache_req_if.valid),
.dcache_req_rw (dcache_req_if.rw),
.dcache_req_byteen (dcache_req_if.byteen),
.dcache_req_addr (dcache_req_if.addr),
.dcache_req_data (dcache_req_if.data),
.dcache_req_tag (dcache_req_if.tag),
.dcache_req_ready (dcache_req_if.ready),
// dcache interface
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
// Dcache core reponse
.dcache_rsp_valid (dcache_rsp_if.valid),
.dcache_rsp_tmask (dcache_rsp_if.tmask),
.dcache_rsp_data (dcache_rsp_if.data),
.dcache_rsp_tag (dcache_rsp_if.tag),
.dcache_rsp_ready (dcache_rsp_if.ready),
// icache interface
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
// Icache core request
.icache_req_valid (icache_req_if.valid),
.icache_req_addr (icache_req_if.addr),
.icache_req_tag (icache_req_if.tag),
.icache_req_ready (icache_req_if.ready),
// Icache core reponse
.icache_rsp_valid (icache_rsp_if.valid),
.icache_rsp_data (icache_rsp_if.data),
.icache_rsp_tag (icache_rsp_if.tag),
.icache_rsp_ready (icache_rsp_if.ready),
`ifdef EXT_TEX_ENABLE
.tcache_req_if (tcache_req_if),
.tcache_rsp_if (tcache_rsp_if),
`endif
// Status
.busy(busy)
.busy (busy)
);
//--
@ -135,14 +134,20 @@ module VX_core #(
.clk (clk),
.reset (reset),
// Core <-> Dcache
// dcache interface
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
// Core <-> Icache
// icache interface
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
`ifdef EXT_TEX_ENABLE
// tcache interface
.tcache_req_if (tcache_req_if),
.tcache_rsp_if (tcache_rsp_if),
`endif
// Memory
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)

6
hw/rtl/VX_define.vh
View file

@ -250,13 +250,13 @@
`define LSUQ_ADDR_BITS `LOG2UP(`LSUQ_SIZE)
`ifdef EXT_TEX_ENABLE
`define LSU_TAG_ID_BITS `MAX(`LSUQ_ADDR_BITS, 2)
`define LSU_TEX_DCACHE_TAG_BITS (`UUID_BITS + `LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS)
`define DCACHE_CORE_TAG_ID_BITS (`LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS + `TEX_TAG_BIT)
`else
`define LSU_TAG_ID_BITS `LSUQ_ADDR_BITS
`define DCACHE_CORE_TAG_ID_BITS (`LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS)
`endif
`define DCACHE_CORE_TAG_ID_BITS (`LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS)
`define DCACHE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS - `SM_ENABLE)
`define DCACHE_CORE_TAG_WIDTH (`UUID_BITS + `DCACHE_CORE_TAG_ID_BITS)
`define DCACHE_TAG_WIDTH (`UUID_BITS + `DCACHE_TAG_ID_BITS)
// Memory request data bits
`define DCACHE_MEM_DATA_WIDTH (`DCACHE_LINE_SIZE * 8)

87
hw/rtl/VX_execute.sv
View file

@ -12,6 +12,12 @@ module VX_execute #(
VX_dcache_req_if.master dcache_req_if,
VX_dcache_rsp_if.slave dcache_rsp_if,
`ifdef EXT_TEX_ENABLE
// Tcache interface
VX_dcache_req_if.master tcache_req_if,
VX_dcache_rsp_if.slave tcache_rsp_if,
`endif
// commit interface
VX_cmt_to_csr_if.slave cmt_to_csr_if,
@ -45,83 +51,13 @@ module VX_execute #(
VX_commit_if.master gpu_commit_if,
input wire busy
);
);
`ifdef EXT_TEX_ENABLE
VX_dcache_req_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS)
) lsu_dcache_req_if();
VX_dcache_rsp_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS)
) lsu_dcache_rsp_if();
VX_dcache_req_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS)
) tex_dcache_req_if();
VX_dcache_rsp_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS)
) tex_dcache_rsp_if();
VX_tex_csr_if tex_csr_if();
`ifdef PERF_ENABLE
VX_perf_tex_if perf_tex_if();
`endif
VX_cache_arb #(
.NUM_REQS (2),
.LANES (`NUM_THREADS),
.DATA_SIZE (4),
.TAG_IN_WIDTH (`LSU_TEX_DCACHE_TAG_BITS),
.TAG_SEL_IDX (`NC_TAG_BIT + `SM_ENABLE)
) tex_lsu_arb (
.clk (clk),
.reset (reset),
// Tex/LSU request
.req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}),
.req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}),
.req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}),
.req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}),
.req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}),
.req_tag_in ({tex_dcache_req_if.tag, lsu_dcache_req_if.tag}),
.req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}),
// Dcache request
.req_valid_out (dcache_req_if.valid),
.req_rw_out (dcache_req_if.rw),
.req_byteen_out (dcache_req_if.byteen),
.req_addr_out (dcache_req_if.addr),
.req_data_out (dcache_req_if.data),
.req_tag_out (dcache_req_if.tag),
.req_ready_out (dcache_req_if.ready),
// Dcache response
.rsp_valid_in (dcache_rsp_if.valid),
.rsp_tmask_in (dcache_rsp_if.tmask),
.rsp_tag_in (dcache_rsp_if.tag),
.rsp_data_in (dcache_rsp_if.data),
.rsp_ready_in (dcache_rsp_if.ready),
// Tex/LSU response
.rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}),
.rsp_tmask_out ({tex_dcache_rsp_if.tmask, lsu_dcache_rsp_if.tmask}),
.rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}),
.rsp_tag_out ({tex_dcache_rsp_if.tag, lsu_dcache_rsp_if.tag}),
.rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready})
);
`endif
`ifdef EXT_F_ENABLE
@ -151,13 +87,8 @@ module VX_execute #(
`SCOPE_BIND_VX_execute_lsu_unit
.clk (clk),
.reset (lsu_reset),
`ifdef EXT_TEX_ENABLE
.dcache_req_if (lsu_dcache_req_if),
.dcache_rsp_if (lsu_dcache_rsp_if),
`else
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
`endif
.lsu_req_if (lsu_req_if),
.ld_commit_if (ld_commit_if),
.st_commit_if (st_commit_if)
@ -220,8 +151,8 @@ module VX_execute #(
.perf_tex_if (perf_tex_if),
`endif
.tex_csr_if (tex_csr_if),
.tcache_req_if (tex_dcache_req_if),
.tcache_rsp_if (tex_dcache_rsp_if),
.tcache_req_if (tcache_req_if),
.tcache_rsp_if (tcache_rsp_if),
`endif
.warp_ctl_if (warp_ctl_if),
.gpu_commit_if (gpu_commit_if)

4
hw/rtl/VX_gpu_unit.sv
View file

@ -14,11 +14,11 @@ module VX_gpu_unit #(
`ifdef EXT_TEX_ENABLE
// PERF
`ifdef PERF_ENABLE
VX_perf_tex_if.master perf_tex_if,
VX_perf_tex_if.master perf_tex_if,
`endif
VX_dcache_req_if.master tcache_req_if,
VX_dcache_rsp_if.slave tcache_rsp_if,
VX_tex_csr_if.slave tex_csr_if,
VX_tex_csr_if.slave tex_csr_if,
`endif
// Outputs

13
hw/rtl/VX_icache_stage.sv
View file

@ -24,28 +24,29 @@ module VX_icache_stage #(
localparam OUT_REG = 0;
wire [`NW_BITS-1:0] req_tag, rsp_tag;
wire [`UUID_BITS-1:0] rsp_uuid;
wire [`NW_BITS-1:0] req_tag, rsp_tag;
wire icache_req_fire = icache_req_if.valid && icache_req_if.ready;
assign req_tag = ifetch_req_if.wid;
assign rsp_tag = icache_rsp_if.tag[`NW_BITS-1:0];
assign {rsp_uuid, rsp_tag} = icache_rsp_if.tag;
wire [`UUID_BITS-1:0] rsp_uuid;
wire [31:0] rsp_PC;
wire [`NUM_THREADS-1:0] rsp_tmask;
VX_dp_ram #(
.DATAW (32 + `NUM_THREADS + `UUID_BITS),
.DATAW (32 + `NUM_THREADS),
.SIZE (`NUM_WARPS),
.LUTRAM (1)
) req_metadata (
.clk (clk),
.wren (icache_req_fire),
.waddr (req_tag),
.wdata ({ifetch_req_if.PC, ifetch_req_if.tmask, ifetch_req_if.uuid}),
.wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}),
.raddr (rsp_tag),
.rdata ({rsp_PC, rsp_tmask, rsp_uuid})
.rdata ({rsp_PC, rsp_tmask})
);
`RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR),

9
hw/rtl/VX_lsu_unit.sv
View file

@ -136,13 +136,14 @@ module VX_lsu_unit #(
wire mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n);
assign mbuf_raddr = dcache_rsp_if.tag[`CACHE_ADDR_TYPE_BITS +: `LSUQ_ADDR_BITS];
`UNUSED_VAR (dcache_rsp_if.tag)
assign rsp_uuid = dcache_rsp_if.tag[`DCACHE_CORE_TAG_ID_BITS +: `UUID_BITS];
`UNUSED_VAR (dcache_rsp_if.tag)
// do not writeback from software prefetch
wire req_wb2 = req_wb && ~req_is_prefetch;
VX_index_buffer #(
.DATAW (`UUID_BITS + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1 + 1),
.DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1 + 1),
.SIZE (`LSUQ_SIZE)
) req_metadata (
.clk (clk),
@ -150,8 +151,8 @@ module VX_lsu_unit #(
.write_addr (mbuf_waddr),
.acquire_slot (mbuf_push),
.read_addr (mbuf_raddr),
.write_data ({req_uuid, req_wid, req_pc, req_tmask, req_rd, req_wb2, req_type, req_offset, req_is_dup, req_is_prefetch}),
.read_data ({rsp_uuid, rsp_wid, rsp_pc, rsp_tmask, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup, rsp_is_prefetch}),
.write_data ({req_wid, req_pc, req_tmask, req_rd, req_wb2, req_type, req_offset, req_is_dup, req_is_prefetch}),
.read_data ({rsp_wid, rsp_pc, rsp_tmask, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup, rsp_is_prefetch}),
.release_addr (mbuf_raddr),
.release_slot (mbuf_pop),
.full (mbuf_full),

133
hw/rtl/VX_mem_unit.sv
View file

@ -12,14 +12,20 @@ module VX_mem_unit # (
VX_perf_memsys_if.master perf_memsys_if,
`endif
// Core <-> Dcache
// dcache interface
VX_dcache_req_if.slave dcache_req_if,
VX_dcache_rsp_if.master dcache_rsp_if,
// Core <-> Icache
// icache interface
VX_icache_req_if.slave icache_req_if,
VX_icache_rsp_if.master icache_rsp_if,
`ifdef EXT_TEX_ENABLE
// tcache interface
VX_dcache_req_if.slave tcache_req_if,
VX_dcache_rsp_if.master tcache_rsp_if,
`endif
// Memory
VX_mem_req_if.master mem_req_if,
VX_mem_rsp_if.slave mem_rsp_if
@ -54,15 +60,27 @@ module VX_mem_unit # (
VX_dcache_req_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
.WORD_SIZE (`DCACHE_WORD_SIZE),
.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE)
.TAG_WIDTH (`DCACHE_TAG_WIDTH)
) dcache_req_tmp_if();
VX_dcache_rsp_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
.WORD_SIZE (`DCACHE_WORD_SIZE),
.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE)
.TAG_WIDTH (`DCACHE_TAG_WIDTH)
) dcache_rsp_tmp_if();
VX_dcache_req_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
.WORD_SIZE (`DCACHE_WORD_SIZE),
.TAG_WIDTH (`DCACHE_TAG_WIDTH+`EXT_TEX_ENABLED)
) dcache_req_tmp2_if();
VX_dcache_rsp_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
.WORD_SIZE (`DCACHE_WORD_SIZE),
.TAG_WIDTH (`DCACHE_TAG_WIDTH+`EXT_TEX_ENABLED)
) dcache_rsp_tmp2_if();
`RESET_RELAY (icache_reset);
`RESET_RELAY (dcache_reset);
`RESET_RELAY (mem_arb_reset);
@ -139,8 +157,8 @@ module VX_mem_unit # (
.MRSQ_SIZE (`DCACHE_MRSQ_SIZE),
.MREQ_SIZE (`DCACHE_MREQ_SIZE),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE),
.CORE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS-`SM_ENABLE),
.CORE_TAG_WIDTH (`DCACHE_TAG_WIDTH+`EXT_TEX_ENABLED),
.CORE_TAG_ID_BITS (`DCACHE_TAG_ID_BITS+`EXT_TEX_ENABLED),
.MEM_TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH),
.NC_ENABLE (1)
) dcache (
@ -150,20 +168,20 @@ module VX_mem_unit # (
.reset (dcache_reset),
// Core req
.core_req_valid (dcache_req_tmp_if.valid),
.core_req_rw (dcache_req_tmp_if.rw),
.core_req_byteen (dcache_req_tmp_if.byteen),
.core_req_addr (dcache_req_tmp_if.addr),
.core_req_data (dcache_req_tmp_if.data),
.core_req_tag (dcache_req_tmp_if.tag),
.core_req_ready (dcache_req_tmp_if.ready),
.core_req_valid (dcache_req_tmp2_if.valid),
.core_req_rw (dcache_req_tmp2_if.rw),
.core_req_byteen (dcache_req_tmp2_if.byteen),
.core_req_addr (dcache_req_tmp2_if.addr),
.core_req_data (dcache_req_tmp2_if.data),
.core_req_tag (dcache_req_tmp2_if.tag),
.core_req_ready (dcache_req_tmp2_if.ready),
// Core response
.core_rsp_valid (dcache_rsp_tmp_if.valid),
.core_rsp_tmask (dcache_rsp_tmp_if.tmask),
.core_rsp_data (dcache_rsp_tmp_if.data),
.core_rsp_tag (dcache_rsp_tmp_if.tag),
.core_rsp_ready (dcache_rsp_tmp_if.ready),
.core_rsp_valid (dcache_rsp_tmp2_if.valid),
.core_rsp_tmask (dcache_rsp_tmp2_if.tmask),
.core_rsp_data (dcache_rsp_tmp2_if.data),
.core_rsp_tag (dcache_rsp_tmp2_if.tag),
.core_rsp_ready (dcache_rsp_tmp2_if.ready),
`ifdef PERF_ENABLE
.perf_cache_if (perf_dcache_if),
@ -185,28 +203,28 @@ module VX_mem_unit # (
.mem_rsp_ready (dcache_mem_rsp_if.ready)
);
if (`SM_ENABLE) begin
if (`SM_ENABLE) begin
VX_dcache_req_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
.WORD_SIZE (`DCACHE_WORD_SIZE),
.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE)
.TAG_WIDTH (`DCACHE_TAG_WIDTH)
) smem_req_if();
VX_dcache_rsp_if #(
.NUM_REQS (`DCACHE_NUM_REQS),
.WORD_SIZE (`DCACHE_WORD_SIZE),
.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE)
.TAG_WIDTH (`DCACHE_TAG_WIDTH)
) smem_rsp_if();
`RESET_RELAY (smem_arb_reset);
`RESET_RELAY (smem_reset);
VX_smem_arb #(
VX_cache_demux #(
.NUM_REQS (2),
.LANES (`NUM_THREADS),
.DATA_SIZE (4),
.TAG_IN_WIDTH (`DCACHE_CORE_TAG_WIDTH),
.TAG_SEL_IDX (0), // SM flag
.TAG_SEL_IDX (0),
.TYPE ("P"),
.BUFFERED_REQ (2),
.BUFFERED_RSP (1)
@ -255,8 +273,8 @@ module VX_mem_unit # (
.NUM_REQS (`SMEM_NUM_REQS),
.CREQ_SIZE (`SMEM_CREQ_SIZE),
.CRSQ_SIZE (`SMEM_CRSQ_SIZE),
.CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE),
.CORE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS-`SM_ENABLE),
.CORE_TAG_WIDTH (`DCACHE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCACHE_TAG_ID_BITS),
.BANK_ADDR_OFFSET (`SMEM_BANK_ADDR_OFFSET)
) smem (
.clk (clk),
@ -305,7 +323,70 @@ module VX_mem_unit # (
assign dcache_rsp_if.tag = dcache_rsp_tmp_if.tag;
assign dcache_rsp_if.data = dcache_rsp_tmp_if.data;
assign dcache_rsp_tmp_if.ready = dcache_rsp_if.ready;
end
end
`ifdef EXT_TEX_ENABLE
VX_cache_mux #(
.NUM_REQS (2),
.LANES (`NUM_THREADS),
.DATA_SIZE (4),
.TAG_IN_WIDTH (`DCACHE_TAG_WIDTH),
.TAG_SEL_IDX (0)
) dcache_arb (
.clk (clk),
.reset (reset),
// Tex/LSU request
.req_valid_in ({tcache_req_if.valid, dcache_req_tmp_if.valid}),
.req_rw_in ({tcache_req_if.rw, dcache_req_tmp_if.rw}),
.req_byteen_in ({tcache_req_if.byteen, dcache_req_tmp_if.byteen}),
.req_addr_in ({tcache_req_if.addr, dcache_req_tmp_if.addr}),
.req_data_in ({tcache_req_if.data, dcache_req_tmp_if.data}),
.req_tag_in ({tcache_req_if.tag, dcache_req_tmp_if.tag}),
.req_ready_in ({tcache_req_if.ready, dcache_req_tmp_if.ready}),
// Dcache request
.req_valid_out (dcache_req_tmp2_if.valid),
.req_rw_out (dcache_req_tmp2_if.rw),
.req_byteen_out (dcache_req_tmp2_if.byteen),
.req_addr_out (dcache_req_tmp2_if.addr),
.req_data_out (dcache_req_tmp2_if.data),
.req_tag_out (dcache_req_tmp2_if.tag),
.req_ready_out (dcache_req_tmp2_if.ready),
// Dcache response
.rsp_valid_in (dcache_rsp_tmp2_if.valid),
.rsp_tmask_in (dcache_rsp_tmp2_if.tmask),
.rsp_tag_in (dcache_rsp_tmp2_if.tag),
.rsp_data_in (dcache_rsp_tmp2_if.data),
.rsp_ready_in (dcache_rsp_tmp2_if.ready),
// Tex/LSU response
.rsp_valid_out ({tcache_rsp_if.valid, dcache_rsp_tmp_if.valid}),
.rsp_tmask_out ({tcache_rsp_if.tmask, dcache_rsp_tmp_if.tmask}),
.rsp_data_out ({tcache_rsp_if.data, dcache_rsp_tmp_if.data}),
.rsp_tag_out ({tcache_rsp_if.tag, dcache_rsp_tmp_if.tag}),
.rsp_ready_out ({tcache_rsp_if.ready, dcache_rsp_tmp_if.ready})
);
`else
assign dcache_req_tmp2_if.valid = dcache_req_tmp_if.valid;
assign dcache_req_tmp2_if.rw = dcache_req_tmp_if.rw;
assign dcache_req_tmp2_if.byteen = dcache_req_tmp_if.byteen;
assign dcache_req_tmp2_if.addr = dcache_req_tmp_if.addr;
assign dcache_req_tmp2_if.data = dcache_req_tmp_if.data;
assign dcache_req_tmp2_if.tag = dcache_req_tmp_if.tag;
assign dcache_req_tmp_if.ready = dcache_req_tmp2_if.ready;
assign dcache_rsp_tmp_if.valid = dcache_rsp_tmp2_if.valid;
assign dcache_rsp_tmp_if.tmask = dcache_rsp_tmp2_if.tmask;
assign dcache_rsp_tmp_if.tag = dcache_rsp_tmp2_if.tag;
assign dcache_rsp_tmp_if.data = dcache_rsp_tmp2_if.data;
assign dcache_rsp_tmp2_if.ready = dcache_rsp_tmp_if.ready;
`endif
wire [`DCACHE_MEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DCACHE_MEM_TAG_WIDTH'(icache_mem_req_if.tag);
wire [`DCACHE_MEM_TAG_WIDTH-1:0] icache_mem_rsp_tag;

113
hw/rtl/VX_pipeline.sv
View file

@ -6,108 +6,30 @@ module VX_pipeline #(
`SCOPE_IO_VX_pipeline
// Clock
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Dcache core request
output wire [`NUM_THREADS-1:0] dcache_req_valid,
output wire [`NUM_THREADS-1:0] dcache_req_rw,
output wire [`NUM_THREADS-1:0][3:0] dcache_req_byteen,
output wire [`NUM_THREADS-1:0][29:0] dcache_req_addr,
output wire [`NUM_THREADS-1:0][31:0] dcache_req_data,
output wire [`NUM_THREADS-1:0][`DCACHE_CORE_TAG_WIDTH-1:0] dcache_req_tag,
input wire [`NUM_THREADS-1:0] dcache_req_ready,
// Dcache interface
VX_dcache_req_if.master dcache_req_if,
VX_dcache_rsp_if.slave dcache_rsp_if,
// Dcache core reponse
input wire dcache_rsp_valid,
input wire [`NUM_THREADS-1:0] dcache_rsp_tmask,
input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag,
output wire dcache_rsp_ready,
// Icache interface
VX_icache_req_if.master icache_req_if,
VX_icache_rsp_if.slave icache_rsp_if,
// Icache core request
output wire icache_req_valid,
output wire [29:0] icache_req_addr,
output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag,
input wire icache_req_ready,
// Icache core response
input wire icache_rsp_valid,
input wire [31:0] icache_rsp_data,
input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag,
output wire icache_rsp_ready,
`ifdef EXT_TEX_ENABLE
// Tcache interface
VX_dcache_req_if.master tcache_req_if,
VX_dcache_rsp_if.slave tcache_rsp_if,
`endif
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_perf_memsys_if.slave perf_memsys_if,
`endif
// Status
output wire busy
output wire busy
);
//
// Dcache request
//
VX_dcache_req_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH)
) dcache_req_if();
assign dcache_req_valid = dcache_req_if.valid;
assign dcache_req_rw = dcache_req_if.rw;
assign dcache_req_byteen = dcache_req_if.byteen;
assign dcache_req_addr = dcache_req_if.addr;
assign dcache_req_data = dcache_req_if.data;
assign dcache_req_tag = dcache_req_if.tag;
assign dcache_req_if.ready = dcache_req_ready;
//
// Dcache response
//
VX_dcache_rsp_if #(
.NUM_REQS (`NUM_THREADS),
.WORD_SIZE (4),
.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH)
) dcache_rsp_if();
assign dcache_rsp_if.valid = dcache_rsp_valid;
assign dcache_rsp_if.tmask = dcache_rsp_tmask;
assign dcache_rsp_if.data = dcache_rsp_data;
assign dcache_rsp_if.tag = dcache_rsp_tag;
assign dcache_rsp_ready = dcache_rsp_if.ready;
//
// Icache request
//
VX_icache_req_if #(
.WORD_SIZE (4),
.TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
) icache_req_if();
assign icache_req_valid = icache_req_if.valid;
assign icache_req_addr = icache_req_if.addr;
assign icache_req_tag = icache_req_if.tag;
assign icache_req_if.ready = icache_req_ready;
//
// Icache response
//
VX_icache_rsp_if #(
.WORD_SIZE (4),
.TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
) icache_rsp_if();
assign icache_rsp_if.valid = icache_rsp_valid;
assign icache_rsp_if.data = icache_rsp_data;
assign icache_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_ready = icache_rsp_if.ready;
///////////////////////////////////////////////////////////////////////////
VX_fetch_to_csr_if fetch_to_csr_if();
VX_cmt_to_csr_if cmt_to_csr_if();
VX_decode_if decode_if();
@ -214,6 +136,11 @@ module VX_pipeline #(
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
`ifdef EXT_TEX_ENABLE
.tcache_req_if (tcache_req_if),
.tcache_rsp_if (tcache_rsp_if),
`endif
.cmt_to_csr_if (cmt_to_csr_if),
.fetch_to_csr_if(fetch_to_csr_if),

2
hw/rtl/tex_unit/VX_tex_mem.sv
View file

@ -164,7 +164,7 @@ module VX_tex_mem #(
assign cache_req_if.addr = req_texel_addr;
assign cache_req_if.byteen = {NUM_REQS{4'b0}};
assign cache_req_if.data = 'x;
assign cache_req_if.tag = {NUM_REQS{q_req_uuid, `LSU_TAG_ID_BITS'(req_texel_idx), `CACHE_ADDR_TYPE_BITS'(0)}};
assign cache_req_if.tag = {NUM_REQS{q_req_uuid, `LSU_TAG_ID_BITS'(req_texel_idx), 1'b0}};
// Dcache Response