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fixed Modelsim build errors
This commit is contained in:
Blaise Tine
parent
07c52d8729
commit
8aa2d74714
4 changed files with 27 additions and 39 deletions
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@ -242,6 +242,9 @@ module VX_bank
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wire[31:0] miss_add_pc;
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wire[31:0] addr_st2;
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wire is_fill_st2;
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VX_cache_miss_resrv #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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@ -298,6 +301,11 @@ module VX_bank
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wire stall_bank_pipe;
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reg is_fill_in_pipe;
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wire valid_st1 [STAGE_1_CYCLES-1:0];
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wire is_fill_st1 [STAGE_1_CYCLES-1:0];
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wire going_to_write_st1[STAGE_1_CYCLES-1:0];
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wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
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reg[16:0] p_stage;
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always @(*) begin
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is_fill_in_pipe = 0;
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@ -316,7 +324,6 @@ module VX_bank
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assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
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assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
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integer st1_cycle;
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always @(*) begin
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@ -334,9 +341,6 @@ module VX_bank
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end
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end
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wire qual_is_fill_st0;
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wire qual_valid_st0;
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wire [31:0] qual_addr_st0;
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@ -347,12 +351,8 @@ module VX_bank
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wire qual_is_snp;
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wire [31:0] qual_pc_st0;
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wire valid_st1 [STAGE_1_CYCLES-1:0];
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wire going_to_write_st1[STAGE_1_CYCLES-1:0];
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wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
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wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
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wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
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wire is_fill_st1 [STAGE_1_CYCLES-1:0];
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wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
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wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
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wire is_snp_st1 [STAGE_1_CYCLES-1:0];
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wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
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@ -493,16 +493,14 @@ module VX_bank
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wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
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wire valid_st2;
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wire[31:0] addr_st2;
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wire valid_st2;
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wire[`WORD_SIZE_RNG] writeword_st2;
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wire[`WORD_SIZE_RNG] readword_st2;
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wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2;
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wire miss_st2;
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wire dirty_st2;
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wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
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wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
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wire is_fill_st2;
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wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
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wire fill_saw_dirty_st2;
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wire is_snp_st2;
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wire [31:0] pc_st2;
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@ -517,6 +515,10 @@ module VX_bank
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.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
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);
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wire cwbq_full;
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wire dwbq_full;
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wire ffsq_full;
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wire invalidate_fill;
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// Enqueue to miss reserv if it's a valid miss
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assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
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@ -534,8 +536,7 @@ module VX_bank
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wire [1:0] cwbq_wb = miss_add_wb;
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wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
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wire [31:0] cwbq_pc = pc_st2;
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wire cwbq_full;
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wire cwbq_empty;
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assign bank_wb_valid = !cwbq_empty;
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VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
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@ -556,11 +557,8 @@ module VX_bank
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wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
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wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2;
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wire dwbq_empty;
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wire dwbq_full;
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wire invalidate_fill;
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wire possible_fill = valid_st2 && miss_st2;
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wire possible_fill = valid_st2 && miss_st2;
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wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
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VX_fill_invalidator #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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@ -611,8 +609,7 @@ module VX_bank
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.full (dwbq_full)
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);
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wire snp_fwd_push;
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wire ffsq_full;
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wire snp_fwd_push;
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wire ffsq_empty;
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assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
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@ -628,13 +625,6 @@ module VX_bank
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.full (ffsq_full)
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);
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assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
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endmodule : VX_bank
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endmodule : VX_bank
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@ -1,3 +1,4 @@
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`include "VX_cache_config.v"
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module VX_snp_fwd_arb
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#(
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@ -93,6 +93,7 @@ module VX_tag_data_access
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wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable;
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wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data;
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wire sw, sb, sh;
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wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)));
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@ -230,9 +231,9 @@ module VX_tag_data_access
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/////////////////////// STORE LOGIC ///////////////////
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wire sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE);
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wire sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE);
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wire sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE);
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assign sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE);
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assign sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE);
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assign sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE);
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wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
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wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
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@ -279,8 +280,4 @@ module VX_tag_data_access
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assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e;
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assign invalidate_line = is_snp_st1e && !miss_st1e;
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endmodule
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endmodule
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@ -127,7 +127,7 @@
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`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
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`define SINGLE_CORE_BENCH
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//`define SINGLE_CORE_BENCH
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`define GLOBAL_BLOCK_SIZE_BYTES 16
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