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missing rtl changes from OPAE

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This commit is contained in:
Blaise Tine 2020-03-27 22:37:35 -04:00
parent e43f5c8767
commit 8bb1f66220
8 changed files with 160 additions and 149 deletions
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44
rtl/Makefile
View file

@ -1,32 +1,35 @@
all: RUNFILE
INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
INCLUDE = -I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
SINGLE_CORE=Vortex.v
MULTI_CORE=Vortex_SOC.v
SINGLE_CORE = Vortex.v
EXE=--exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp
MULTI_EXE=--exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
MULTI_CORE = Vortex_SOC.v
COMP=--compiler gcc --language 1800-2009
EXE += --exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
MULTI_EXE += --exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
VF += -compiler gcc --language 1800-2009
WNO += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
# WNO=
# LIGHTW=
LIGHTW=-Wno-UNOPTFLAT
LIGHTW += -Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=
LIB +=
CF = -std=c++11 -fms-extensions
CF += -std=c++11 -fms-extensions
DEB=--trace -DVL_DEBUG=1
DEB += --trace -DVL_DEBUG=1
MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKECPP += (cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk)
MAKECPPRel += (cd obj_dir && make -j -f VVortex.mk)
MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKEMULTICPP += (cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
@ -36,23 +39,22 @@ build_config:
# -LDFLAGS '-lsystemc'
VERILATOR: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW)
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(LIGHTW)
VERILATORnoWarnings: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB)
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB)
VERILATORnoWarningsRel: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) --threads $(THREADS)
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS)
VERILATORMULTInoWarnings: build_config
verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB)
verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS)
compdebug: build_config
verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
compdebugmulti: build_config
verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
RUNFILE: VERILATOR
$(MAKECPP)

22
rtl/Vortex.v
View file

@ -30,11 +30,31 @@ module Vortex
input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// LLC Snooping
// DRAM Icache Req
output wire I_dram_req,
output wire I_dram_req_write,
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG],
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res
output wire I_dram_fill_accept,
input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG],
// Dcache Snooping
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
// Icache Snooping
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak
`else

8
rtl/Vortex_SOC.v
View file

@ -369,11 +369,11 @@ module Vortex_SOC (
assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
end
// endgenerate

5
rtl/shared_memory/VX_shared_memory_block.v
View file

@ -29,6 +29,8 @@ module VX_shared_memory_block
`ifndef SYN
reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0];
wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
//wire need_to_write = (|we);
integer curr_ind;
@ -48,8 +50,7 @@ module VX_shared_memory_block
if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3];
end
end
wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
assign reg_addr = addr;
// always @(posedge clk)
// reg_addr <= addr;

109
rtl/simulate/Vortex.h
View file

@ -1,7 +1,7 @@
// C++ libraries
#include <utility>
#include <utility>
#include <iostream>
#include <map>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
@ -20,62 +20,61 @@
#include <verilated_vcd_c.h>
#endif
typedef struct
{
int cycles_left;
int data_length;
unsigned base_addr;
unsigned * data;
typedef struct {
int cycles_left;
int data_length;
unsigned base_addr;
unsigned *data;
} dram_req_t;
class Vortex
{
public:
Vortex(RAM* ram);
~Vortex();
bool simulate();
void step();
void reset();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool is_busy();
private:
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
class Vortex {
public:
Vortex(RAM *ram);
~Vortex();
bool is_busy();
void reset();
void step();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool simulate();
RAM* ram;
private:
void print_stats(bool cycle_test = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
VVortex * vortex;
RAM *ram;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
std::vector<dram_req_t> I_dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
VVortex *vortex;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
std::vector<dram_req_t> I_dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};

108
rtl/simulate/Vortex_SOC.h
View file

@ -1,7 +1,7 @@
// C++ libraries
#include <utility>
#include <utility>
#include <iostream>
#include <map>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
@ -19,61 +19,59 @@
#include <verilated_vcd_c.h>
#endif
typedef struct
{
int cycles_left;
int data_length;
unsigned base_addr;
unsigned * data;
typedef struct {
int cycles_left;
int data_length;
unsigned base_addr;
unsigned *data;
} dram_req_t;
class Vortex_SOC
{
public:
Vortex_SOC(RAM* ram);
~Vortex_SOC();
bool simulate();
void step();
void reset();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool is_busy();
private:
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
class Vortex_SOC {
public:
Vortex_SOC(RAM *ram);
~Vortex_SOC();
bool is_busy();
void reset();
void step();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool simulate();
private:
void print_stats(bool cycle_test = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
RAM* ram;
RAM *ram;
VVortex_SOC * vortex;
VVortex_SOC *vortex;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};

8
rtl/simulate/multi_test_bench.cpp
View file

@ -3,16 +3,10 @@
#define NUM_TESTS 46
int main(int argc, char **argv)
{
// Verilated::debug(1);
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// #define ALL_TESTS
#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
std::string tests[NUM_TESTS] = {

5
rtl/simulate/test_bench.cpp
View file

@ -9,10 +9,7 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// #define ALL_TESTS
#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;