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Added rf2_32x19_wm0 again

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Lingjun Zhu 2019-11-11 14:28:45 -05:00
parent 4b2ea58b79
commit 8cddba46ee
22 changed files with 75872 additions and 0 deletions
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models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.bitmap Normal file
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#address bit[0] bit[0]_ bit[1] bit[1]_ bit[2] bit[2]_ bit[3] bit[3]_ bit[4] bit[4]_ bit[5] bit[5]_ bit[6] bit[6]_ bit[7] bit[7]_ bit[8] bit[8]_ bit[9] bit[9]_ bit[10] bit[10]_ bit[11] bit[11]_ bit[12] bit[12]_ bit[13] bit[13]_ bit[14] bit[14]_ bit[15] bit[15]_ bit[16] bit[16]_ bit[17] bit[17]_ bit[18] bit[18]_
00000 15.175,2.960 15.275,3.030 15.175,5.840 15.275,5.910 15.175,8.720 15.275,8.790 15.175,11.600 15.275,11.670 15.175,14.480 15.275,14.550 15.175,17.360 15.275,17.430 15.175,20.240 15.275,20.310 15.175,23.120 15.275,23.190 15.175,26.000 15.275,26.070 15.175,72.060 15.275,71.990 15.175,74.940 15.275,74.870 15.175,77.820 15.275,77.750 15.175,80.700 15.275,80.630 15.175,83.580 15.275,83.510 15.175,86.460 15.275,86.390 15.175,89.340 15.275,89.270 15.175,92.220 15.275,92.150 15.175,95.100 15.275,95.030 15.175,97.980 15.275,97.910
00001 15.175,1.590 15.275,1.520 15.175,4.470 15.275,4.400 15.175,7.350 15.275,7.280 15.175,10.230 15.275,10.160 15.175,13.110 15.275,13.040 15.175,15.990 15.275,15.920 15.175,18.870 15.275,18.800 15.175,21.750 15.275,21.680 15.175,24.630 15.275,24.560 15.175,73.430 15.275,73.500 15.175,76.310 15.275,76.380 15.175,79.190 15.275,79.260 15.175,82.070 15.275,82.140 15.175,84.950 15.275,85.020 15.175,87.830 15.275,87.900 15.175,90.710 15.275,90.780 15.175,93.590 15.275,93.660 15.175,96.470 15.275,96.540 15.175,99.350 15.275,99.420
00002 15.545,2.960 15.445,3.030 15.545,5.840 15.445,5.910 15.545,8.720 15.445,8.790 15.545,11.600 15.445,11.670 15.545,14.480 15.445,14.550 15.545,17.360 15.445,17.430 15.545,20.240 15.445,20.310 15.545,23.120 15.445,23.190 15.545,26.000 15.445,26.070 15.545,72.060 15.445,71.990 15.545,74.940 15.445,74.870 15.545,77.820 15.445,77.750 15.545,80.700 15.445,80.630 15.545,83.580 15.445,83.510 15.545,86.460 15.445,86.390 15.545,89.340 15.445,89.270 15.545,92.220 15.445,92.150 15.545,95.100 15.445,95.030 15.545,97.980 15.445,97.910
00003 15.545,1.590 15.445,1.520 15.545,4.470 15.445,4.400 15.545,7.350 15.445,7.280 15.545,10.230 15.445,10.160 15.545,13.110 15.445,13.040 15.545,15.990 15.445,15.920 15.545,18.870 15.445,18.800 15.545,21.750 15.445,21.680 15.545,24.630 15.445,24.560 15.545,73.430 15.445,73.500 15.545,76.310 15.445,76.380 15.545,79.190 15.445,79.260 15.545,82.070 15.445,82.140 15.545,84.950 15.445,85.020 15.545,87.830 15.445,87.900 15.545,90.710 15.445,90.780 15.545,93.590 15.445,93.660 15.545,96.470 15.445,96.540 15.545,99.350 15.445,99.420
00004 15.715,2.960 15.815,3.030 15.715,5.840 15.815,5.910 15.715,8.720 15.815,8.790 15.715,11.600 15.815,11.670 15.715,14.480 15.815,14.550 15.715,17.360 15.815,17.430 15.715,20.240 15.815,20.310 15.715,23.120 15.815,23.190 15.715,26.000 15.815,26.070 15.715,72.060 15.815,71.990 15.715,74.940 15.815,74.870 15.715,77.820 15.815,77.750 15.715,80.700 15.815,80.630 15.715,83.580 15.815,83.510 15.715,86.460 15.815,86.390 15.715,89.340 15.815,89.270 15.715,92.220 15.815,92.150 15.715,95.100 15.815,95.030 15.715,97.980 15.815,97.910
00005 15.715,1.590 15.815,1.520 15.715,4.470 15.815,4.400 15.715,7.350 15.815,7.280 15.715,10.230 15.815,10.160 15.715,13.110 15.815,13.040 15.715,15.990 15.815,15.920 15.715,18.870 15.815,18.800 15.715,21.750 15.815,21.680 15.715,24.630 15.815,24.560 15.715,73.430 15.815,73.500 15.715,76.310 15.815,76.380 15.715,79.190 15.815,79.260 15.715,82.070 15.815,82.140 15.715,84.950 15.815,85.020 15.715,87.830 15.815,87.900 15.715,90.710 15.815,90.780 15.715,93.590 15.815,93.660 15.715,96.470 15.815,96.540 15.715,99.350 15.815,99.420
00006 16.085,2.960 15.985,3.030 16.085,5.840 15.985,5.910 16.085,8.720 15.985,8.790 16.085,11.600 15.985,11.670 16.085,14.480 15.985,14.550 16.085,17.360 15.985,17.430 16.085,20.240 15.985,20.310 16.085,23.120 15.985,23.190 16.085,26.000 15.985,26.070 16.085,72.060 15.985,71.990 16.085,74.940 15.985,74.870 16.085,77.820 15.985,77.750 16.085,80.700 15.985,80.630 16.085,83.580 15.985,83.510 16.085,86.460 15.985,86.390 16.085,89.340 15.985,89.270 16.085,92.220 15.985,92.150 16.085,95.100 15.985,95.030 16.085,97.980 15.985,97.910
00007 16.085,1.590 15.985,1.520 16.085,4.470 15.985,4.400 16.085,7.350 15.985,7.280 16.085,10.230 15.985,10.160 16.085,13.110 15.985,13.040 16.085,15.990 15.985,15.920 16.085,18.870 15.985,18.800 16.085,21.750 15.985,21.680 16.085,24.630 15.985,24.560 16.085,73.430 15.985,73.500 16.085,76.310 15.985,76.380 16.085,79.190 15.985,79.260 16.085,82.070 15.985,82.140 16.085,84.950 15.985,85.020 16.085,87.830 15.985,87.900 16.085,90.710 15.985,90.780 16.085,93.590 15.985,93.660 16.085,96.470 15.985,96.540 16.085,99.350 15.985,99.420
00008 16.255,2.960 16.355,3.030 16.255,5.840 16.355,5.910 16.255,8.720 16.355,8.790 16.255,11.600 16.355,11.670 16.255,14.480 16.355,14.550 16.255,17.360 16.355,17.430 16.255,20.240 16.355,20.310 16.255,23.120 16.355,23.190 16.255,26.000 16.355,26.070 16.255,72.060 16.355,71.990 16.255,74.940 16.355,74.870 16.255,77.820 16.355,77.750 16.255,80.700 16.355,80.630 16.255,83.580 16.355,83.510 16.255,86.460 16.355,86.390 16.255,89.340 16.355,89.270 16.255,92.220 16.355,92.150 16.255,95.100 16.355,95.030 16.255,97.980 16.355,97.910
00009 16.255,1.590 16.355,1.520 16.255,4.470 16.355,4.400 16.255,7.350 16.355,7.280 16.255,10.230 16.355,10.160 16.255,13.110 16.355,13.040 16.255,15.990 16.355,15.920 16.255,18.870 16.355,18.800 16.255,21.750 16.355,21.680 16.255,24.630 16.355,24.560 16.255,73.430 16.355,73.500 16.255,76.310 16.355,76.380 16.255,79.190 16.355,79.260 16.255,82.070 16.355,82.140 16.255,84.950 16.355,85.020 16.255,87.830 16.355,87.900 16.255,90.710 16.355,90.780 16.255,93.590 16.355,93.660 16.255,96.470 16.355,96.540 16.255,99.350 16.355,99.420
0000A 16.625,2.960 16.525,3.030 16.625,5.840 16.525,5.910 16.625,8.720 16.525,8.790 16.625,11.600 16.525,11.670 16.625,14.480 16.525,14.550 16.625,17.360 16.525,17.430 16.625,20.240 16.525,20.310 16.625,23.120 16.525,23.190 16.625,26.000 16.525,26.070 16.625,72.060 16.525,71.990 16.625,74.940 16.525,74.870 16.625,77.820 16.525,77.750 16.625,80.700 16.525,80.630 16.625,83.580 16.525,83.510 16.625,86.460 16.525,86.390 16.625,89.340 16.525,89.270 16.625,92.220 16.525,92.150 16.625,95.100 16.525,95.030 16.625,97.980 16.525,97.910
0000B 16.625,1.590 16.525,1.520 16.625,4.470 16.525,4.400 16.625,7.350 16.525,7.280 16.625,10.230 16.525,10.160 16.625,13.110 16.525,13.040 16.625,15.990 16.525,15.920 16.625,18.870 16.525,18.800 16.625,21.750 16.525,21.680 16.625,24.630 16.525,24.560 16.625,73.430 16.525,73.500 16.625,76.310 16.525,76.380 16.625,79.190 16.525,79.260 16.625,82.070 16.525,82.140 16.625,84.950 16.525,85.020 16.625,87.830 16.525,87.900 16.625,90.710 16.525,90.780 16.625,93.590 16.525,93.660 16.625,96.470 16.525,96.540 16.625,99.350 16.525,99.420
0000C 16.795,2.960 16.895,3.030 16.795,5.840 16.895,5.910 16.795,8.720 16.895,8.790 16.795,11.600 16.895,11.670 16.795,14.480 16.895,14.550 16.795,17.360 16.895,17.430 16.795,20.240 16.895,20.310 16.795,23.120 16.895,23.190 16.795,26.000 16.895,26.070 16.795,72.060 16.895,71.990 16.795,74.940 16.895,74.870 16.795,77.820 16.895,77.750 16.795,80.700 16.895,80.630 16.795,83.580 16.895,83.510 16.795,86.460 16.895,86.390 16.795,89.340 16.895,89.270 16.795,92.220 16.895,92.150 16.795,95.100 16.895,95.030 16.795,97.980 16.895,97.910
0000D 16.795,1.590 16.895,1.520 16.795,4.470 16.895,4.400 16.795,7.350 16.895,7.280 16.795,10.230 16.895,10.160 16.795,13.110 16.895,13.040 16.795,15.990 16.895,15.920 16.795,18.870 16.895,18.800 16.795,21.750 16.895,21.680 16.795,24.630 16.895,24.560 16.795,73.430 16.895,73.500 16.795,76.310 16.895,76.380 16.795,79.190 16.895,79.260 16.795,82.070 16.895,82.140 16.795,84.950 16.895,85.020 16.795,87.830 16.895,87.900 16.795,90.710 16.895,90.780 16.795,93.590 16.895,93.660 16.795,96.470 16.895,96.540 16.795,99.350 16.895,99.420
0000E 17.165,2.960 17.065,3.030 17.165,5.840 17.065,5.910 17.165,8.720 17.065,8.790 17.165,11.600 17.065,11.670 17.165,14.480 17.065,14.550 17.165,17.360 17.065,17.430 17.165,20.240 17.065,20.310 17.165,23.120 17.065,23.190 17.165,26.000 17.065,26.070 17.165,72.060 17.065,71.990 17.165,74.940 17.065,74.870 17.165,77.820 17.065,77.750 17.165,80.700 17.065,80.630 17.165,83.580 17.065,83.510 17.165,86.460 17.065,86.390 17.165,89.340 17.065,89.270 17.165,92.220 17.065,92.150 17.165,95.100 17.065,95.030 17.165,97.980 17.065,97.910
0000F 17.165,1.590 17.065,1.520 17.165,4.470 17.065,4.400 17.165,7.350 17.065,7.280 17.165,10.230 17.065,10.160 17.165,13.110 17.065,13.040 17.165,15.990 17.065,15.920 17.165,18.870 17.065,18.800 17.165,21.750 17.065,21.680 17.165,24.630 17.065,24.560 17.165,73.430 17.065,73.500 17.165,76.310 17.065,76.380 17.165,79.190 17.065,79.260 17.165,82.070 17.065,82.140 17.165,84.950 17.065,85.020 17.165,87.830 17.065,87.900 17.165,90.710 17.065,90.780 17.165,93.590 17.065,93.660 17.165,96.470 17.065,96.540 17.165,99.350 17.065,99.420
00010 17.335,2.960 17.435,3.030 17.335,5.840 17.435,5.910 17.335,8.720 17.435,8.790 17.335,11.600 17.435,11.670 17.335,14.480 17.435,14.550 17.335,17.360 17.435,17.430 17.335,20.240 17.435,20.310 17.335,23.120 17.435,23.190 17.335,26.000 17.435,26.070 17.335,72.060 17.435,71.990 17.335,74.940 17.435,74.870 17.335,77.820 17.435,77.750 17.335,80.700 17.435,80.630 17.335,83.580 17.435,83.510 17.335,86.460 17.435,86.390 17.335,89.340 17.435,89.270 17.335,92.220 17.435,92.150 17.335,95.100 17.435,95.030 17.335,97.980 17.435,97.910
00011 17.335,1.590 17.435,1.520 17.335,4.470 17.435,4.400 17.335,7.350 17.435,7.280 17.335,10.230 17.435,10.160 17.335,13.110 17.435,13.040 17.335,15.990 17.435,15.920 17.335,18.870 17.435,18.800 17.335,21.750 17.435,21.680 17.335,24.630 17.435,24.560 17.335,73.430 17.435,73.500 17.335,76.310 17.435,76.380 17.335,79.190 17.435,79.260 17.335,82.070 17.435,82.140 17.335,84.950 17.435,85.020 17.335,87.830 17.435,87.900 17.335,90.710 17.435,90.780 17.335,93.590 17.435,93.660 17.335,96.470 17.435,96.540 17.335,99.350 17.435,99.420
00012 17.705,2.960 17.605,3.030 17.705,5.840 17.605,5.910 17.705,8.720 17.605,8.790 17.705,11.600 17.605,11.670 17.705,14.480 17.605,14.550 17.705,17.360 17.605,17.430 17.705,20.240 17.605,20.310 17.705,23.120 17.605,23.190 17.705,26.000 17.605,26.070 17.705,72.060 17.605,71.990 17.705,74.940 17.605,74.870 17.705,77.820 17.605,77.750 17.705,80.700 17.605,80.630 17.705,83.580 17.605,83.510 17.705,86.460 17.605,86.390 17.705,89.340 17.605,89.270 17.705,92.220 17.605,92.150 17.705,95.100 17.605,95.030 17.705,97.980 17.605,97.910
00013 17.705,1.590 17.605,1.520 17.705,4.470 17.605,4.400 17.705,7.350 17.605,7.280 17.705,10.230 17.605,10.160 17.705,13.110 17.605,13.040 17.705,15.990 17.605,15.920 17.705,18.870 17.605,18.800 17.705,21.750 17.605,21.680 17.705,24.630 17.605,24.560 17.705,73.430 17.605,73.500 17.705,76.310 17.605,76.380 17.705,79.190 17.605,79.260 17.705,82.070 17.605,82.140 17.705,84.950 17.605,85.020 17.705,87.830 17.605,87.900 17.705,90.710 17.605,90.780 17.705,93.590 17.605,93.660 17.705,96.470 17.605,96.540 17.705,99.350 17.605,99.420
00014 17.875,2.960 17.975,3.030 17.875,5.840 17.975,5.910 17.875,8.720 17.975,8.790 17.875,11.600 17.975,11.670 17.875,14.480 17.975,14.550 17.875,17.360 17.975,17.430 17.875,20.240 17.975,20.310 17.875,23.120 17.975,23.190 17.875,26.000 17.975,26.070 17.875,72.060 17.975,71.990 17.875,74.940 17.975,74.870 17.875,77.820 17.975,77.750 17.875,80.700 17.975,80.630 17.875,83.580 17.975,83.510 17.875,86.460 17.975,86.390 17.875,89.340 17.975,89.270 17.875,92.220 17.975,92.150 17.875,95.100 17.975,95.030 17.875,97.980 17.975,97.910
00015 17.875,1.590 17.975,1.520 17.875,4.470 17.975,4.400 17.875,7.350 17.975,7.280 17.875,10.230 17.975,10.160 17.875,13.110 17.975,13.040 17.875,15.990 17.975,15.920 17.875,18.870 17.975,18.800 17.875,21.750 17.975,21.680 17.875,24.630 17.975,24.560 17.875,73.430 17.975,73.500 17.875,76.310 17.975,76.380 17.875,79.190 17.975,79.260 17.875,82.070 17.975,82.140 17.875,84.950 17.975,85.020 17.875,87.830 17.975,87.900 17.875,90.710 17.975,90.780 17.875,93.590 17.975,93.660 17.875,96.470 17.975,96.540 17.875,99.350 17.975,99.420
00016 18.245,2.960 18.145,3.030 18.245,5.840 18.145,5.910 18.245,8.720 18.145,8.790 18.245,11.600 18.145,11.670 18.245,14.480 18.145,14.550 18.245,17.360 18.145,17.430 18.245,20.240 18.145,20.310 18.245,23.120 18.145,23.190 18.245,26.000 18.145,26.070 18.245,72.060 18.145,71.990 18.245,74.940 18.145,74.870 18.245,77.820 18.145,77.750 18.245,80.700 18.145,80.630 18.245,83.580 18.145,83.510 18.245,86.460 18.145,86.390 18.245,89.340 18.145,89.270 18.245,92.220 18.145,92.150 18.245,95.100 18.145,95.030 18.245,97.980 18.145,97.910
00017 18.245,1.590 18.145,1.520 18.245,4.470 18.145,4.400 18.245,7.350 18.145,7.280 18.245,10.230 18.145,10.160 18.245,13.110 18.145,13.040 18.245,15.990 18.145,15.920 18.245,18.870 18.145,18.800 18.245,21.750 18.145,21.680 18.245,24.630 18.145,24.560 18.245,73.430 18.145,73.500 18.245,76.310 18.145,76.380 18.245,79.190 18.145,79.260 18.245,82.070 18.145,82.140 18.245,84.950 18.145,85.020 18.245,87.830 18.145,87.900 18.245,90.710 18.145,90.780 18.245,93.590 18.145,93.660 18.245,96.470 18.145,96.540 18.245,99.350 18.145,99.420
00018 18.415,2.960 18.515,3.030 18.415,5.840 18.515,5.910 18.415,8.720 18.515,8.790 18.415,11.600 18.515,11.670 18.415,14.480 18.515,14.550 18.415,17.360 18.515,17.430 18.415,20.240 18.515,20.310 18.415,23.120 18.515,23.190 18.415,26.000 18.515,26.070 18.415,72.060 18.515,71.990 18.415,74.940 18.515,74.870 18.415,77.820 18.515,77.750 18.415,80.700 18.515,80.630 18.415,83.580 18.515,83.510 18.415,86.460 18.515,86.390 18.415,89.340 18.515,89.270 18.415,92.220 18.515,92.150 18.415,95.100 18.515,95.030 18.415,97.980 18.515,97.910
00019 18.415,1.590 18.515,1.520 18.415,4.470 18.515,4.400 18.415,7.350 18.515,7.280 18.415,10.230 18.515,10.160 18.415,13.110 18.515,13.040 18.415,15.990 18.515,15.920 18.415,18.870 18.515,18.800 18.415,21.750 18.515,21.680 18.415,24.630 18.515,24.560 18.415,73.430 18.515,73.500 18.415,76.310 18.515,76.380 18.415,79.190 18.515,79.260 18.415,82.070 18.515,82.140 18.415,84.950 18.515,85.020 18.415,87.830 18.515,87.900 18.415,90.710 18.515,90.780 18.415,93.590 18.515,93.660 18.415,96.470 18.515,96.540 18.415,99.350 18.515,99.420
0001A 18.785,2.960 18.685,3.030 18.785,5.840 18.685,5.910 18.785,8.720 18.685,8.790 18.785,11.600 18.685,11.670 18.785,14.480 18.685,14.550 18.785,17.360 18.685,17.430 18.785,20.240 18.685,20.310 18.785,23.120 18.685,23.190 18.785,26.000 18.685,26.070 18.785,72.060 18.685,71.990 18.785,74.940 18.685,74.870 18.785,77.820 18.685,77.750 18.785,80.700 18.685,80.630 18.785,83.580 18.685,83.510 18.785,86.460 18.685,86.390 18.785,89.340 18.685,89.270 18.785,92.220 18.685,92.150 18.785,95.100 18.685,95.030 18.785,97.980 18.685,97.910
0001B 18.785,1.590 18.685,1.520 18.785,4.470 18.685,4.400 18.785,7.350 18.685,7.280 18.785,10.230 18.685,10.160 18.785,13.110 18.685,13.040 18.785,15.990 18.685,15.920 18.785,18.870 18.685,18.800 18.785,21.750 18.685,21.680 18.785,24.630 18.685,24.560 18.785,73.430 18.685,73.500 18.785,76.310 18.685,76.380 18.785,79.190 18.685,79.260 18.785,82.070 18.685,82.140 18.785,84.950 18.685,85.020 18.785,87.830 18.685,87.900 18.785,90.710 18.685,90.780 18.785,93.590 18.685,93.660 18.785,96.470 18.685,96.540 18.785,99.350 18.685,99.420
0001C 18.955,2.960 19.055,3.030 18.955,5.840 19.055,5.910 18.955,8.720 19.055,8.790 18.955,11.600 19.055,11.670 18.955,14.480 19.055,14.550 18.955,17.360 19.055,17.430 18.955,20.240 19.055,20.310 18.955,23.120 19.055,23.190 18.955,26.000 19.055,26.070 18.955,72.060 19.055,71.990 18.955,74.940 19.055,74.870 18.955,77.820 19.055,77.750 18.955,80.700 19.055,80.630 18.955,83.580 19.055,83.510 18.955,86.460 19.055,86.390 18.955,89.340 19.055,89.270 18.955,92.220 19.055,92.150 18.955,95.100 19.055,95.030 18.955,97.980 19.055,97.910
0001D 18.955,1.590 19.055,1.520 18.955,4.470 19.055,4.400 18.955,7.350 19.055,7.280 18.955,10.230 19.055,10.160 18.955,13.110 19.055,13.040 18.955,15.990 19.055,15.920 18.955,18.870 19.055,18.800 18.955,21.750 19.055,21.680 18.955,24.630 19.055,24.560 18.955,73.430 19.055,73.500 18.955,76.310 19.055,76.380 18.955,79.190 19.055,79.260 18.955,82.070 19.055,82.140 18.955,84.950 19.055,85.020 18.955,87.830 19.055,87.900 18.955,90.710 19.055,90.780 18.955,93.590 19.055,93.660 18.955,96.470 19.055,96.540 18.955,99.350 19.055,99.420
0001E 19.325,2.960 19.225,3.030 19.325,5.840 19.225,5.910 19.325,8.720 19.225,8.790 19.325,11.600 19.225,11.670 19.325,14.480 19.225,14.550 19.325,17.360 19.225,17.430 19.325,20.240 19.225,20.310 19.325,23.120 19.225,23.190 19.325,26.000 19.225,26.070 19.325,72.060 19.225,71.990 19.325,74.940 19.225,74.870 19.325,77.820 19.225,77.750 19.325,80.700 19.225,80.630 19.325,83.580 19.225,83.510 19.325,86.460 19.225,86.390 19.325,89.340 19.225,89.270 19.325,92.220 19.225,92.150 19.325,95.100 19.225,95.030 19.325,97.980 19.225,97.910
0001F 19.325,1.590 19.225,1.520 19.325,4.470 19.225,4.400 19.325,7.350 19.225,7.280 19.325,10.230 19.225,10.160 19.325,13.110 19.225,13.040 19.325,15.990 19.225,15.920 19.325,18.870 19.225,18.800 19.325,21.750 19.225,21.680 19.325,24.630 19.225,24.560 19.325,73.430 19.225,73.500 19.325,76.310 19.225,76.380 19.325,79.190 19.225,79.260 19.325,82.070 19.225,82.140 19.325,84.950 19.225,85.020 19.325,87.830 19.225,87.900 19.325,90.710 19.225,90.780 19.325,93.590 19.225,93.660 19.325,96.470 19.225,96.540 19.325,99.350 19.225,99.420

69
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.cpf Normal file
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# cpf_memcomp Version: 4.0.6-EAC
# common_memcomp Version: c0.1.0-EAC
# lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37
#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# CPF Macro-Model for High Density Two Port Register File SVT MVT Compiler
#
# Instance Name: rf2_32x19_wm0
# Words: 32
# Bits: 19
# Mux: 2
# Drive: 6
# Write Mask: Off
# Write Thru: Off
# Extra Margin Adjustment: On
# Test Muxes On
# Power Gating: Off
# Retention: On
# Pipeline: Off
# Read Disturb Test: Off
#
# Creation Date: Mon Nov 11 11:59:51 2019
# Version: r4p0
#
set_cpf_version 1.1
set_macro_model rf2_32x19_wm0
#The Voltages Specified in this macro-model not real. They are dummy values suggested by Cadence.
create_nominal_condition -name nc_on -voltage 1 -ground_voltage 0.0 -state on
create_nominal_condition -name nc_off -voltage 0.0 -ground_voltage 0.0 -state off
create_power_domain -name PDPE -default \
-boundary_ports { CENYA AYA[*] CENYB AYB[*] QA[*] SOA[*] SOB[*] CLKA CENA AA[*] CLKB CENB AB[*] DB[*] EMAA[*] EMASA EMAB[*] TENA TCENA TAA[*] TENB TCENB TAB[*] TDB[*] SIA[*] SEA DFTRAMBYP SIB[*] SEB COLLDISN } \
-instances { clk0_int CENA_int AA_int[4] AA_int[3] AA_int[2] AA_int[1] AA_int[0] clk1_int CENB_int AB_int[4] AB_int[3] AB_int[2] AB_int[1] AB_int[0] DB_int[18] DB_int[17] DB_int[16] DB_int[15] DB_int[14] DB_int[13] DB_int[12] DB_int[11] DB_int[10] DB_int[9] DB_int[8] DB_int[7] DB_int[6] DB_int[5] DB_int[4] DB_int[3] DB_int[2] DB_int[1] DB_int[0] EMAA_int[2] EMAA_int[1] EMAA_int[0] EMASA_int EMAB_int[2] EMAB_int[1] EMAB_int[0] TENA_int TCENA_int TAA_int[4] TAA_int[3] TAA_int[2] TAA_int[1] TAA_int[0] TENB_int TCENB_int TAB_int[4] TAB_int[3] TAB_int[2] TAB_int[1] TAB_int[0] TDB_int[18] TDB_int[17] TDB_int[16] TDB_int[15] TDB_int[14] TDB_int[13] TDB_int[12] TDB_int[11] TDB_int[10] TDB_int[9] TDB_int[8] TDB_int[7] TDB_int[6] TDB_int[5] TDB_int[4] TDB_int[3] TDB_int[2] TDB_int[1] TDB_int[0] SIA_int[1] SIA_int[0] SEA_int DFTRAMBYP_int SIB_int[1] SIB_int[0] SEB_int COLLDISN_int }
update_power_domain -name PDPE \
-primary_power_net VDDPE -primary_ground_net VSSE
create_power_domain -name PDCE \
-boundary_ports { RET1N } \
-instances { mem* RET1N_int }
update_power_domain -name PDCE \
-primary_power_net VDDCE -primary_ground_net VSSE
# mode A1/A2 - Normal/Selective_Precharge
create_power_mode -name PM1 -domain_conditions \
{PDPE@nc_on PDCE@nc_on} -default
#mode A3 - Retention mode
create_power_mode -name PM2 -domain_conditions \
{PDPE@nc_off PDCE@nc_on}
#mode A4 - power down mode
create_power_mode -name PM3 -domain_conditions \
{PDPE@nc_off PDCE@nc_off}
end_macro_model rf2_32x19_wm0

381
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.ctl Normal file
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/* ctl_memcomp Version: 4.0.5-EAC3 */
/* common_memcomp Version: 4.0.5.2-amci */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// CTL model for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x19_wm0
// Words: 32
// Bits: 19
// Mux: 2
// Drive: 6
// Write Mask: Off
// Write Thru: Off
// Extra Margin Adjustment: On
// Redundant Columns: 2
// Test Muxes On
// Power Gating: Off
// Retention: On
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Mon Nov 11 11:59:52 2019
// Version: r4p0
STIL 1.0 {
CTL P2001.10;
Design P2001.01;
}
Header {
Title "CTL model for `rf2_32x19_wm0";
}
Signals {
"CENYA" Out;
"AYA[4]" Out;
"AYA[3]" Out;
"AYA[2]" Out;
"AYA[1]" Out;
"AYA[0]" Out;
"CENYB" Out;
"AYB[4]" Out;
"AYB[3]" Out;
"AYB[2]" Out;
"AYB[1]" Out;
"AYB[0]" Out;
"QA[18]" Out;
"QA[17]" Out;
"QA[16]" Out;
"QA[15]" Out;
"QA[14]" Out;
"QA[13]" Out;
"QA[12]" Out;
"QA[11]" Out;
"QA[10]" Out;
"QA[9]" Out;
"QA[8]" Out;
"QA[7]" Out;
"QA[6]" Out;
"QA[5]" Out;
"QA[4]" Out;
"QA[3]" Out;
"QA[2]" Out;
"QA[1]" Out;
"QA[0]" Out;
"SOA[1]" Out;
"SOA[0]" Out;
"SOB[1]" Out;
"SOB[0]" Out;
"CLKA" In;
"CENA" In;
"AA[4]" In;
"AA[3]" In;
"AA[2]" In;
"AA[1]" In;
"AA[0]" In;
"CLKB" In;
"CENB" In;
"AB[4]" In;
"AB[3]" In;
"AB[2]" In;
"AB[1]" In;
"AB[0]" In;
"DB[18]" In;
"DB[17]" In;
"DB[16]" In;
"DB[15]" In;
"DB[14]" In;
"DB[13]" In;
"DB[12]" In;
"DB[11]" In;
"DB[10]" In;
"DB[9]" In;
"DB[8]" In;
"DB[7]" In;
"DB[6]" In;
"DB[5]" In;
"DB[4]" In;
"DB[3]" In;
"DB[2]" In;
"DB[1]" In;
"DB[0]" In;
"EMAA[2]" In;
"EMAA[1]" In;
"EMAA[0]" In;
"EMASA" In;
"EMAB[2]" In;
"EMAB[1]" In;
"EMAB[0]" In;
"TENA" In;
"TCENA" In;
"TAA[4]" In;
"TAA[3]" In;
"TAA[2]" In;
"TAA[1]" In;
"TAA[0]" In;
"TENB" In;
"TCENB" In;
"TAB[4]" In;
"TAB[3]" In;
"TAB[2]" In;
"TAB[1]" In;
"TAB[0]" In;
"TDB[18]" In;
"TDB[17]" In;
"TDB[16]" In;
"TDB[15]" In;
"TDB[14]" In;
"TDB[13]" In;
"TDB[12]" In;
"TDB[11]" In;
"TDB[10]" In;
"TDB[9]" In;
"TDB[8]" In;
"TDB[7]" In;
"TDB[6]" In;
"TDB[5]" In;
"TDB[4]" In;
"TDB[3]" In;
"TDB[2]" In;
"TDB[1]" In;
"TDB[0]" In;
"RET1N" In;
"SIA[1]" In;
"SIA[0]" In;
"SEA" In;
"DFTRAMBYP" In;
"SIB[1]" In;
"SIB[0]" In;
"SEB" In;
"COLLDISN" In;
}
SignalGroups {
"all_inputs" = '"CLKA" + "CENA" + "AA[4]" + "AA[3]" + "AA[2]" + "AA[1]" + "AA[0]" +
"CLKB" + "CENB" + "AB[4]" + "AB[3]" + "AB[2]" + "AB[1]" + "AB[0]" + "DB[18]" +
"DB[17]" + "DB[16]" + "DB[15]" + "DB[14]" + "DB[13]" + "DB[12]" + "DB[11]" + "DB[10]" +
"DB[9]" + "DB[8]" + "DB[7]" + "DB[6]" + "DB[5]" + "DB[4]" + "DB[3]" + "DB[2]" +
"DB[1]" + "DB[0]" + "EMAA[2]" + "EMAA[1]" + "EMAA[0]" + "EMASA" + "EMAB[2]" +
"EMAB[1]" + "EMAB[0]" + "TENA" + "TCENA" + "TAA[4]" + "TAA[3]" + "TAA[2]" + "TAA[1]" +
"TAA[0]" + "TENB" + "TCENB" + "TAB[4]" + "TAB[3]" + "TAB[2]" + "TAB[1]" + "TAB[0]" +
"TDB[18]" + "TDB[17]" + "TDB[16]" + "TDB[15]" + "TDB[14]" + "TDB[13]" + "TDB[12]" +
"TDB[11]" + "TDB[10]" + "TDB[9]" + "TDB[8]" + "TDB[7]" + "TDB[6]" + "TDB[5]" +
"TDB[4]" + "TDB[3]" + "TDB[2]" + "TDB[1]" + "TDB[0]" + "RET1N" + "SIA[1]" + "SIA[0]" +
"SEA" + "DFTRAMBYP" + "SIB[1]" + "SIB[0]" + "SEB" + "COLLDISN"';
"all_outputs" = '"CENYA" + "AYA[4]" + "AYA[3]" + "AYA[2]" + "AYA[1]" + "AYA[0]" +
"CENYB" + "AYB[4]" + "AYB[3]" + "AYB[2]" + "AYB[1]" + "AYB[0]" + "QA[18]" + "QA[17]" +
"QA[16]" + "QA[15]" + "QA[14]" + "QA[13]" + "QA[12]" + "QA[11]" + "QA[10]" + "QA[9]" +
"QA[8]" + "QA[7]" + "QA[6]" + "QA[5]" + "QA[4]" + "QA[3]" + "QA[2]" + "QA[1]" +
"QA[0]" + "SOA[1]" + "SOA[0]" + "SOB[1]" + "SOB[0]"';
"all_ports" = '"all_inputs" + "all_outputs"';
"_pi" = '"CLKA" + "CENA" + "AA[4]" + "AA[3]" + "AA[2]" + "AA[1]" + "AA[0]" + "CLKB" +
"CENB" + "AB[4]" + "AB[3]" + "AB[2]" + "AB[1]" + "AB[0]" + "DB[18]" + "DB[17]" +
"DB[16]" + "DB[15]" + "DB[14]" + "DB[13]" + "DB[12]" + "DB[11]" + "DB[10]" + "DB[9]" +
"DB[8]" + "DB[7]" + "DB[6]" + "DB[5]" + "DB[4]" + "DB[3]" + "DB[2]" + "DB[1]" +
"DB[0]" + "EMAA[2]" + "EMAA[1]" + "EMAA[0]" + "EMASA" + "EMAB[2]" + "EMAB[1]" +
"EMAB[0]" + "TENA" + "TCENA" + "TAA[4]" + "TAA[3]" + "TAA[2]" + "TAA[1]" + "TAA[0]" +
"TENB" + "TCENB" + "TAB[4]" + "TAB[3]" + "TAB[2]" + "TAB[1]" + "TAB[0]" + "TDB[18]" +
"TDB[17]" + "TDB[16]" + "TDB[15]" + "TDB[14]" + "TDB[13]" + "TDB[12]" + "TDB[11]" +
"TDB[10]" + "TDB[9]" + "TDB[8]" + "TDB[7]" + "TDB[6]" + "TDB[5]" + "TDB[4]" +
"TDB[3]" + "TDB[2]" + "TDB[1]" + "TDB[0]" + "RET1N" + "SIA[1]" + "SIA[0]" + "SEA" +
"DFTRAMBYP" + "SIB[1]" + "SIB[0]" + "SEB" + "COLLDISN"';
"_po" = '"CENYA" + "AYA[4]" + "AYA[3]" + "AYA[2]" + "AYA[1]" + "AYA[0]" + "CENYB" +
"AYB[4]" + "AYB[3]" + "AYB[2]" + "AYB[1]" + "AYB[0]" + "QA[18]" + "QA[17]" + "QA[16]" +
"QA[15]" + "QA[14]" + "QA[13]" + "QA[12]" + "QA[11]" + "QA[10]" + "QA[9]" + "QA[8]" +
"QA[7]" + "QA[6]" + "QA[5]" + "QA[4]" + "QA[3]" + "QA[2]" + "QA[1]" + "QA[0]" +
"SOA[1]" + "SOA[0]" + "SOB[1]" + "SOB[0]"';
"_si" = '"SIA[0]" + "SIA[1]" + "SIB[0]" + "SIB[1]"' {ScanIn; }
"_so" = '"SOA[0]" + "SOA[1]" + "SOB[0]" + "SOB[1]"' {ScanOut; }
}
ScanStructures {
ScanChain "chain_rf2_32x19_wm0_1" {
ScanLength 9;
ScanCells "uDQA8" "uDQA7" "uDQA6" "uDQA5" "uDQA4" "uDQA3" "uDQA2" "uDQA1" "uDQA0" ;
ScanIn "SIA[0]";
ScanOut "SOA[0]";
ScanEnable "SEA";
ScanMasterClock "CLKA";
}
ScanChain "chain_rf2_32x19_wm0_2" {
ScanLength 10;
ScanCells "uDQA9" "uDQA10" "uDQA11" "uDQA12" "uDQA13" "uDQA14" "uDQA15" "uDQA16" "uDQA17" "uDQA18" ;
ScanIn "SIA[1]";
ScanOut "SOA[1]";
ScanEnable "SEA";
ScanMasterClock "CLKA";
}
ScanChain "chain_rf2_32x19_wm0_3" {
ScanLength 9;
ScanCells "uDQB8" "uDQB7" "uDQB6" "uDQB5" "uDQB4" "uDQB3" "uDQB2" "uDQB1" "uDQB0" ;
ScanIn "SIB[0]";
ScanOut "SOB[0]";
ScanEnable "SEB";
ScanMasterClock "CLKB";
}
ScanChain "chain_rf2_32x19_wm0_4" {
ScanLength 10;
ScanCells "uDQB9" "uDQB10" "uDQB11" "uDQB12" "uDQB13" "uDQB14" "uDQB15" "uDQB16" "uDQB17" "uDQB18" ;
ScanIn "SIB[1]";
ScanOut "SOB[1]";
ScanEnable "SEB";
ScanMasterClock "CLKB";
}
}
Timing {
WaveformTable "_default_WFT_" {
Period '100ns';
Waveforms {
"all_inputs" {
01ZN { '0ns' D/U/Z/N; }
}
"all_outputs" {
XHTL { '40ns' X/H/T/L; }
}
"CLKA" {
P { '0ns' D; '45ns' U; '55ns' D; }
}
"CLKB" {
P { '0ns' D; '45ns' U; '55ns' D; }
}
}
}
}
Procedures {
"capture" {
W "_default_WFT_";
V { "_pi" = #; "_po" = #; }
}
"capture_CLK" {
W "_default_WFT_";
V {"_pi" = #; "_po" = #;"CLKA" = P;"CLKB" = P; }
}
"load_unload" {
W "_default_WFT_";
V { "CLKA" = 0; "CLKB" = 0; "_si" = \r2 N; "_so" =\r2 X; "SEA" = 1; "SEB" = 1; "DFTRAMBYP" = 1; }
Shift {
V { "CLKA" = P; "CLKB" = P; "_si" = \r2 #; "_so" = \r2 #; }
}
}
}
MacroDefs {
"test_setup" {
W "_default_WFT_";
C {"all_inputs" = \r60 N; "all_outputs" = \r34 X; }
V { "CLKA" = P; "CLKB" = P; }
}
}
Environment "rf2_32x19_wm0" {
CTL {
}
CTL Internal_scan {
TestMode InternalTest;
Focus Top {
}
Internal {
"SIA[0]" {
CaptureClock "CLKA" {
LeadingEdge;
}
DataType ScanDataIn {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SIA[1]" {
CaptureClock "CLKA" {
LeadingEdge;
}
DataType ScanDataIn {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SOA[0]" {
LaunchClock "CLKA" {
LeadingEdge;
}
DataType ScanDataOut {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SOA[1]" {
LaunchClock "CLKA" {
LeadingEdge;
}
DataType ScanDataOut {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SEA" {
DataType ScanEnable {
ActiveState ForceUp;
}
}
"CLKA" {
DataType ScanMasterClock MasterClock;
}
"SIB[0]" {
CaptureClock "CLKB" {
LeadingEdge;
}
DataType ScanDataIn {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SIB[1]" {
CaptureClock "CLKB" {
LeadingEdge;
}
DataType ScanDataIn {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SOB[0]" {
LaunchClock "CLKB" {
LeadingEdge;
}
DataType ScanDataOut {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SOB[1]" {
LaunchClock "CLKB" {
LeadingEdge;
}
DataType ScanDataOut {
ScanDataType Internal;
}
ScanStyle MultiplexedData;
}
"SEB" {
DataType ScanEnable {
ActiveState ForceUp;
}
}
"CLKB" {
DataType ScanMasterClock MasterClock;
}
}
}
}
Environment dftSpec {
CTL {
}
CTL all_dft {
TestMode ForInheritOnly;
}
}

6921
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.lef Normal file
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612
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.mdt Normal file
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// fastscan_memcomp Version: 4.0.5-EAC10
// common_memcomp Version: 4.0.5.2-amci
// lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// Fastscan model for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x19_wm0
// Words: 32
// Bits: 19
// Mux: 2
// Drive: 6
// Write Mask: Off
// Write Thru: Off
// Extra Margin Adjustment: On
// Redundant Columns: 2
// Test Muxes On
// Power Gating: Off
// Retention: On
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Mon Nov 11 11:59:53 2019
// Version: r4p0
// Modeling Assumptions: This is Sequential Synchronous Mentor model
// with Mentor ATPG primitives used to test UTI and generate test
// vectors.
//
// Modeling Limitations: None.
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
model rf2_32x19_wm0_scanflop (Q, SI, D, SE, CLK, Xout) (
input (SI) ()
input (D) ()
input (SE) ()
input (CLK) ()
input (Xout) ()
output (Q) (
primitive = _tiex mx_tiex (mx);
primitive = _tie0 m0_tie0 (m0_0);
primitive = _tie0 m1_tie0 (m0_1);
primitive = _mux m1 (D, SI, SE, n1);
primitive = _mux m2 (n1, mx, Xout, n2);
primitive = _dff r1 ( m0_0, m0_1, CLK, n2, Q, );
)
)
model rf2_32x19_wm0_bitcell (CLK, WRITE, READ, WA, RA, D, Xout, Q) (
intern (WA_ram, RA_ram) (array = 4:0;)
input (CLK) ()
intern (READ_ram) ()
input (WRITE) ()
input (READ) ()
input (D) ()
input (WA, RA) (array = 4:0;)
input (Xout) ()
output (Q) (
primitive = _tiex mx_tiex ( mx );
primitive = _mux WRITE_MUX ( WRITE, mx, Xout, WRITE_ram );
primitive = _mux D_mux ( D, mx, Xout, D_ram );
primitive = _mux AA0_mux ( WA[0], mx, Xout, WA_ram[0] );
primitive = _mux AA1_mux ( WA[1], mx, Xout, WA_ram[1] );
primitive = _mux AA2_mux ( WA[2], mx, Xout, WA_ram[2] );
primitive = _mux AA3_mux ( WA[3], mx, Xout, WA_ram[3] );
primitive = _mux AA4_mux ( WA[4], mx, Xout, WA_ram[4] );
primitive = _mux READ_MUX ( READ, mx, Xout, READ_ram );
primitive = _mux RA0_mux ( RA[0], mx, Xout, RA_ram[0] );
primitive = _mux RA1_mux ( RA[1], mx, Xout, RA_ram[1] );
primitive = _mux RA2_mux ( RA[2], mx, Xout, RA_ram[2] );
primitive = _mux RA3_mux ( RA[3], mx, Xout, RA_ram[3] );
primitive = _mux RA4_mux ( RA[4], mx, Xout, RA_ram[4] );
data_size = 1;
address_size = 5;
min_address = 0;
max_address = 31;
edge_trigger = w;
read_write_conflict = XW;
// Verilog RAM has no Set or Reset pin :
primitive = _cram mem ( , ,
// Following write port will Hold in-memory data when not writing.
_write { , , } (CLK, WRITE_ram, WA_ram, D_ram),
// Following read port will Hold output data after reading.
_read { , , ,} ( , READ_ram, , RA_ram, Q)
);
)
)
model rf2_32x19_wm0 (CENYA, AYA, CENYB, AYB, QA, SOA, SOB, CLKA, CENA, AA, CLKB, CENB,
AB, DB, EMAA, EMASA, EMAB, TENA, TCENA, TAA, TENB, TCENB, TAB, TDB, RET1N, SIA,
SEA, DFTRAMBYP, SIB, SEB, COLLDISN) (
input (CLKA) ()
input (CENA) ()
input (AA) (array = 4 : 0; )
input (CLKB) ()
input (CENB) ()
input (AB) (array = 4 : 0; )
input (DB) (array = 18 : 0; )
input (EMAA) (array = 2 : 0; used=false;fault=none;)
input (EMASA) (used=false;fault=none;)
input (EMAB) (array = 2 : 0; used=false;fault=none;)
input (TENA) ()
input (TCENA) ()
input (TAA) (array = 4 : 0; )
input (TENB) ()
input (TCENB) ()
input (TAB) (array = 4 : 0; )
input (TDB) (array = 18 : 0; )
input (RET1N) (used=false;fault=none;)
input (SIA) (array = 1 : 0; )
input (SEA) ()
input (DFTRAMBYP) ()
input (SIB) (array = 1 : 0; )
input (SEB) ()
input (COLLDISN) (used=false;fault=none;)
intern (mtie_sel0) (primitive = _tie0 m0_sel0 ( mtie_sel0 );)
intern (tiex_readq) (primitive = _tiex mtiex_readq(tiex_readq);)
intern (mlc_bmuxsel) (primitive = _tie0 m0_bmuxsel ( mlc_bmuxsel );)
intern (BUS_SIA) (array = 1 : 0;
primitive = _buf wbSIA0 (SIA[0], BUS_SIA[0]);
primitive = _buf wbSIA1 (SIA[1], BUS_SIA[1]);
)
intern (BUS_AA) (array = 4 : 0;
primitive = _buf bBUS_AA0 ( AA[0], BUS_AA[0]);
primitive = _buf bBUS_AA1 ( AA[1], BUS_AA[1]);
primitive = _buf bBUS_AA2 ( AA[2], BUS_AA[2]);
primitive = _buf bBUS_AA3 ( AA[3], BUS_AA[3]);
primitive = _buf bBUS_AA4 ( AA[4], BUS_AA[4]);
)
intern (BMUX_AA) ( array = 4 : 0;
primitive = _mux maA0(TAA[0], BUS_AA[0], TENA, BMUX_AA[0]);
primitive = _mux maA1(TAA[1], BUS_AA[1], TENA, BMUX_AA[1]);
primitive = _mux maA2(TAA[2], BUS_AA[2], TENA, BMUX_AA[2]);
primitive = _mux maA3(TAA[3], BUS_AA[3], TENA, BMUX_AA[3]);
primitive = _mux maA4(TAA[4], BUS_AA[4], TENA, BMUX_AA[4]);
)
intern (BMUXSEL_AA) ( array = 4 : 0;
primitive = _mux mBMUXSEL_AA0(mlc_bmuxsel, BMUX_AA[0], DFTRAMBYP, BMUXSEL_AA[0]);
primitive = _mux mBMUXSEL_AA1(mlc_bmuxsel, BMUX_AA[1], DFTRAMBYP, BMUXSEL_AA[1]);
primitive = _mux mBMUXSEL_AA2(mlc_bmuxsel, BMUX_AA[2], DFTRAMBYP, BMUXSEL_AA[2]);
primitive = _mux mBMUXSEL_AA3(mlc_bmuxsel, BMUX_AA[3], DFTRAMBYP, BMUXSEL_AA[3]);
primitive = _mux mBMUXSEL_AA4(mlc_bmuxsel, BMUX_AA[4], DFTRAMBYP, BMUXSEL_AA[4]);
)
output (AYA) ( array = 4 : 0;
primitive = _buf bAYA0(BMUXSEL_AA[0], AYA[0]);
primitive = _buf bAYA1(BMUXSEL_AA[1], AYA[1]);
primitive = _buf bAYA2(BMUXSEL_AA[2], AYA[2]);
primitive = _buf bAYA3(BMUXSEL_AA[3], AYA[3]);
primitive = _buf bAYA4(BMUXSEL_AA[4], AYA[4]);
)
intern (BMUX_CENA) (primitive = _mux mBMUX_CENA(TCENA, CENA, TENA, BMUX_CENA);)
intern (BMUXSEL_CENA) (primitive = _mux mBMUXSEL_CENA(mlc_bmuxsel, BMUX_CENA, DFTRAMBYP, BMUXSEL_CENA);)
output (CENYA) (primitive = _buf bCENYA(BMUXSEL_CENA, CENYA);)
intern (BMUX_AA_n) (array = 4 : 1;
primitive = _inv iBMUX_AA_n1 ( BMUX_AA[1], BMUX_AA_n[1] );
primitive = _inv iBMUX_AA_n2 ( BMUX_AA[2], BMUX_AA_n[2] );
primitive = _inv iBMUX_AA_n3 ( BMUX_AA[3], BMUX_AA_n[3] );
primitive = _inv iBMUX_AA_n4 ( BMUX_AA[4], BMUX_AA_n[4] );
)
intern (A_max) (array = 4 : 0;
primitive = _tie1 bA_max0 ( A_max[0] );
primitive = _tie1 bA_max1 ( A_max[1] );
primitive = _tie1 bA_max2 ( A_max[2] );
primitive = _tie1 bA_max3 ( A_max[3] );
primitive = _tie1 bA_max4 ( A_max[4] );
)
intern (A_max_n) (array = 4 : 0;
primitive = _inv bA_max_n0( A_max[0], A_max_n[0] );
primitive = _inv bA_max_n1( A_max[1], A_max_n[1] );
primitive = _inv bA_max_n2( A_max[2], A_max_n[2] );
primitive = _inv bA_max_n3( A_max[3], A_max_n[3] );
primitive = _inv bA_max_n4( A_max[4], A_max_n[4] );
)
intern (AA_m) (array = 4 : 0;
primitive = _and aAA_m0(BMUX_AA[0], A_max_n[0], AA_m[0] );
primitive = _and aAA_m1(BMUX_AA[1], A_max_n[1], AA_m[1] );
primitive = _and aAA_m2(BMUX_AA[2], A_max_n[2], AA_m[2] );
primitive = _and aAA_m3(BMUX_AA[3], A_max_n[3], AA_m[3] );
primitive = _and aAA_m4(BMUX_AA[4], A_max_n[4], AA_m[4] );
)
intern (m_AA) (array = 4 : 1;
primitive = _and am_AA1(BMUX_AA_n[1], A_max[1], m_AA[1] );
primitive = _and am_AA2(BMUX_AA_n[2], A_max[2], m_AA[2] );
primitive = _and am_AA3(BMUX_AA_n[3], A_max[3], m_AA[3] );
primitive = _and am_AA4(BMUX_AA_n[4], A_max[4], m_AA[4] );
)
intern (EQ_A) (array = 4 : 1;
primitive = _nor nEQ_A1(m_AA[1], AA_m[1], EQ_A[1] );
primitive = _nor nEQ_A2(m_AA[2], AA_m[2], EQ_A[2] );
primitive = _nor nEQ_A3(m_AA[3], AA_m[3], EQ_A[3] );
primitive = _nor nEQ_A4(m_AA[4], AA_m[4], EQ_A[4] );
)
intern (XoutAi) (array = 3 : 0;
primitive = _and aXoutAi0(AA_m[0], EQ_A[4], EQ_A[3], EQ_A[2], EQ_A[1], XoutAi[0]);
primitive = _and aXoutAi1(AA_m[1], EQ_A[4], EQ_A[3], EQ_A[2], XoutAi[1]);
primitive = _and aXoutAi2(AA_m[2], EQ_A[4], EQ_A[3], XoutAi[2]);
primitive = _and aXoutAi3(AA_m[3], EQ_A[4], XoutAi[3]);
)
intern (XoutAifTemp) (primitive = _or oXoutAifTemp (AA_m[4], XoutAi[0], XoutAi[1], XoutAi[2], XoutAi[3], XoutAifTemp);)
intern (XoutAif) (primitive = _and oXoutAif (XoutAifTemp, NOT_CENA, XoutAif);)
intern (nscanshiftA) (
primitive = _nor nnscanshiftA (DFTRAMBYP, SEA, nscanshiftA);)
intern (XoutaddrA) (
primitive = _and aXoutaddrA (nscanshiftA, XoutAif, XoutaddrA);)
intern (XoutAiff) (
primitive = _or oXoutAiff (XoutaddrA, XoutA, XoutAiff);)
intern (NOT_CENA) (primitive = _inv iNOT_CENA(BMUX_CENA, NOT_CENA);)
intern (NOT_DFTRAMBYP) (primitive = _inv iNOT_DFTRAMBYP(DFTRAMBYP, NOT_DFTRAMBYP);)
intern (READA) (array = 18:0;
primitive = _buf bREADA0(NOT_CENA, READA[0]);
primitive = _buf bREADA1(NOT_CENA, READA[1]);
primitive = _buf bREADA2(NOT_CENA, READA[2]);
primitive = _buf bREADA3(NOT_CENA, READA[3]);
primitive = _buf bREADA4(NOT_CENA, READA[4]);
primitive = _buf bREADA5(NOT_CENA, READA[5]);
primitive = _buf bREADA6(NOT_CENA, READA[6]);
primitive = _buf bREADA7(NOT_CENA, READA[7]);
primitive = _buf bREADA8(NOT_CENA, READA[8]);
primitive = _buf bREADA9(NOT_CENA, READA[9]);
primitive = _buf bREADA10(NOT_CENA, READA[10]);
primitive = _buf bREADA11(NOT_CENA, READA[11]);
primitive = _buf bREADA12(NOT_CENA, READA[12]);
primitive = _buf bREADA13(NOT_CENA, READA[13]);
primitive = _buf bREADA14(NOT_CENA, READA[14]);
primitive = _buf bREADA15(NOT_CENA, READA[15]);
primitive = _buf bREADA16(NOT_CENA, READA[16]);
primitive = _buf bREADA17(NOT_CENA, READA[17]);
primitive = _buf bREADA18(NOT_CENA, READA[18]);
)
intern (x_detection_CENA) (primitive = _xor xx_detection_CENA(BMUX_CENA, BMUX_CENA, x_detection_CENA);)
intern (x_detection_CLKA) (primitive = _xor xx_detection_CLKA(CLKA, CLKA, x_detection_CLKA);)
intern (aSEA) (primitive = _and a1SEA ( SEA, DFTRAMBYPinv, aSEA );)
intern (acendftA) (primitive = _and a1cendft[A] (x_detection_CENA, DFTRAMBYPinv, acendftA );)
intern (acendftCA) (primitive = _and a1cendftCA ( x_detection_CLKA, DFTRAMBYPinv, acendftCA );)
intern (XoutA) (primitive = _or oXoutA ( aSEA, acendftA, XoutA );)
intern (READ_QA) (array = 18:0;
primitive = _mux mREAD_QA0(QA[0], INT_QA[0], READA[0], READ_QA[0]);
primitive = _mux mREAD_QA1(QA[1], INT_QA[1], READA[1], READ_QA[1]);
primitive = _mux mREAD_QA2(QA[2], INT_QA[2], READA[2], READ_QA[2]);
primitive = _mux mREAD_QA3(QA[3], INT_QA[3], READA[3], READ_QA[3]);
primitive = _mux mREAD_QA4(QA[4], INT_QA[4], READA[4], READ_QA[4]);
primitive = _mux mREAD_QA5(QA[5], INT_QA[5], READA[5], READ_QA[5]);
primitive = _mux mREAD_QA6(QA[6], INT_QA[6], READA[6], READ_QA[6]);
primitive = _mux mREAD_QA7(QA[7], INT_QA[7], READA[7], READ_QA[7]);
primitive = _mux mREAD_QA8(QA[8], INT_QA[8], READA[8], READ_QA[8]);
primitive = _mux mREAD_QA9(QA[9], INT_QA[9], READA[9], READ_QA[9]);
primitive = _mux mREAD_QA10(QA[10], INT_QA[10], READA[10], READ_QA[10]);
primitive = _mux mREAD_QA11(QA[11], INT_QA[11], READA[11], READ_QA[11]);
primitive = _mux mREAD_QA12(QA[12], INT_QA[12], READA[12], READ_QA[12]);
primitive = _mux mREAD_QA13(QA[13], INT_QA[13], READA[13], READ_QA[13]);
primitive = _mux mREAD_QA14(QA[14], INT_QA[14], READA[14], READ_QA[14]);
primitive = _mux mREAD_QA15(QA[15], INT_QA[15], READA[15], READ_QA[15]);
primitive = _mux mREAD_QA16(QA[16], INT_QA[16], READA[16], READ_QA[16]);
primitive = _mux mREAD_QA17(QA[17], INT_QA[17], READA[17], READ_QA[17]);
primitive = _mux mREAD_QA18(QA[18], INT_QA[18], READA[18], READ_QA[18]);
)
intern (AAXOR) (array = 4 : 0;
primitive = _xor xAAXOR0(BMUX_AA[0], BMUX_AA[0], AAXOR[0]);
primitive = _xor xAAXOR1(BMUX_AA[1], BMUX_AA[1], AAXOR[1]);
primitive = _xor xAAXOR2(BMUX_AA[2], BMUX_AA[2], AAXOR[2]);
primitive = _xor xAAXOR3(BMUX_AA[3], BMUX_AA[3], AAXOR[3]);
primitive = _xor xAAXOR4(BMUX_AA[4], BMUX_AA[4], AAXOR[4]);
)
intern (xA_addr_temp) (primitive = _or oxA_addr_temp( AAXOR[0], AAXOR[1], AAXOR[2], AAXOR[3], AAXOR[4], xA_addr_temp);)
intern (xA_addr) (primitive = _and oxA_addr(NOT_CENA,xA_addr_temp,xA_addr);)
intern (READ_QAX) (array = 18 : 0;
primitive = _mux mREAD_QAX0 (READ_QA[0], tiex_readq, xA_addr, READ_QAX[0]);
primitive = _mux mREAD_QAX1 (READ_QA[1], tiex_readq, xA_addr, READ_QAX[1]);
primitive = _mux mREAD_QAX2 (READ_QA[2], tiex_readq, xA_addr, READ_QAX[2]);
primitive = _mux mREAD_QAX3 (READ_QA[3], tiex_readq, xA_addr, READ_QAX[3]);
primitive = _mux mREAD_QAX4 (READ_QA[4], tiex_readq, xA_addr, READ_QAX[4]);
primitive = _mux mREAD_QAX5 (READ_QA[5], tiex_readq, xA_addr, READ_QAX[5]);
primitive = _mux mREAD_QAX6 (READ_QA[6], tiex_readq, xA_addr, READ_QAX[6]);
primitive = _mux mREAD_QAX7 (READ_QA[7], tiex_readq, xA_addr, READ_QAX[7]);
primitive = _mux mREAD_QAX8 (READ_QA[8], tiex_readq, xA_addr, READ_QAX[8]);
primitive = _mux mREAD_QAX9 (READ_QA[9], tiex_readq, xA_addr, READ_QAX[9]);
primitive = _mux mREAD_QAX10 (READ_QA[10], tiex_readq, xA_addr, READ_QAX[10]);
primitive = _mux mREAD_QAX11 (READ_QA[11], tiex_readq, xA_addr, READ_QAX[11]);
primitive = _mux mREAD_QAX12 (READ_QA[12], tiex_readq, xA_addr, READ_QAX[12]);
primitive = _mux mREAD_QAX13 (READ_QA[13], tiex_readq, xA_addr, READ_QAX[13]);
primitive = _mux mREAD_QAX14 (READ_QA[14], tiex_readq, xA_addr, READ_QAX[14]);
primitive = _mux mREAD_QAX15 (READ_QA[15], tiex_readq, xA_addr, READ_QAX[15]);
primitive = _mux mREAD_QAX16 (READ_QA[16], tiex_readq, xA_addr, READ_QAX[16]);
primitive = _mux mREAD_QAX17 (READ_QA[17], tiex_readq, xA_addr, READ_QAX[17]);
primitive = _mux mREAD_QAX18 (READ_QA[18], tiex_readq, xA_addr, READ_QAX[18]);
)
intern (DA_scan) (array = 18 : 0;
primitive = _mux mDA_scan0(READ_QAX[0], QA[1], DFTRAMBYP, DA_scan[0]);
primitive = _mux mDA_scan1(READ_QAX[1], QA[2], DFTRAMBYP, DA_scan[1]);
primitive = _mux mDA_scan2(READ_QAX[2], QA[3], DFTRAMBYP, DA_scan[2]);
primitive = _mux mDA_scan3(READ_QAX[3], QA[4], DFTRAMBYP, DA_scan[3]);
primitive = _mux mDA_scan4(READ_QAX[4], QA[5], DFTRAMBYP, DA_scan[4]);
primitive = _mux mDA_scan5(READ_QAX[5], QA[6], DFTRAMBYP, DA_scan[5]);
primitive = _mux mDA_scan6(READ_QAX[6], QA[7], DFTRAMBYP, DA_scan[6]);
primitive = _mux mDA_scan7(READ_QAX[7], QA[8], DFTRAMBYP, DA_scan[7]);
primitive = _mux mDA_scan8(READ_QAX[8], mtie_sel0, DFTRAMBYP, DA_scan[8]);
primitive = _mux mDA_scan9(READ_QAX[9], mtie_sel0, DFTRAMBYP, DA_scan[9]);
primitive = _mux mDA_scan10(READ_QAX[10], QA[9], DFTRAMBYP, DA_scan[10]);
primitive = _mux mDA_scan11(READ_QAX[11], QA[10], DFTRAMBYP, DA_scan[11]);
primitive = _mux mDA_scan12(READ_QAX[12], QA[11], DFTRAMBYP, DA_scan[12]);
primitive = _mux mDA_scan13(READ_QAX[13], QA[12], DFTRAMBYP, DA_scan[13]);
primitive = _mux mDA_scan14(READ_QAX[14], QA[13], DFTRAMBYP, DA_scan[14]);
primitive = _mux mDA_scan15(READ_QAX[15], QA[14], DFTRAMBYP, DA_scan[15]);
primitive = _mux mDA_scan16(READ_QAX[16], QA[15], DFTRAMBYP, DA_scan[16]);
primitive = _mux mDA_scan17(READ_QAX[17], QA[16], DFTRAMBYP, DA_scan[17]);
primitive = _mux mDA_scan18(READ_QAX[18], QA[17], DFTRAMBYP, DA_scan[18]);
)
output (QA) ( array = 18 : 0;
instance = rf2_32x19_wm0_scanflop uDQA0 (.CLK(CLKA), .SE(SEA), .SI(QA[1]), .D(DA_scan[0]), .Q(QA[0]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA1 (.CLK(CLKA), .SE(SEA), .SI(QA[2]), .D(DA_scan[1]), .Q(QA[1]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA2 (.CLK(CLKA), .SE(SEA), .SI(QA[3]), .D(DA_scan[2]), .Q(QA[2]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA3 (.CLK(CLKA), .SE(SEA), .SI(QA[4]), .D(DA_scan[3]), .Q(QA[3]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA4 (.CLK(CLKA), .SE(SEA), .SI(QA[5]), .D(DA_scan[4]), .Q(QA[4]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA5 (.CLK(CLKA), .SE(SEA), .SI(QA[6]), .D(DA_scan[5]), .Q(QA[5]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA6 (.CLK(CLKA), .SE(SEA), .SI(QA[7]), .D(DA_scan[6]), .Q(QA[6]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA7 (.CLK(CLKA), .SE(SEA), .SI(QA[8]), .D(DA_scan[7]), .Q(QA[7]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA8 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[0]), .D(DA_scan[8]), .Q(QA[8]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA9 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[1]), .D(DA_scan[9]), .Q(QA[9]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA10 (.CLK(CLKA), .SE(SEA), .SI(QA[9]), .D(DA_scan[10]), .Q(QA[10]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA11 (.CLK(CLKA), .SE(SEA), .SI(QA[10]), .D(DA_scan[11]), .Q(QA[11]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA12 (.CLK(CLKA), .SE(SEA), .SI(QA[11]), .D(DA_scan[12]), .Q(QA[12]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA13 (.CLK(CLKA), .SE(SEA), .SI(QA[12]), .D(DA_scan[13]), .Q(QA[13]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA14 (.CLK(CLKA), .SE(SEA), .SI(QA[13]), .D(DA_scan[14]), .Q(QA[14]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA15 (.CLK(CLKA), .SE(SEA), .SI(QA[14]), .D(DA_scan[15]), .Q(QA[15]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA16 (.CLK(CLKA), .SE(SEA), .SI(QA[15]), .D(DA_scan[16]), .Q(QA[16]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA17 (.CLK(CLKA), .SE(SEA), .SI(QA[16]), .D(DA_scan[17]), .Q(QA[17]), .Xout(XoutAiff));
instance = rf2_32x19_wm0_scanflop uDQA18 (.CLK(CLKA), .SE(SEA), .SI(QA[17]), .D(DA_scan[18]), .Q(QA[18]), .Xout(XoutAiff));
)
output (SOA) ( array = 1 : 0;
primitive = _buf bSOA0 ( QA[0], SOA[0] );
primitive = _buf bSOA1 ( QA[18], SOA[1] );
)
intern (BUS_SIB) (array = 1 : 0;
primitive = _buf wbSIB0 (SIB[0], BUS_SIB[0]);
primitive = _buf wbSIB1 (SIB[1], BUS_SIB[1]);
)
intern (BUS_AB) (array = 4 : 0;
primitive = _buf bBUS_AB0 ( AB[0], BUS_AB[0]);
primitive = _buf bBUS_AB1 ( AB[1], BUS_AB[1]);
primitive = _buf bBUS_AB2 ( AB[2], BUS_AB[2]);
primitive = _buf bBUS_AB3 ( AB[3], BUS_AB[3]);
primitive = _buf bBUS_AB4 ( AB[4], BUS_AB[4]);
)
intern (BUS_DB) (array = 18 : 0;
primitive = _buf bBUS_DB0( DB[0], BUS_DB[0] );
primitive = _buf bBUS_DB1( DB[1], BUS_DB[1] );
primitive = _buf bBUS_DB2( DB[2], BUS_DB[2] );
primitive = _buf bBUS_DB3( DB[3], BUS_DB[3] );
primitive = _buf bBUS_DB4( DB[4], BUS_DB[4] );
primitive = _buf bBUS_DB5( DB[5], BUS_DB[5] );
primitive = _buf bBUS_DB6( DB[6], BUS_DB[6] );
primitive = _buf bBUS_DB7( DB[7], BUS_DB[7] );
primitive = _buf bBUS_DB8( DB[8], BUS_DB[8] );
primitive = _buf bBUS_DB9( DB[9], BUS_DB[9] );
primitive = _buf bBUS_DB10( DB[10], BUS_DB[10] );
primitive = _buf bBUS_DB11( DB[11], BUS_DB[11] );
primitive = _buf bBUS_DB12( DB[12], BUS_DB[12] );
primitive = _buf bBUS_DB13( DB[13], BUS_DB[13] );
primitive = _buf bBUS_DB14( DB[14], BUS_DB[14] );
primitive = _buf bBUS_DB15( DB[15], BUS_DB[15] );
primitive = _buf bBUS_DB16( DB[16], BUS_DB[16] );
primitive = _buf bBUS_DB17( DB[17], BUS_DB[17] );
primitive = _buf bBUS_DB18( DB[18], BUS_DB[18] );
)
intern (BMUX_AB) ( array = 4 : 0;
primitive = _mux maB0(TAB[0], BUS_AB[0], TENB, BMUX_AB[0]);
primitive = _mux maB1(TAB[1], BUS_AB[1], TENB, BMUX_AB[1]);
primitive = _mux maB2(TAB[2], BUS_AB[2], TENB, BMUX_AB[2]);
primitive = _mux maB3(TAB[3], BUS_AB[3], TENB, BMUX_AB[3]);
primitive = _mux maB4(TAB[4], BUS_AB[4], TENB, BMUX_AB[4]);
)
intern (BMUXSEL_AB) ( array = 4 : 0;
primitive = _mux mBMUXSEL_AB0(mlc_bmuxsel, BMUX_AB[0], DFTRAMBYP, BMUXSEL_AB[0]);
primitive = _mux mBMUXSEL_AB1(mlc_bmuxsel, BMUX_AB[1], DFTRAMBYP, BMUXSEL_AB[1]);
primitive = _mux mBMUXSEL_AB2(mlc_bmuxsel, BMUX_AB[2], DFTRAMBYP, BMUXSEL_AB[2]);
primitive = _mux mBMUXSEL_AB3(mlc_bmuxsel, BMUX_AB[3], DFTRAMBYP, BMUXSEL_AB[3]);
primitive = _mux mBMUXSEL_AB4(mlc_bmuxsel, BMUX_AB[4], DFTRAMBYP, BMUXSEL_AB[4]);
)
output (AYB) ( array = 4 : 0;
primitive = _buf bAYB0(BMUXSEL_AB[0], AYB[0]);
primitive = _buf bAYB1(BMUXSEL_AB[1], AYB[1]);
primitive = _buf bAYB2(BMUXSEL_AB[2], AYB[2]);
primitive = _buf bAYB3(BMUXSEL_AB[3], AYB[3]);
primitive = _buf bAYB4(BMUXSEL_AB[4], AYB[4]);
)
intern (BMUX_DB) ( array = 18 : 0;
primitive = _mux mBMUX_DB0(TDB[0], BUS_DB[0], TENB, BMUX_DB[0]);
primitive = _mux mBMUX_DB1(TDB[1], BUS_DB[1], TENB, BMUX_DB[1]);
primitive = _mux mBMUX_DB2(TDB[2], BUS_DB[2], TENB, BMUX_DB[2]);
primitive = _mux mBMUX_DB3(TDB[3], BUS_DB[3], TENB, BMUX_DB[3]);
primitive = _mux mBMUX_DB4(TDB[4], BUS_DB[4], TENB, BMUX_DB[4]);
primitive = _mux mBMUX_DB5(TDB[5], BUS_DB[5], TENB, BMUX_DB[5]);
primitive = _mux mBMUX_DB6(TDB[6], BUS_DB[6], TENB, BMUX_DB[6]);
primitive = _mux mBMUX_DB7(TDB[7], BUS_DB[7], TENB, BMUX_DB[7]);
primitive = _mux mBMUX_DB8(TDB[8], BUS_DB[8], TENB, BMUX_DB[8]);
primitive = _mux mBMUX_DB9(TDB[9], BUS_DB[9], TENB, BMUX_DB[9]);
primitive = _mux mBMUX_DB10(TDB[10], BUS_DB[10], TENB, BMUX_DB[10]);
primitive = _mux mBMUX_DB11(TDB[11], BUS_DB[11], TENB, BMUX_DB[11]);
primitive = _mux mBMUX_DB12(TDB[12], BUS_DB[12], TENB, BMUX_DB[12]);
primitive = _mux mBMUX_DB13(TDB[13], BUS_DB[13], TENB, BMUX_DB[13]);
primitive = _mux mBMUX_DB14(TDB[14], BUS_DB[14], TENB, BMUX_DB[14]);
primitive = _mux mBMUX_DB15(TDB[15], BUS_DB[15], TENB, BMUX_DB[15]);
primitive = _mux mBMUX_DB16(TDB[16], BUS_DB[16], TENB, BMUX_DB[16]);
primitive = _mux mBMUX_DB17(TDB[17], BUS_DB[17], TENB, BMUX_DB[17]);
primitive = _mux mBMUX_DB18(TDB[18], BUS_DB[18], TENB, BMUX_DB[18]);
)
intern (BMUX_CENB) (primitive = _mux mBMUX_CENB(TCENB, CENB, TENB, BMUX_CENB);)
intern (BMUXSEL_CENB) (primitive = _mux mBMUXSEL_CENB(mlc_bmuxsel, BMUX_CENB, DFTRAMBYP, BMUXSEL_CENB);)
output (CENYB) (primitive = _buf bCENYB(BMUXSEL_CENB, CENYB);)
intern (BMUX_AB_n) (array = 4 : 1;
primitive = _inv iBMUX_AB_n1 ( BMUX_AB[1], BMUX_AB_n[1] );
primitive = _inv iBMUX_AB_n2 ( BMUX_AB[2], BMUX_AB_n[2] );
primitive = _inv iBMUX_AB_n3 ( BMUX_AB[3], BMUX_AB_n[3] );
primitive = _inv iBMUX_AB_n4 ( BMUX_AB[4], BMUX_AB_n[4] );
)
intern (B_max) (array = 4 : 0;
primitive = _tie1 bB_max0 ( B_max[0] );
primitive = _tie1 bB_max1 ( B_max[1] );
primitive = _tie1 bB_max2 ( B_max[2] );
primitive = _tie1 bB_max3 ( B_max[3] );
primitive = _tie1 bB_max4 ( B_max[4] );
)
intern (B_max_n) (array = 4 : 0;
primitive = _inv bB_max_n0( B_max[0], B_max_n[0] );
primitive = _inv bB_max_n1( B_max[1], B_max_n[1] );
primitive = _inv bB_max_n2( B_max[2], B_max_n[2] );
primitive = _inv bB_max_n3( B_max[3], B_max_n[3] );
primitive = _inv bB_max_n4( B_max[4], B_max_n[4] );
)
intern (AB_m) (array = 4 : 0;
primitive = _and aAB_m0(BMUX_AB[0], B_max_n[0], AB_m[0] );
primitive = _and aAB_m1(BMUX_AB[1], B_max_n[1], AB_m[1] );
primitive = _and aAB_m2(BMUX_AB[2], B_max_n[2], AB_m[2] );
primitive = _and aAB_m3(BMUX_AB[3], B_max_n[3], AB_m[3] );
primitive = _and aAB_m4(BMUX_AB[4], B_max_n[4], AB_m[4] );
)
intern (m_AB) (array = 4 : 1;
primitive = _and am_AB1(BMUX_AB_n[1], B_max[1], m_AB[1] );
primitive = _and am_AB2(BMUX_AB_n[2], B_max[2], m_AB[2] );
primitive = _and am_AB3(BMUX_AB_n[3], B_max[3], m_AB[3] );
primitive = _and am_AB4(BMUX_AB_n[4], B_max[4], m_AB[4] );
)
intern (EQ_B) (array = 4 : 1;
primitive = _nor nEQ_B1(m_AB[1], AB_m[1], EQ_B[1] );
primitive = _nor nEQ_B2(m_AB[2], AB_m[2], EQ_B[2] );
primitive = _nor nEQ_B3(m_AB[3], AB_m[3], EQ_B[3] );
primitive = _nor nEQ_B4(m_AB[4], AB_m[4], EQ_B[4] );
)
intern (XoutBi) (array = 3 : 0;
primitive = _and aXoutBi0(AB_m[0], EQ_B[4], EQ_B[3], EQ_B[2], EQ_B[1], XoutBi[0]);
primitive = _and aXoutBi1(AB_m[1], EQ_B[4], EQ_B[3], EQ_B[2], XoutBi[1]);
primitive = _and aXoutBi2(AB_m[2], EQ_B[4], EQ_B[3], XoutBi[2]);
primitive = _and aXoutBi3(AB_m[3], EQ_B[4], XoutBi[3]);
)
intern (XoutBifTemp) (primitive = _or oXoutBifTemp (AB_m[4], XoutBi[0], XoutBi[1], XoutBi[2], XoutBi[3], XoutBifTemp);)
intern (XoutBif) (primitive = _and oXoutBif (XoutBifTemp, NOT_CENB, XoutBif);)
intern (nscanshiftB) (
primitive = _nor nnscanshiftB (DFTRAMBYP, SEB, nscanshiftB);)
intern (XoutaddrB) (
primitive = _and aXoutaddrB (nscanshiftB, XoutBif, XoutaddrB);)
intern (XoutBiff) (
primitive = _or oXoutBiff (XoutaddrB, XoutB, XoutBiff);)
intern (NOT_CENB) (primitive = _inv iNOT_CENB(BMUX_CENB, NOT_CENB);)
intern (WRITEB) (array = 18 : 0;
primitive = _and aWRITEB0(NOT_DFTRAMBYP, NOT_CENB, WRITEB[0]);
primitive = _and aWRITEB1(NOT_DFTRAMBYP, NOT_CENB, WRITEB[1]);
primitive = _and aWRITEB2(NOT_DFTRAMBYP, NOT_CENB, WRITEB[2]);
primitive = _and aWRITEB3(NOT_DFTRAMBYP, NOT_CENB, WRITEB[3]);
primitive = _and aWRITEB4(NOT_DFTRAMBYP, NOT_CENB, WRITEB[4]);
primitive = _and aWRITEB5(NOT_DFTRAMBYP, NOT_CENB, WRITEB[5]);
primitive = _and aWRITEB6(NOT_DFTRAMBYP, NOT_CENB, WRITEB[6]);
primitive = _and aWRITEB7(NOT_DFTRAMBYP, NOT_CENB, WRITEB[7]);
primitive = _and aWRITEB8(NOT_DFTRAMBYP, NOT_CENB, WRITEB[8]);
primitive = _and aWRITEB9(NOT_DFTRAMBYP, NOT_CENB, WRITEB[9]);
primitive = _and aWRITEB10(NOT_DFTRAMBYP, NOT_CENB, WRITEB[10]);
primitive = _and aWRITEB11(NOT_DFTRAMBYP, NOT_CENB, WRITEB[11]);
primitive = _and aWRITEB12(NOT_DFTRAMBYP, NOT_CENB, WRITEB[12]);
primitive = _and aWRITEB13(NOT_DFTRAMBYP, NOT_CENB, WRITEB[13]);
primitive = _and aWRITEB14(NOT_DFTRAMBYP, NOT_CENB, WRITEB[14]);
primitive = _and aWRITEB15(NOT_DFTRAMBYP, NOT_CENB, WRITEB[15]);
primitive = _and aWRITEB16(NOT_DFTRAMBYP, NOT_CENB, WRITEB[16]);
primitive = _and aWRITEB17(NOT_DFTRAMBYP, NOT_CENB, WRITEB[17]);
primitive = _and aWRITEB18(NOT_DFTRAMBYP, NOT_CENB, WRITEB[18]);
)
intern (INT_QA) (array = 18 : 0;
instance = rf2_32x19_wm0_bitcell memB0 (.CLK(CLKB), .WRITE(WRITEB[0]), .READ(READA[0]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[0]), .Xout(XoutBiff), .Q(INT_QA[0]));
instance = rf2_32x19_wm0_bitcell memB1 (.CLK(CLKB), .WRITE(WRITEB[1]), .READ(READA[1]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[1]), .Xout(XoutBiff), .Q(INT_QA[1]));
instance = rf2_32x19_wm0_bitcell memB2 (.CLK(CLKB), .WRITE(WRITEB[2]), .READ(READA[2]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[2]), .Xout(XoutBiff), .Q(INT_QA[2]));
instance = rf2_32x19_wm0_bitcell memB3 (.CLK(CLKB), .WRITE(WRITEB[3]), .READ(READA[3]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[3]), .Xout(XoutBiff), .Q(INT_QA[3]));
instance = rf2_32x19_wm0_bitcell memB4 (.CLK(CLKB), .WRITE(WRITEB[4]), .READ(READA[4]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[4]), .Xout(XoutBiff), .Q(INT_QA[4]));
instance = rf2_32x19_wm0_bitcell memB5 (.CLK(CLKB), .WRITE(WRITEB[5]), .READ(READA[5]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[5]), .Xout(XoutBiff), .Q(INT_QA[5]));
instance = rf2_32x19_wm0_bitcell memB6 (.CLK(CLKB), .WRITE(WRITEB[6]), .READ(READA[6]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[6]), .Xout(XoutBiff), .Q(INT_QA[6]));
instance = rf2_32x19_wm0_bitcell memB7 (.CLK(CLKB), .WRITE(WRITEB[7]), .READ(READA[7]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[7]), .Xout(XoutBiff), .Q(INT_QA[7]));
instance = rf2_32x19_wm0_bitcell memB8 (.CLK(CLKB), .WRITE(WRITEB[8]), .READ(READA[8]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[8]), .Xout(XoutBiff), .Q(INT_QA[8]));
instance = rf2_32x19_wm0_bitcell memB9 (.CLK(CLKB), .WRITE(WRITEB[9]), .READ(READA[9]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[9]), .Xout(XoutBiff), .Q(INT_QA[9]));
instance = rf2_32x19_wm0_bitcell memB10 (.CLK(CLKB), .WRITE(WRITEB[10]), .READ(READA[10]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[10]), .Xout(XoutBiff), .Q(INT_QA[10]));
instance = rf2_32x19_wm0_bitcell memB11 (.CLK(CLKB), .WRITE(WRITEB[11]), .READ(READA[11]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[11]), .Xout(XoutBiff), .Q(INT_QA[11]));
instance = rf2_32x19_wm0_bitcell memB12 (.CLK(CLKB), .WRITE(WRITEB[12]), .READ(READA[12]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[12]), .Xout(XoutBiff), .Q(INT_QA[12]));
instance = rf2_32x19_wm0_bitcell memB13 (.CLK(CLKB), .WRITE(WRITEB[13]), .READ(READA[13]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[13]), .Xout(XoutBiff), .Q(INT_QA[13]));
instance = rf2_32x19_wm0_bitcell memB14 (.CLK(CLKB), .WRITE(WRITEB[14]), .READ(READA[14]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[14]), .Xout(XoutBiff), .Q(INT_QA[14]));
instance = rf2_32x19_wm0_bitcell memB15 (.CLK(CLKB), .WRITE(WRITEB[15]), .READ(READA[15]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[15]), .Xout(XoutBiff), .Q(INT_QA[15]));
instance = rf2_32x19_wm0_bitcell memB16 (.CLK(CLKB), .WRITE(WRITEB[16]), .READ(READA[16]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[16]), .Xout(XoutBiff), .Q(INT_QA[16]));
instance = rf2_32x19_wm0_bitcell memB17 (.CLK(CLKB), .WRITE(WRITEB[17]), .READ(READA[17]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[17]), .Xout(XoutBiff), .Q(INT_QA[17]));
instance = rf2_32x19_wm0_bitcell memB18 (.CLK(CLKB), .WRITE(WRITEB[18]), .READ(READA[18]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[18]), .Xout(XoutBiff), .Q(INT_QA[18]));
)
intern (x_detection_CENB) (primitive = _xor xx_detection_CENB(BMUX_CENB, BMUX_CENB, x_detection_CENB);)
intern (x_detection_CLKB) (primitive = _xor xx_detection_CLKB(CLKB, CLKB, x_detection_CLKB);)
intern (aSEB) (primitive = _and a1SEB ( SEB, DFTRAMBYPinv, aSEB );)
intern (acendftB) (primitive = _and a1cendft[B] (x_detection_CENB, DFTRAMBYPinv, acendftB );)
intern (acendftCB) (primitive = _and a1cendftCB ( x_detection_CLKB, DFTRAMBYPinv, acendftCB );)
intern (XoutB) (primitive = _or oXoutB ( aSEB, acendftB, acendftCA, acendftCB, XoutB );)
intern (DFTRAMBYPinv) (primitive = _inv imDFTRAMBYP ( DFTRAMBYP, DFTRAMBYPinv );)
intern (DB_hold) (array = 18:0;
primitive = _mux mDB_hold0 (BMUX_DB[0], QB_int[0], BMUX_CENB, DB_hold[0] );
primitive = _mux mDB_hold1 (BMUX_DB[1], QB_int[1], BMUX_CENB, DB_hold[1] );
primitive = _mux mDB_hold2 (BMUX_DB[2], QB_int[2], BMUX_CENB, DB_hold[2] );
primitive = _mux mDB_hold3 (BMUX_DB[3], QB_int[3], BMUX_CENB, DB_hold[3] );
primitive = _mux mDB_hold4 (BMUX_DB[4], QB_int[4], BMUX_CENB, DB_hold[4] );
primitive = _mux mDB_hold5 (BMUX_DB[5], QB_int[5], BMUX_CENB, DB_hold[5] );
primitive = _mux mDB_hold6 (BMUX_DB[6], QB_int[6], BMUX_CENB, DB_hold[6] );
primitive = _mux mDB_hold7 (BMUX_DB[7], QB_int[7], BMUX_CENB, DB_hold[7] );
primitive = _mux mDB_hold8 (BMUX_DB[8], QB_int[8], BMUX_CENB, DB_hold[8] );
primitive = _mux mDB_hold9 (BMUX_DB[9], QB_int[9], BMUX_CENB, DB_hold[9] );
primitive = _mux mDB_hold10 (BMUX_DB[10], QB_int[10], BMUX_CENB, DB_hold[10] );
primitive = _mux mDB_hold11 (BMUX_DB[11], QB_int[11], BMUX_CENB, DB_hold[11] );
primitive = _mux mDB_hold12 (BMUX_DB[12], QB_int[12], BMUX_CENB, DB_hold[12] );
primitive = _mux mDB_hold13 (BMUX_DB[13], QB_int[13], BMUX_CENB, DB_hold[13] );
primitive = _mux mDB_hold14 (BMUX_DB[14], QB_int[14], BMUX_CENB, DB_hold[14] );
primitive = _mux mDB_hold15 (BMUX_DB[15], QB_int[15], BMUX_CENB, DB_hold[15] );
primitive = _mux mDB_hold16 (BMUX_DB[16], QB_int[16], BMUX_CENB, DB_hold[16] );
primitive = _mux mDB_hold17 (BMUX_DB[17], QB_int[17], BMUX_CENB, DB_hold[17] );
primitive = _mux mDB_hold18 (BMUX_DB[18], QB_int[18], BMUX_CENB, DB_hold[18] );
)
intern (DB_scan) (array = 18:0;
primitive = _mux mDB_scan0 (DB_hold[0], BMUX_DB[0], DFTRAMBYP, DB_scan[0] );
primitive = _mux mDB_scan1 (DB_hold[1], BMUX_DB[1], DFTRAMBYP, DB_scan[1] );
primitive = _mux mDB_scan2 (DB_hold[2], BMUX_DB[2], DFTRAMBYP, DB_scan[2] );
primitive = _mux mDB_scan3 (DB_hold[3], BMUX_DB[3], DFTRAMBYP, DB_scan[3] );
primitive = _mux mDB_scan4 (DB_hold[4], BMUX_DB[4], DFTRAMBYP, DB_scan[4] );
primitive = _mux mDB_scan5 (DB_hold[5], BMUX_DB[5], DFTRAMBYP, DB_scan[5] );
primitive = _mux mDB_scan6 (DB_hold[6], BMUX_DB[6], DFTRAMBYP, DB_scan[6] );
primitive = _mux mDB_scan7 (DB_hold[7], BMUX_DB[7], DFTRAMBYP, DB_scan[7] );
primitive = _mux mDB_scan8 (DB_hold[8], BMUX_DB[8], DFTRAMBYP, DB_scan[8] );
primitive = _mux mDB_scan9 (DB_hold[9], BMUX_DB[9], DFTRAMBYP, DB_scan[9] );
primitive = _mux mDB_scan10 (DB_hold[10], BMUX_DB[10], DFTRAMBYP, DB_scan[10] );
primitive = _mux mDB_scan11 (DB_hold[11], BMUX_DB[11], DFTRAMBYP, DB_scan[11] );
primitive = _mux mDB_scan12 (DB_hold[12], BMUX_DB[12], DFTRAMBYP, DB_scan[12] );
primitive = _mux mDB_scan13 (DB_hold[13], BMUX_DB[13], DFTRAMBYP, DB_scan[13] );
primitive = _mux mDB_scan14 (DB_hold[14], BMUX_DB[14], DFTRAMBYP, DB_scan[14] );
primitive = _mux mDB_scan15 (DB_hold[15], BMUX_DB[15], DFTRAMBYP, DB_scan[15] );
primitive = _mux mDB_scan16 (DB_hold[16], BMUX_DB[16], DFTRAMBYP, DB_scan[16] );
primitive = _mux mDB_scan17 (DB_hold[17], BMUX_DB[17], DFTRAMBYP, DB_scan[17] );
primitive = _mux mDB_scan18 (DB_hold[18], BMUX_DB[18], DFTRAMBYP, DB_scan[18] );
)
intern (QB_int) (array = 18 : 0;
instance = rf2_32x19_wm0_scanflop uDQB0 (.CLK(CLKB), .SE(SEB), .SI(QB_int[1]), .D(DB_scan[0]), .Q(QB_int[0]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB1 (.CLK(CLKB), .SE(SEB), .SI(QB_int[2]), .D(DB_scan[1]), .Q(QB_int[1]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB2 (.CLK(CLKB), .SE(SEB), .SI(QB_int[3]), .D(DB_scan[2]), .Q(QB_int[2]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB3 (.CLK(CLKB), .SE(SEB), .SI(QB_int[4]), .D(DB_scan[3]), .Q(QB_int[3]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB4 (.CLK(CLKB), .SE(SEB), .SI(QB_int[5]), .D(DB_scan[4]), .Q(QB_int[4]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB5 (.CLK(CLKB), .SE(SEB), .SI(QB_int[6]), .D(DB_scan[5]), .Q(QB_int[5]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB6 (.CLK(CLKB), .SE(SEB), .SI(QB_int[7]), .D(DB_scan[6]), .Q(QB_int[6]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB7 (.CLK(CLKB), .SE(SEB), .SI(QB_int[8]), .D(DB_scan[7]), .Q(QB_int[7]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB8 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[0]), .D(DB_scan[8]), .Q(QB_int[8]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB9 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[1]), .D(DB_scan[9]), .Q(QB_int[9]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB10 (.CLK(CLKB), .SE(SEB), .SI(QB_int[9]), .D(DB_scan[10]), .Q(QB_int[10]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB11 (.CLK(CLKB), .SE(SEB), .SI(QB_int[10]), .D(DB_scan[11]), .Q(QB_int[11]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB12 (.CLK(CLKB), .SE(SEB), .SI(QB_int[11]), .D(DB_scan[12]), .Q(QB_int[12]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB13 (.CLK(CLKB), .SE(SEB), .SI(QB_int[12]), .D(DB_scan[13]), .Q(QB_int[13]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB14 (.CLK(CLKB), .SE(SEB), .SI(QB_int[13]), .D(DB_scan[14]), .Q(QB_int[14]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB15 (.CLK(CLKB), .SE(SEB), .SI(QB_int[14]), .D(DB_scan[15]), .Q(QB_int[15]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB16 (.CLK(CLKB), .SE(SEB), .SI(QB_int[15]), .D(DB_scan[16]), .Q(QB_int[16]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB17 (.CLK(CLKB), .SE(SEB), .SI(QB_int[16]), .D(DB_scan[17]), .Q(QB_int[17]), .Xout(XoutBiff));
instance = rf2_32x19_wm0_scanflop uDQB18 (.CLK(CLKB), .SE(SEB), .SI(QB_int[17]), .D(DB_scan[18]), .Q(QB_int[18]), .Xout(XoutBiff));
)
output (SOB) ( array = 1 : 0;
primitive = _buf bSOB0 (QB_int[0], SOB[0] );
primitive = _buf bSOB1 (QB_int[18], SOB[1] );
)
)

238
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.memlib Normal file
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/* logicvision_memcomp Version: c0.1.2-beta */
/* common_memcomp Version: c0.1.0-EAC */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// logicvision model for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x19_wm0
// Words: 32
// Bits: 19
// Mux: 2
// Drive: 6
// Write Mask: Off
// Extra Margin Adjustment: On
// Redundant Rows: 0
// Redundant Columns: 2
// Test Muxes On
//
// Creation Date: Mon Nov 11 12:00:43 2019
// Version: r4p0
//
// Modeling Assumptions:
//
// Modeling Limitations: None
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
MemoryTemplate (rf2_32x19_wm0) {
Algorithm : SmarchChkbvcd;
DataOutStage : None;
LogicalPorts : 1R1W;
BitGrouping : 1;
MemoryType : SRAM;
MinHold : 0.5;
OperationSet : SyncWRvcd;
SelectDuringWriteThru : Off;
ShadowRead : On;
ShadowWrite : On;
TransparentMode : None;
ObservationLogic: On;
InternalScanLogic: On;
CellName : rf2_32x19_wm0;
NumberOfWords : 32;
AddressCounter{
Function (Address) {
LogicalAddressMap{
ColumnAddress[0] : Address[0];
RowAddress[3:0] : Address[4:1];
}
}
Function (ColumnAddress) {
CountRange [0:1];
}
Function (RowAddress) {
CountRange [0:15];
}
}
PhysicalAddressMap{
ColumnAddress[0] : c[0];
RowAddress[0] : r[0];
RowAddress[1] : r[1];
RowAddress[2] : r[2];
RowAddress[3] : r[3];
}
PhysicalDataMap{
Data[0] : NOT d[0];
Data[1] : NOT d[1];
Data[2] : NOT d[2];
Data[3] : NOT d[3];
Data[4] : NOT d[4];
Data[5] : NOT d[5];
Data[6] : NOT d[6];
Data[7] : NOT d[7];
Data[8] : NOT d[8];
Data[9] : d[9];
Data[10] : d[10];
Data[11] : d[11];
Data[12] : d[12];
Data[13] : d[13];
Data[14] : d[14];
Data[15] : d[15];
Data[16] : d[16];
Data[17] : d[17];
Data[18] : d[18];
}
Port (AA[4:0]) {
Function : Address;
LogicalPort : A;
EmbeddedTestLogic {
TestInput : TAA[4:0];
TestOutput : AYA[4:0];
}
}
Port (QA[18:0]) {
Function : Data;
Direction : output;
LogicalPort : A;
}
Port (CENA) {
Function : ReadEnable;
LogicalPort : A;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TCENA;
TestOutput : CENYA;
}
}
Port (TENA) {
Function : BISTOn;
Direction : Input;
LogicalPort : A;
Polarity : ActiveLow;
}
Port (CLKA) {
Function : Clock;
LogicalPort : A;
Polarity : ActiveHigh;
}
Port (EMAA[2:0]) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : A;
Polarity : ActiveHigh;
}
Port (EMASA) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : A;
Polarity : ActiveHigh;
}
port (SEA){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SIA[1:0]){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SOA[1:0]){
Function : None;
Direction : Output;
}
port (DFTRAMBYP){
Function : ScanTest;
Direction : Input;
Polarity : ActiveHigh;
}
Port (AB[4:0]) {
Function : Address;
LogicalPort : B;
EmbeddedTestLogic {
TestInput : TAB[4:0];
TestOutput : AYB[4:0];
}
}
Port (DB[18:0]) {
Function : Data;
Direction : input;
LogicalPort : B;
EmbeddedTestLogic {
TestInput : TDB[18:0];
}
}
Port (CENB) {
Function : WriteEnable;
LogicalPort : B;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TCENB;
TestOutput : CENYB;
}
}
Port (TENB) {
Function : BISTOn;
Direction : Input;
LogicalPort : B;
Polarity : ActiveLow;
}
Port (CLKB) {
Function : Clock;
LogicalPort : B;
Polarity : ActiveHigh;
}
Port (EMAB[2:0]) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : B;
Polarity : ActiveHigh;
}
Port (COLLDISN) {
Function : None;
SafeValue : 1;
Direction : Input;
Polarity : ActiveLow;
}
port (SEB){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SIB[1:0]){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SOB[1:0]){
Function : None;
Direction : Output;
}
port (RET1N){
Function : None;
Direction : Input;
SafeValue : 1;
Polarity : Activelow;
}
}

562
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.tv Normal file
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/* tetramax_memcomp Version: 4.0.5-EAC3 */
/* common_memcomp Version: 4.0.5.2-amci */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// Tetramax model for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x19_wm0
// Words: 32
// Bits: 19
// Mux: 2
// Drive: 6
// Write Mask: Off
// Write Thru: Off
// Extra Margin Adjustment: On
// Redundant Columns: 2
// Test Muxes On
// Power Gating: Off
// Retention: On
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Mon Nov 11 12:01:06 2019
// Version: r4p0
//
// Verified
//
// Modeling Assumptions:
// This model is for use by only TetraMax ATPG tool.
// It is not intended to be used by any Verilog Simulator.
//
// Modeling Limitations: These models have limited functionality as
// defined by the TetraMax modelling guidelines. These models are
// developed on Verilog syntax but they don't fully represent the
// functionality of the memory model as they are restricted by
// the ATPG tool. We have used fast sequential ATPG engine for verification
// of all the memories on recommendation from Synopsys Tetramax expert.
// The models have been tested by generating the ATPG vectors and simulating them
// as well as running functional vectors through tetramax logical simulation engine.
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
`timescale 1ns/1ps
`define read_write readx
`celldefine
module rf2_32x19_wm0_scanflop (Q, SI, D, SE, CLK, Xout);
output Q;
input SI, D, SE, CLK, Xout;
_MUX m1 (SE, D, SI, n1);
_MUX m2 (Xout, n1, 1'bX, n2);
_DFF r1 (1'b0, 1'b0, CLK, n2, Q);
endmodule
`endcelldefine
`celldefine
module rf2_32x19_wm0_bitcell (CLK, WRITE, WA, RA, D, Xout, Q);
input CLK, WRITE, D, Xout;
input [4:0] WA, RA;
output Q;
reg Q;
reg mem [31:0];
wire WRITE_ram, D_ram;
wire [4:0] WA_ram;
_MUX WRITE_MUX (Xout, WRITE, 1'bX, WRITE_ram);
_MUX D_mux (Xout, D, 1'bX, D_ram);
_MUX A0_mux (Xout, WA[0], 1'bX, WA_ram[0]);
_MUX A1_mux (Xout, WA[1], 1'bX, WA_ram[1]);
_MUX A2_mux (Xout, WA[2], 1'bX, WA_ram[2]);
_MUX A3_mux (Xout, WA[3], 1'bX, WA_ram[3]);
_MUX A4_mux (Xout, WA[4], 1'bX, WA_ram[4]);
event WRITE_OP;
always @ (posedge CLK) if(WRITE_ram) begin
mem[WA_ram]=D_ram;
#0; -> WRITE_OP;
end
wire TIE1;
assign TIE1 = 1'b1;
always @ (TIE1 or RA or WRITE_OP) if(TIE1) Q=mem[RA];
endmodule
`endcelldefine
`suppress_faults
`enable_portfaults
`ifdef POWER_PINS
module rf2_32x19_wm0 (VDDCE, VDDPE, VSSE, CENYA, AYA, CENYB, AYB, QA, SOA, SOB, CLKA,
CENA, AA, CLKB, CENB, AB, DB, EMAA, EMASA, EMAB, TENA, TCENA, TAA, TENB, TCENB,
TAB, TDB, RET1N, SIA, SEA, DFTRAMBYP, SIB, SEB, COLLDISN);
`else
module rf2_32x19_wm0 (CENYA, AYA, CENYB, AYB, QA, SOA, SOB, CLKA, CENA, AA, CLKB, CENB,
AB, DB, EMAA, EMASA, EMAB, TENA, TCENA, TAA, TENB, TCENB, TAB, TDB, RET1N, SIA,
SEA, DFTRAMBYP, SIB, SEB, COLLDISN);
`endif
output CENYA;
output [4:0] AYA;
output CENYB;
output [4:0] AYB;
output [18:0] QA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [4:0] AA;
input CLKB;
input CENB;
input [4:0] AB;
input [18:0] DB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [4:0] TAA;
input TENB;
input TCENB;
input [4:0] TAB;
input [18:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
`ifdef POWER_PINS
inout VDDCE;
inout VDDPE;
inout VSSE;
`endif
wire [1:0] BUS_SIA;
assign BUS_SIA[0] = SIA[0];
assign BUS_SIA[1] = SIA[1];
wire [4:0] BUS_AA;
assign BUS_AA = AA;
wire [4:0] BMUX_AA;
wire [4:0] BMUXSEL_AA;
wire BMUX_CENA;
wire BMUXSEL_CENA;
wire [18:0] INT_QA;
wire [18:0] READ_QA;
_MUX maA0 (TENA, TAA[0], BUS_AA[0], BMUX_AA[0]);
_MUX maselA0 (DFTRAMBYP, 1'b0, BMUX_AA[0], BMUXSEL_AA[0]);
buf bufmaA0(AYA[0],BMUXSEL_AA[0]);
_MUX maA1 (TENA, TAA[1], BUS_AA[1], BMUX_AA[1]);
_MUX maselA1 (DFTRAMBYP, 1'b0, BMUX_AA[1], BMUXSEL_AA[1]);
buf bufmaA1(AYA[1],BMUXSEL_AA[1]);
_MUX maA2 (TENA, TAA[2], BUS_AA[2], BMUX_AA[2]);
_MUX maselA2 (DFTRAMBYP, 1'b0, BMUX_AA[2], BMUXSEL_AA[2]);
buf bufmaA2(AYA[2],BMUXSEL_AA[2]);
_MUX maA3 (TENA, TAA[3], BUS_AA[3], BMUX_AA[3]);
_MUX maselA3 (DFTRAMBYP, 1'b0, BMUX_AA[3], BMUXSEL_AA[3]);
buf bufmaA3(AYA[3],BMUXSEL_AA[3]);
_MUX maA4 (TENA, TAA[4], BUS_AA[4], BMUX_AA[4]);
_MUX maselA4 (DFTRAMBYP, 1'b0, BMUX_AA[4], BMUXSEL_AA[4]);
buf bufmaA4(AYA[4],BMUXSEL_AA[4]);
_MUX mcenA (TENA, TCENA, CENA, BMUX_CENA);
_MUX mcenselA (DFTRAMBYP, 1'b0,BMUX_CENA, BMUXSEL_CENA);
buf bufmcenA (CENYA, BMUXSEL_CENA);
wire [4:0] A_max, A_max_n, AA_m;
wire XoutAif, XoutAiff;
wire [4:1] BMUX_AA_n, EQ_A, m_AA;
wire [3:0] XoutAi;
not BMUX_AA1_n (BMUX_AA_n[1], BMUX_AA[1]);
not BMUX_AA2_n (BMUX_AA_n[2], BMUX_AA[2]);
not BMUX_AA3_n (BMUX_AA_n[3], BMUX_AA[3]);
not BMUX_AA4_n (BMUX_AA_n[4], BMUX_AA[4]);
assign A_max[0] = 1;
assign A_max[1] = 1;
assign A_max[2] = 1;
assign A_max[3] = 1;
assign A_max[4] = 1;
not Amax0_n (A_max_n[0], A_max[0]);
not Amax1_n (A_max_n[1], A_max[1]);
not Amax2_n (A_max_n[2], A_max[2]);
not Amax3_n (A_max_n[3], A_max[3]);
not Amax4_n (A_max_n[4], A_max[4]);
and andBMUXAAAmax0 (AA_m[0], BMUX_AA[0], A_max_n[0]);
and andBMUXAAAmax1 (AA_m[1], BMUX_AA[1], A_max_n[1]);
and andBMUXAAAmax2 (AA_m[2], BMUX_AA[2], A_max_n[2]);
and andBMUXAAAmax3 (AA_m[3], BMUX_AA[3], A_max_n[3]);
and andBMUXAAAmax4 (AA_m[4], BMUX_AA[4], A_max_n[4]);
and andBMUXAAAmax1_n (m_AA[1], BMUX_AA_n[1], A_max[1]);
and andBMUXAAAmax2_n (m_AA[2], BMUX_AA_n[2], A_max[2]);
and andBMUXAAAmax3_n (m_AA[3], BMUX_AA_n[3], A_max[3]);
and andBMUXAAAmax4_n (m_AA[4], BMUX_AA_n[4], A_max[4]);
nor norAAAmax1 (EQ_A[1], m_AA[1], AA_m[1]);
nor norAAAmax2 (EQ_A[2], m_AA[2], AA_m[2]);
nor norAAAmax3 (EQ_A[3], m_AA[3], AA_m[3]);
nor norAAAmax4 (EQ_A[4], m_AA[4], AA_m[4]);
and XfAAAmax0 (XoutAi[0], AA_m[0], EQ_A[4], EQ_A[3], EQ_A[2], EQ_A[1]);
and XfAAAmax1 (XoutAi[1], AA_m[1], EQ_A[4], EQ_A[3], EQ_A[2]);
and XfAAAmax2 (XoutAi[2], AA_m[2], EQ_A[4], EQ_A[3]);
and XfAAAmax3 (XoutAi[3], AA_m[3], EQ_A[4]);
or orXfAAAmax4 (XoutAif, AA_m[4], XoutAi[0], XoutAi[1], XoutAi[2], XoutAi[3]);
wire [4:0] xDetectionAddrBusA;
xor addrHandleA0 (xDetectionAddrBusA[0], BMUX_AA[0], BMUX_AA[0]);
xor addrHandleA1 (xDetectionAddrBusA[1], BMUX_AA[1], BMUX_AA[1]);
xor addrHandleA2 (xDetectionAddrBusA[2], BMUX_AA[2], BMUX_AA[2]);
xor addrHandleA3 (xDetectionAddrBusA[3], BMUX_AA[3], BMUX_AA[3]);
xor addrHandleA4 (xDetectionAddrBusA[4], BMUX_AA[4], BMUX_AA[4]);
or addrFinalA (xAddrA,xDetectionAddrBusA[0],xDetectionAddrBusA[1],xDetectionAddrBusA[2],xDetectionAddrBusA[3],xDetectionAddrBusA[4]);
or xBoundA (XoutAFinal, XoutAif, xAddrA);
nor scanshiftA (nscanshiftA, DFTRAMBYP, SEA);
and XoutaddrA (XoutaddrA, nscanshiftA, XoutAFinal);
or XoutAFF0 (XoutAiff, XoutaddrA, XoutA);
wire NOT_CENA;
not (NOT_CENA, BMUX_CENA);
wire NOT_DFTRAMBYP;
not (NOT_DFTRAMBYP, DFTRAMBYP);
wire [18:0] READA;
buf (READA[0], NOT_CENA);
buf (READA[1], NOT_CENA);
buf (READA[2], NOT_CENA);
buf (READA[3], NOT_CENA);
buf (READA[4], NOT_CENA);
buf (READA[5], NOT_CENA);
buf (READA[6], NOT_CENA);
buf (READA[7], NOT_CENA);
buf (READA[8], NOT_CENA);
buf (READA[9], NOT_CENA);
buf (READA[10], NOT_CENA);
buf (READA[11], NOT_CENA);
buf (READA[12], NOT_CENA);
buf (READA[13], NOT_CENA);
buf (READA[14], NOT_CENA);
buf (READA[15], NOT_CENA);
buf (READA[16], NOT_CENA);
buf (READA[17], NOT_CENA);
buf (READA[18], NOT_CENA);
xor (x_detection_CENA, BMUX_CENA, BMUX_CENA);
and (acendftA, x_detection_CENA, NOT_DFTRAMBYP);
assign XoutA = (SEA & ~DFTRAMBYP) | acendftA;
_MUX reA0 (READA[0], QA[0], INT_QA[0], READ_QA[0]);
_MUX reA1 (READA[1], QA[1], INT_QA[1], READ_QA[1]);
_MUX reA2 (READA[2], QA[2], INT_QA[2], READ_QA[2]);
_MUX reA3 (READA[3], QA[3], INT_QA[3], READ_QA[3]);
_MUX reA4 (READA[4], QA[4], INT_QA[4], READ_QA[4]);
_MUX reA5 (READA[5], QA[5], INT_QA[5], READ_QA[5]);
_MUX reA6 (READA[6], QA[6], INT_QA[6], READ_QA[6]);
_MUX reA7 (READA[7], QA[7], INT_QA[7], READ_QA[7]);
_MUX reA8 (READA[8], QA[8], INT_QA[8], READ_QA[8]);
_MUX reA9 (READA[9], QA[9], INT_QA[9], READ_QA[9]);
_MUX reA10 (READA[10], QA[10], INT_QA[10], READ_QA[10]);
_MUX reA11 (READA[11], QA[11], INT_QA[11], READ_QA[11]);
_MUX reA12 (READA[12], QA[12], INT_QA[12], READ_QA[12]);
_MUX reA13 (READA[13], QA[13], INT_QA[13], READ_QA[13]);
_MUX reA14 (READA[14], QA[14], INT_QA[14], READ_QA[14]);
_MUX reA15 (READA[15], QA[15], INT_QA[15], READ_QA[15]);
_MUX reA16 (READA[16], QA[16], INT_QA[16], READ_QA[16]);
_MUX reA17 (READA[17], QA[17], INT_QA[17], READ_QA[17]);
_MUX reA18 (READA[18], QA[18], INT_QA[18], READ_QA[18]);
wire [4:0] AAXOR;
xor (AAXOR[0], BMUX_AA[0], BMUX_AA[0]);
xor (AAXOR[1], BMUX_AA[1], BMUX_AA[1]);
xor (AAXOR[2], BMUX_AA[2], BMUX_AA[2]);
xor (AAXOR[3], BMUX_AA[3], BMUX_AA[3]);
xor (AAXOR[4], BMUX_AA[4], BMUX_AA[4]);
wire xA_addr;
or (xA_addr, AAXOR[0], AAXOR[1], AAXOR[2], AAXOR[3], AAXOR[4]);
_MUX rxA0 (xA_addr, READ_QA[0], 1'bX, READ_QAX[0]);
_MUX rxA1 (xA_addr, READ_QA[1], 1'bX, READ_QAX[1]);
_MUX rxA2 (xA_addr, READ_QA[2], 1'bX, READ_QAX[2]);
_MUX rxA3 (xA_addr, READ_QA[3], 1'bX, READ_QAX[3]);
_MUX rxA4 (xA_addr, READ_QA[4], 1'bX, READ_QAX[4]);
_MUX rxA5 (xA_addr, READ_QA[5], 1'bX, READ_QAX[5]);
_MUX rxA6 (xA_addr, READ_QA[6], 1'bX, READ_QAX[6]);
_MUX rxA7 (xA_addr, READ_QA[7], 1'bX, READ_QAX[7]);
_MUX rxA8 (xA_addr, READ_QA[8], 1'bX, READ_QAX[8]);
_MUX rxA9 (xA_addr, READ_QA[9], 1'bX, READ_QAX[9]);
_MUX rxA10 (xA_addr, READ_QA[10], 1'bX, READ_QAX[10]);
_MUX rxA11 (xA_addr, READ_QA[11], 1'bX, READ_QAX[11]);
_MUX rxA12 (xA_addr, READ_QA[12], 1'bX, READ_QAX[12]);
_MUX rxA13 (xA_addr, READ_QA[13], 1'bX, READ_QAX[13]);
_MUX rxA14 (xA_addr, READ_QA[14], 1'bX, READ_QAX[14]);
_MUX rxA15 (xA_addr, READ_QA[15], 1'bX, READ_QAX[15]);
_MUX rxA16 (xA_addr, READ_QA[16], 1'bX, READ_QAX[16]);
_MUX rxA17 (xA_addr, READ_QA[17], 1'bX, READ_QAX[17]);
_MUX rxA18 (xA_addr, READ_QA[18], 1'bX, READ_QAX[18]);
_MUX mqA0 (DFTRAMBYP, READ_QAX[0], QA[1], DA_scan[0]);
_MUX mqA1 (DFTRAMBYP, READ_QAX[1], QA[2], DA_scan[1]);
_MUX mqA2 (DFTRAMBYP, READ_QAX[2], QA[3], DA_scan[2]);
_MUX mqA3 (DFTRAMBYP, READ_QAX[3], QA[4], DA_scan[3]);
_MUX mqA4 (DFTRAMBYP, READ_QAX[4], QA[5], DA_scan[4]);
_MUX mqA5 (DFTRAMBYP, READ_QAX[5], QA[6], DA_scan[5]);
_MUX mqA6 (DFTRAMBYP, READ_QAX[6], QA[7], DA_scan[6]);
_MUX mqA7 (DFTRAMBYP, READ_QAX[7], QA[8], DA_scan[7]);
_MUX mqA8 (DFTRAMBYP, READ_QAX[8], 1'b0, DA_scan[8]);
_MUX mqA9 (DFTRAMBYP, READ_QAX[9], 1'b0, DA_scan[9]);
_MUX mqA10 (DFTRAMBYP, READ_QAX[10], QA[9], DA_scan[10]);
_MUX mqA11 (DFTRAMBYP, READ_QAX[11], QA[10], DA_scan[11]);
_MUX mqA12 (DFTRAMBYP, READ_QAX[12], QA[11], DA_scan[12]);
_MUX mqA13 (DFTRAMBYP, READ_QAX[13], QA[12], DA_scan[13]);
_MUX mqA14 (DFTRAMBYP, READ_QAX[14], QA[13], DA_scan[14]);
_MUX mqA15 (DFTRAMBYP, READ_QAX[15], QA[14], DA_scan[15]);
_MUX mqA16 (DFTRAMBYP, READ_QAX[16], QA[15], DA_scan[16]);
_MUX mqA17 (DFTRAMBYP, READ_QAX[17], QA[16], DA_scan[17]);
_MUX mqA18 (DFTRAMBYP, READ_QAX[18], QA[17], DA_scan[18]);
rf2_32x19_wm0_scanflop uDQA0 (.CLK(CLKA), .SE(SEA), .SI(QA[1]), .D(DA_scan[0]), .Q(QA[0]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA1 (.CLK(CLKA), .SE(SEA), .SI(QA[2]), .D(DA_scan[1]), .Q(QA[1]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA2 (.CLK(CLKA), .SE(SEA), .SI(QA[3]), .D(DA_scan[2]), .Q(QA[2]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA3 (.CLK(CLKA), .SE(SEA), .SI(QA[4]), .D(DA_scan[3]), .Q(QA[3]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA4 (.CLK(CLKA), .SE(SEA), .SI(QA[5]), .D(DA_scan[4]), .Q(QA[4]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA5 (.CLK(CLKA), .SE(SEA), .SI(QA[6]), .D(DA_scan[5]), .Q(QA[5]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA6 (.CLK(CLKA), .SE(SEA), .SI(QA[7]), .D(DA_scan[6]), .Q(QA[6]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA7 (.CLK(CLKA), .SE(SEA), .SI(QA[8]), .D(DA_scan[7]), .Q(QA[7]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA8 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[0]), .D(DA_scan[8]), .Q(QA[8]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA9 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[1]), .D(DA_scan[9]), .Q(QA[9]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA10 (.CLK(CLKA), .SE(SEA), .SI(QA[9]), .D(DA_scan[10]), .Q(QA[10]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA11 (.CLK(CLKA), .SE(SEA), .SI(QA[10]), .D(DA_scan[11]), .Q(QA[11]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA12 (.CLK(CLKA), .SE(SEA), .SI(QA[11]), .D(DA_scan[12]), .Q(QA[12]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA13 (.CLK(CLKA), .SE(SEA), .SI(QA[12]), .D(DA_scan[13]), .Q(QA[13]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA14 (.CLK(CLKA), .SE(SEA), .SI(QA[13]), .D(DA_scan[14]), .Q(QA[14]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA15 (.CLK(CLKA), .SE(SEA), .SI(QA[14]), .D(DA_scan[15]), .Q(QA[15]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA16 (.CLK(CLKA), .SE(SEA), .SI(QA[15]), .D(DA_scan[16]), .Q(QA[16]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA17 (.CLK(CLKA), .SE(SEA), .SI(QA[16]), .D(DA_scan[17]), .Q(QA[17]), .Xout(XoutAiff));
rf2_32x19_wm0_scanflop uDQA18 (.CLK(CLKA), .SE(SEA), .SI(QA[17]), .D(DA_scan[18]), .Q(QA[18]), .Xout(XoutAiff));
assign SOA[0] = QA[0];
assign SOA[1] = QA[18];
wire [1:0] BUS_SIB;
assign BUS_SIB[0] = SIB[0];
assign BUS_SIB[1] = SIB[1];
wire [4:0] BUS_AB;
assign BUS_AB = AB;
wire [18:0] BUS_DB;
assign BUS_DB = DB;
wire [18:0] DB_scan;
wire [4:0] BMUX_AB;
wire [4:0] BMUXSEL_AB;
wire [18:0] BMUX_DB;
wire BMUX_CENB;
wire BMUXSEL_CENB;
_MUX maB0 (TENB, TAB[0], BUS_AB[0], BMUX_AB[0]);
_MUX maselB0 (DFTRAMBYP, 1'b0, BMUX_AB[0], BMUXSEL_AB[0]);
buf bufmaB0(AYB[0],BMUXSEL_AB[0]);
_MUX maB1 (TENB, TAB[1], BUS_AB[1], BMUX_AB[1]);
_MUX maselB1 (DFTRAMBYP, 1'b0, BMUX_AB[1], BMUXSEL_AB[1]);
buf bufmaB1(AYB[1],BMUXSEL_AB[1]);
_MUX maB2 (TENB, TAB[2], BUS_AB[2], BMUX_AB[2]);
_MUX maselB2 (DFTRAMBYP, 1'b0, BMUX_AB[2], BMUXSEL_AB[2]);
buf bufmaB2(AYB[2],BMUXSEL_AB[2]);
_MUX maB3 (TENB, TAB[3], BUS_AB[3], BMUX_AB[3]);
_MUX maselB3 (DFTRAMBYP, 1'b0, BMUX_AB[3], BMUXSEL_AB[3]);
buf bufmaB3(AYB[3],BMUXSEL_AB[3]);
_MUX maB4 (TENB, TAB[4], BUS_AB[4], BMUX_AB[4]);
_MUX maselB4 (DFTRAMBYP, 1'b0, BMUX_AB[4], BMUXSEL_AB[4]);
buf bufmaB4(AYB[4],BMUXSEL_AB[4]);
_MUX mdB0 (TENB, TDB[0], BUS_DB[0], BMUX_DB[0]);
_MUX mdB1 (TENB, TDB[1], BUS_DB[1], BMUX_DB[1]);
_MUX mdB2 (TENB, TDB[2], BUS_DB[2], BMUX_DB[2]);
_MUX mdB3 (TENB, TDB[3], BUS_DB[3], BMUX_DB[3]);
_MUX mdB4 (TENB, TDB[4], BUS_DB[4], BMUX_DB[4]);
_MUX mdB5 (TENB, TDB[5], BUS_DB[5], BMUX_DB[5]);
_MUX mdB6 (TENB, TDB[6], BUS_DB[6], BMUX_DB[6]);
_MUX mdB7 (TENB, TDB[7], BUS_DB[7], BMUX_DB[7]);
_MUX mdB8 (TENB, TDB[8], BUS_DB[8], BMUX_DB[8]);
_MUX mdB9 (TENB, TDB[9], BUS_DB[9], BMUX_DB[9]);
_MUX mdB10 (TENB, TDB[10], BUS_DB[10], BMUX_DB[10]);
_MUX mdB11 (TENB, TDB[11], BUS_DB[11], BMUX_DB[11]);
_MUX mdB12 (TENB, TDB[12], BUS_DB[12], BMUX_DB[12]);
_MUX mdB13 (TENB, TDB[13], BUS_DB[13], BMUX_DB[13]);
_MUX mdB14 (TENB, TDB[14], BUS_DB[14], BMUX_DB[14]);
_MUX mdB15 (TENB, TDB[15], BUS_DB[15], BMUX_DB[15]);
_MUX mdB16 (TENB, TDB[16], BUS_DB[16], BMUX_DB[16]);
_MUX mdB17 (TENB, TDB[17], BUS_DB[17], BMUX_DB[17]);
_MUX mdB18 (TENB, TDB[18], BUS_DB[18], BMUX_DB[18]);
_MUX mcenB (TENB, TCENB, CENB, BMUX_CENB);
_MUX mcenselB (DFTRAMBYP, 1'b0,BMUX_CENB, BMUXSEL_CENB);
buf bufmcenB (CENYB, BMUXSEL_CENB);
wire [4:0] B_max, B_max_n, AB_m;
wire XoutBif, XoutBiff;
wire [4:1] BMUX_AB_n, EQ_B, m_AB;
wire [3:0] XoutBi;
not BMUX_AB1_n (BMUX_AB_n[1], BMUX_AB[1]);
not BMUX_AB2_n (BMUX_AB_n[2], BMUX_AB[2]);
not BMUX_AB3_n (BMUX_AB_n[3], BMUX_AB[3]);
not BMUX_AB4_n (BMUX_AB_n[4], BMUX_AB[4]);
assign B_max[0] = 1;
assign B_max[1] = 1;
assign B_max[2] = 1;
assign B_max[3] = 1;
assign B_max[4] = 1;
not Bmax0_n (B_max_n[0], B_max[0]);
not Bmax1_n (B_max_n[1], B_max[1]);
not Bmax2_n (B_max_n[2], B_max[2]);
not Bmax3_n (B_max_n[3], B_max[3]);
not Bmax4_n (B_max_n[4], B_max[4]);
and andBMUXABAmax0 (AB_m[0], BMUX_AB[0], B_max_n[0]);
and andBMUXABAmax1 (AB_m[1], BMUX_AB[1], B_max_n[1]);
and andBMUXABAmax2 (AB_m[2], BMUX_AB[2], B_max_n[2]);
and andBMUXABAmax3 (AB_m[3], BMUX_AB[3], B_max_n[3]);
and andBMUXABAmax4 (AB_m[4], BMUX_AB[4], B_max_n[4]);
and andBMUXABAmax1_n (m_AB[1], BMUX_AB_n[1], B_max[1]);
and andBMUXABAmax2_n (m_AB[2], BMUX_AB_n[2], B_max[2]);
and andBMUXABAmax3_n (m_AB[3], BMUX_AB_n[3], B_max[3]);
and andBMUXABAmax4_n (m_AB[4], BMUX_AB_n[4], B_max[4]);
nor norABAmax1 (EQ_B[1], m_AB[1], AB_m[1]);
nor norABAmax2 (EQ_B[2], m_AB[2], AB_m[2]);
nor norABAmax3 (EQ_B[3], m_AB[3], AB_m[3]);
nor norABAmax4 (EQ_B[4], m_AB[4], AB_m[4]);
and XfABAmax0 (XoutBi[0], AB_m[0], EQ_B[4], EQ_B[3], EQ_B[2], EQ_B[1]);
and XfABAmax1 (XoutBi[1], AB_m[1], EQ_B[4], EQ_B[3], EQ_B[2]);
and XfABAmax2 (XoutBi[2], AB_m[2], EQ_B[4], EQ_B[3]);
and XfABAmax3 (XoutBi[3], AB_m[3], EQ_B[4]);
or orXfABAmax4 (XoutBif, AB_m[4], XoutBi[0], XoutBi[1], XoutBi[2], XoutBi[3]);
wire [4:0] xDetectionAddrBusB;
xor addrHandleB0 (xDetectionAddrBusB[0], BMUX_AB[0], BMUX_AB[0]);
xor addrHandleB1 (xDetectionAddrBusB[1], BMUX_AB[1], BMUX_AB[1]);
xor addrHandleB2 (xDetectionAddrBusB[2], BMUX_AB[2], BMUX_AB[2]);
xor addrHandleB3 (xDetectionAddrBusB[3], BMUX_AB[3], BMUX_AB[3]);
xor addrHandleB4 (xDetectionAddrBusB[4], BMUX_AB[4], BMUX_AB[4]);
or addrFinalB (xAddrB,xDetectionAddrBusB[0],xDetectionAddrBusB[1],xDetectionAddrBusB[2],xDetectionAddrBusB[3],xDetectionAddrBusB[4]);
or xBoundB (XoutBFinal, XoutBif, xAddrB);
nor scanshiftB (nscanshiftB, DFTRAMBYP, SEB);
and XoutaddrB (XoutaddrB, nscanshiftB, XoutBFinal);
or XoutBFF0 (XoutBiff, XoutaddrB, XoutB);
wire NOT_CENB;
not (NOT_CENB, BMUX_CENB);
wire NOT_DFTRAMBYP;
not (NOT_DFTRAMBYP, DFTRAMBYP);
wire [18:0] WRITEB;
and (WRITEB[0], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[1], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[2], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[3], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[4], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[5], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[6], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[7], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[8], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[9], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[10], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[11], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[12], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[13], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[14], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[15], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[16], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[17], NOT_DFTRAMBYP, NOT_CENB);
and (WRITEB[18], NOT_DFTRAMBYP, NOT_CENB);
rf2_32x19_wm0_bitcell memB0 (.CLK(CLKB), .WRITE(WRITEB[0]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[0]), .Xout(XoutBiff), .Q(INT_QA[0]));
rf2_32x19_wm0_bitcell memB1 (.CLK(CLKB), .WRITE(WRITEB[1]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[1]), .Xout(XoutBiff), .Q(INT_QA[1]));
rf2_32x19_wm0_bitcell memB2 (.CLK(CLKB), .WRITE(WRITEB[2]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[2]), .Xout(XoutBiff), .Q(INT_QA[2]));
rf2_32x19_wm0_bitcell memB3 (.CLK(CLKB), .WRITE(WRITEB[3]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[3]), .Xout(XoutBiff), .Q(INT_QA[3]));
rf2_32x19_wm0_bitcell memB4 (.CLK(CLKB), .WRITE(WRITEB[4]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[4]), .Xout(XoutBiff), .Q(INT_QA[4]));
rf2_32x19_wm0_bitcell memB5 (.CLK(CLKB), .WRITE(WRITEB[5]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[5]), .Xout(XoutBiff), .Q(INT_QA[5]));
rf2_32x19_wm0_bitcell memB6 (.CLK(CLKB), .WRITE(WRITEB[6]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[6]), .Xout(XoutBiff), .Q(INT_QA[6]));
rf2_32x19_wm0_bitcell memB7 (.CLK(CLKB), .WRITE(WRITEB[7]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[7]), .Xout(XoutBiff), .Q(INT_QA[7]));
rf2_32x19_wm0_bitcell memB8 (.CLK(CLKB), .WRITE(WRITEB[8]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[8]), .Xout(XoutBiff), .Q(INT_QA[8]));
rf2_32x19_wm0_bitcell memB9 (.CLK(CLKB), .WRITE(WRITEB[9]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[9]), .Xout(XoutBiff), .Q(INT_QA[9]));
rf2_32x19_wm0_bitcell memB10 (.CLK(CLKB), .WRITE(WRITEB[10]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[10]), .Xout(XoutBiff), .Q(INT_QA[10]));
rf2_32x19_wm0_bitcell memB11 (.CLK(CLKB), .WRITE(WRITEB[11]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[11]), .Xout(XoutBiff), .Q(INT_QA[11]));
rf2_32x19_wm0_bitcell memB12 (.CLK(CLKB), .WRITE(WRITEB[12]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[12]), .Xout(XoutBiff), .Q(INT_QA[12]));
rf2_32x19_wm0_bitcell memB13 (.CLK(CLKB), .WRITE(WRITEB[13]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[13]), .Xout(XoutBiff), .Q(INT_QA[13]));
rf2_32x19_wm0_bitcell memB14 (.CLK(CLKB), .WRITE(WRITEB[14]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[14]), .Xout(XoutBiff), .Q(INT_QA[14]));
rf2_32x19_wm0_bitcell memB15 (.CLK(CLKB), .WRITE(WRITEB[15]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[15]), .Xout(XoutBiff), .Q(INT_QA[15]));
rf2_32x19_wm0_bitcell memB16 (.CLK(CLKB), .WRITE(WRITEB[16]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[16]), .Xout(XoutBiff), .Q(INT_QA[16]));
rf2_32x19_wm0_bitcell memB17 (.CLK(CLKB), .WRITE(WRITEB[17]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[17]), .Xout(XoutBiff), .Q(INT_QA[17]));
rf2_32x19_wm0_bitcell memB18 (.CLK(CLKB), .WRITE(WRITEB[18]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[18]), .Xout(XoutBiff), .Q(INT_QA[18]));
xor (x_detection_CENB, BMUX_CENB, BMUX_CENB);
and (acendftB, x_detection_CENB, NOT_DFTRAMBYP);
assign XoutB = (SEB & ~DFTRAMBYP) | acendftB;
wire [18:0] QB_int;
wire [18:0] DB_hold;
_MUX mhB0 (BMUX_CENB, BMUX_DB[0], QB_int[0], DB_hold[0]);
_MUX mhB1 (BMUX_CENB, BMUX_DB[1], QB_int[1], DB_hold[1]);
_MUX mhB2 (BMUX_CENB, BMUX_DB[2], QB_int[2], DB_hold[2]);
_MUX mhB3 (BMUX_CENB, BMUX_DB[3], QB_int[3], DB_hold[3]);
_MUX mhB4 (BMUX_CENB, BMUX_DB[4], QB_int[4], DB_hold[4]);
_MUX mhB5 (BMUX_CENB, BMUX_DB[5], QB_int[5], DB_hold[5]);
_MUX mhB6 (BMUX_CENB, BMUX_DB[6], QB_int[6], DB_hold[6]);
_MUX mhB7 (BMUX_CENB, BMUX_DB[7], QB_int[7], DB_hold[7]);
_MUX mhB8 (BMUX_CENB, BMUX_DB[8], QB_int[8], DB_hold[8]);
_MUX mhB9 (BMUX_CENB, BMUX_DB[9], QB_int[9], DB_hold[9]);
_MUX mhB10 (BMUX_CENB, BMUX_DB[10], QB_int[10], DB_hold[10]);
_MUX mhB11 (BMUX_CENB, BMUX_DB[11], QB_int[11], DB_hold[11]);
_MUX mhB12 (BMUX_CENB, BMUX_DB[12], QB_int[12], DB_hold[12]);
_MUX mhB13 (BMUX_CENB, BMUX_DB[13], QB_int[13], DB_hold[13]);
_MUX mhB14 (BMUX_CENB, BMUX_DB[14], QB_int[14], DB_hold[14]);
_MUX mhB15 (BMUX_CENB, BMUX_DB[15], QB_int[15], DB_hold[15]);
_MUX mhB16 (BMUX_CENB, BMUX_DB[16], QB_int[16], DB_hold[16]);
_MUX mhB17 (BMUX_CENB, BMUX_DB[17], QB_int[17], DB_hold[17]);
_MUX mhB18 (BMUX_CENB, BMUX_DB[18], QB_int[18], DB_hold[18]);
_MUX mqB0 (DFTRAMBYP, DB_hold[0], BMUX_DB[0], DB_scan[0]);
_MUX mqB1 (DFTRAMBYP, DB_hold[1], BMUX_DB[1], DB_scan[1]);
_MUX mqB2 (DFTRAMBYP, DB_hold[2], BMUX_DB[2], DB_scan[2]);
_MUX mqB3 (DFTRAMBYP, DB_hold[3], BMUX_DB[3], DB_scan[3]);
_MUX mqB4 (DFTRAMBYP, DB_hold[4], BMUX_DB[4], DB_scan[4]);
_MUX mqB5 (DFTRAMBYP, DB_hold[5], BMUX_DB[5], DB_scan[5]);
_MUX mqB6 (DFTRAMBYP, DB_hold[6], BMUX_DB[6], DB_scan[6]);
_MUX mqB7 (DFTRAMBYP, DB_hold[7], BMUX_DB[7], DB_scan[7]);
_MUX mqB8 (DFTRAMBYP, DB_hold[8], BMUX_DB[8], DB_scan[8]);
_MUX mqB9 (DFTRAMBYP, DB_hold[9], BMUX_DB[9], DB_scan[9]);
_MUX mqB10 (DFTRAMBYP, DB_hold[10], BMUX_DB[10], DB_scan[10]);
_MUX mqB11 (DFTRAMBYP, DB_hold[11], BMUX_DB[11], DB_scan[11]);
_MUX mqB12 (DFTRAMBYP, DB_hold[12], BMUX_DB[12], DB_scan[12]);
_MUX mqB13 (DFTRAMBYP, DB_hold[13], BMUX_DB[13], DB_scan[13]);
_MUX mqB14 (DFTRAMBYP, DB_hold[14], BMUX_DB[14], DB_scan[14]);
_MUX mqB15 (DFTRAMBYP, DB_hold[15], BMUX_DB[15], DB_scan[15]);
_MUX mqB16 (DFTRAMBYP, DB_hold[16], BMUX_DB[16], DB_scan[16]);
_MUX mqB17 (DFTRAMBYP, DB_hold[17], BMUX_DB[17], DB_scan[17]);
_MUX mqB18 (DFTRAMBYP, DB_hold[18], BMUX_DB[18], DB_scan[18]);
rf2_32x19_wm0_scanflop uDQB0 (.CLK(CLKB), .SE(SEB), .SI(QB_int[1]), .D(DB_scan[0]), .Q(QB_int[0]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB1 (.CLK(CLKB), .SE(SEB), .SI(QB_int[2]), .D(DB_scan[1]), .Q(QB_int[1]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB2 (.CLK(CLKB), .SE(SEB), .SI(QB_int[3]), .D(DB_scan[2]), .Q(QB_int[2]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB3 (.CLK(CLKB), .SE(SEB), .SI(QB_int[4]), .D(DB_scan[3]), .Q(QB_int[3]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB4 (.CLK(CLKB), .SE(SEB), .SI(QB_int[5]), .D(DB_scan[4]), .Q(QB_int[4]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB5 (.CLK(CLKB), .SE(SEB), .SI(QB_int[6]), .D(DB_scan[5]), .Q(QB_int[5]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB6 (.CLK(CLKB), .SE(SEB), .SI(QB_int[7]), .D(DB_scan[6]), .Q(QB_int[6]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB7 (.CLK(CLKB), .SE(SEB), .SI(QB_int[8]), .D(DB_scan[7]), .Q(QB_int[7]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB8 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[0]), .D(DB_scan[8]), .Q(QB_int[8]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB9 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[1]), .D(DB_scan[9]), .Q(QB_int[9]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB10 (.CLK(CLKB), .SE(SEB), .SI(QB_int[9]), .D(DB_scan[10]), .Q(QB_int[10]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB11 (.CLK(CLKB), .SE(SEB), .SI(QB_int[10]), .D(DB_scan[11]), .Q(QB_int[11]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB12 (.CLK(CLKB), .SE(SEB), .SI(QB_int[11]), .D(DB_scan[12]), .Q(QB_int[12]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB13 (.CLK(CLKB), .SE(SEB), .SI(QB_int[12]), .D(DB_scan[13]), .Q(QB_int[13]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB14 (.CLK(CLKB), .SE(SEB), .SI(QB_int[13]), .D(DB_scan[14]), .Q(QB_int[14]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB15 (.CLK(CLKB), .SE(SEB), .SI(QB_int[14]), .D(DB_scan[15]), .Q(QB_int[15]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB16 (.CLK(CLKB), .SE(SEB), .SI(QB_int[15]), .D(DB_scan[16]), .Q(QB_int[16]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB17 (.CLK(CLKB), .SE(SEB), .SI(QB_int[16]), .D(DB_scan[17]), .Q(QB_int[17]), .Xout(XoutBiff));
rf2_32x19_wm0_scanflop uDQB18 (.CLK(CLKB), .SE(SEB), .SI(QB_int[17]), .D(DB_scan[18]), .Q(QB_int[18]), .Xout(XoutBiff));
assign SOB[0] = QB_int[0];
assign SOB[1] = QB_int[18];
endmodule
`undef read_write
`disable_portfaults
`nosuppress_faults

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# Copyright (c) 1993 - 2019 ARM Limited. All Rights Reserved.
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Limited.
# PhyVGen V 8.3.0
# ARM Version r4p0
# Creation Date: Mon Nov 11 12:00:01 2019
defineGateSize "rf2_32x19_wm0" "AA[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AA[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AA[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AA[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AA[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AA[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AA[3]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AA[3]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AA[4]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AA[4]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AB[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AB[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AB[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AB[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AB[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AB[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AB[3]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AB[3]" '(0.018)
defineGateSize "rf2_32x19_wm0" "AB[4]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "AB[4]" '(0.018)
defineGateSize "rf2_32x19_wm0" "CENA" 0.014
defineDiodeProtection "rf2_32x19_wm0" "CENA" '(0.018)
defineGateSize "rf2_32x19_wm0" "CENB" 0.014
defineDiodeProtection "rf2_32x19_wm0" "CENB" '(0.018)
defineGateSize "rf2_32x19_wm0" "CLKA" 0.014
defineDiodeProtection "rf2_32x19_wm0" "CLKA" '(0.018)
defineGateSize "rf2_32x19_wm0" "CLKB" 0.014
defineDiodeProtection "rf2_32x19_wm0" "CLKB" '(0.018)
defineGateSize "rf2_32x19_wm0" "COLLDISN" 0.014
defineDiodeProtection "rf2_32x19_wm0" "COLLDISN" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[10]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[10]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[11]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[11]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[12]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[12]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[13]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[13]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[14]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[14]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[15]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[15]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[16]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[16]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[17]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[17]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[18]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[18]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[3]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[3]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[4]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[4]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[5]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[5]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[6]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[6]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[7]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[7]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[8]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[8]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DB[9]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DB[9]" '(0.018)
defineGateSize "rf2_32x19_wm0" "DFTRAMBYP" 0.014
defineDiodeProtection "rf2_32x19_wm0" "DFTRAMBYP" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMAA[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMAA[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMAA[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMAA[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMAA[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMAA[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMAB[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMAB[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMAB[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMAB[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMAB[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMAB[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "EMASA" 0.014
defineDiodeProtection "rf2_32x19_wm0" "EMASA" '(0.018)
defineGateSize "rf2_32x19_wm0" "RET1N" 0.014
defineDiodeProtection "rf2_32x19_wm0" "RET1N" '(0.018)
defineGateSize "rf2_32x19_wm0" "SEA" 0.014
defineDiodeProtection "rf2_32x19_wm0" "SEA" '(0.018)
defineGateSize "rf2_32x19_wm0" "SEB" 0.014
defineDiodeProtection "rf2_32x19_wm0" "SEB" '(0.018)
defineGateSize "rf2_32x19_wm0" "SIA[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "SIA[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "SIA[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "SIA[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "SIB[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "SIB[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "SIB[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "SIB[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAA[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAA[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAA[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAA[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAA[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAA[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAA[3]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAA[3]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAA[4]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAA[4]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAB[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAB[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAB[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAB[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAB[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAB[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAB[3]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAB[3]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TAB[4]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TAB[4]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TCENA" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TCENA" '(0.018)
defineGateSize "rf2_32x19_wm0" "TCENB" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TCENB" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[0]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[0]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[10]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[10]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[11]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[11]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[12]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[12]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[13]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[13]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[14]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[14]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[15]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[15]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[16]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[16]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[17]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[17]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[18]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[18]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[1]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[1]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[2]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[2]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[3]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[3]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[4]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[4]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[5]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[5]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[6]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[6]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[7]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[7]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[8]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[8]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TDB[9]" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TDB[9]" '(0.018)
defineGateSize "rf2_32x19_wm0" "TENA" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TENA" '(0.018)
defineGateSize "rf2_32x19_wm0" "TENB" 0.014
defineDiodeProtection "rf2_32x19_wm0" "TENB" '(0.018)

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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Mon Nov 11 11:59:11 2019
#
# Instance Options:
# Instance Name: rf2_32x19_wm0
# Number of Words: 32
# Number of Bits: 19
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: off
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_32x19_wm0 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 669
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.99 0.99
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 6.46914e-05nF
VDDPE VSSE 1.34730e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 2.37238mA
VDDPE VSSE 2.99422mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 7.11605e-05nF
VDDPE VSSE 7.17701e-04nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 2.60961mA
VDDPE VSSE 12.10194mA
}
Cpd avm_read_write {
VDDCE VSSE 8.47271e-05nF
VDDPE VSSE 1.61911e-03nF
}
PEAK_I avm_read_write {
VDDCE VSSE 3.46982mA
VDDPE VSSE 17.44105mA
}
Cpd avm_read_desel {
VDDCE VSSE 3.73601e-05nF
VDDPE VSSE 8.02541e-04nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 1.73316mA
VDDPE VSSE 11.37893mA
}
Cpd avm_desel_write {
VDDCE VSSE 4.73670e-05nF
VDDPE VSSE 8.16567e-04nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 1.75233mA
VDDPE VSSE 12.18938mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.27046e-06nF
VDDPE VSSE 2.20337e-03nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.42769mA
VDDPE VSSE 11.39868mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.27046e-06nF
VDDPE VSSE 2.20337e-03nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.42769mA
VDDPE VSSE 11.39868mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.95501e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 2.17223e-05nF
}
LEAKAGE_I {
VDDCE VSSE 4.74690e-02mA
VDDPE VSSE 0.31536mA
}
tsu 0.092778ns
ck2q_delay 0.272935ns
tr_q 0.013428ns
tf_q 0.0155257ns
CHARACTERIZATION_MODE accurate
}

322
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.dat Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Mon Nov 11 11:59:34 2019
#
# Instance Options:
# Instance Name: rf2_32x19_wm0
# Number of Words: 32
# Number of Bits: 19
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: off
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name ff_0p99v_0p99v_125c
S N
geomx 21.1650
geomy 100.9400
volt 0.9900
temp 125.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.0917
ttcenacenya 0.0905
ttenacenyapu 0.1191
ttenacenyanu 0.1399
tdftrambypcenya 0.0912
taaaya 0.0751
ttaaaya 0.0751
ttenaayapu 0.1377
ttenaayanu 0.1335
tdftrambypaya 0.0823
tcenbcenyb 0.0947
ttcenbcenyb 0.0939
ttenbcenybpu 0.1240
ttenbcenybnu 0.1515
tdftrambypcenyb 0.0907
tabayb 0.0753
ttabayb 0.0779
ttenbaybpu 0.1447
ttenbaybnu 0.1398
tdftrambypayb 0.0822
taccqa_rd0 0.2718
taccqa_rd1 0.2724
taccqa_rd2 0.2724
taccqa_rd3 0.2729
taccqa_rd4 0.3149
taccqa_rd5 0.3516
taccqa_rd6 0.3900
taccqa_rd7 0.4267
taccqa_scan0 0.2718
taccqa_scan1 0.2724
taccqa_scan2 0.2724
taccqa_scan3 0.2729
taccqa_scan4 0.3149
taccqa_scan5 0.3516
taccqa_scan6 0.3900
taccqa_scan7 0.4267
tclkasoa_rd0 0.2903
tclkasoa_rd1 0.2908
tclkasoa_rd2 0.2909
tclkasoa_rd3 0.2914
tclkasoa_rd4 0.3334
tclkasoa_rd5 0.3700
tclkasoa_rd6 0.4085
tclkasoa_rd7 0.4452
tclkasoa_scan0 0.2903
tclkasoa_scan1 0.2908
tclkasoa_scan2 0.2909
tclkasoa_scan3 0.2914
tclkasoa_scan4 0.3334
tclkasoa_scan5 0.3700
tclkasoa_scan6 0.4085
tclkasoa_scan7 0.4452
tclkbsob 0.1594
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 1.7116
kload_aya 1.4236
kload_cenyb 1.6712
kload_ayb 1.4006
kload_qa 0.5053
kload_soa 1.3720
kload_sob 1.4400
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.3800
tcyca_ema1 0.3806
tcyca_ema2 0.3806
tcyca_ema3 0.3812
tcyca_ema4 0.4238
tcyca_ema5 0.4610
tcyca_ema6 0.5000
tcyca_ema7 0.5373
tcycb_ema0 0.4062
tcycb_ema1 0.4106
tcycb_ema2 0.4143
tcycb_ema3 0.4208
tcycb_ema4 0.4729
tcycb_ema5 0.5088
tcycb_ema6 0.5566
tcycb_ema7 0.5917
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.1913
tcracwb_rd1 0.1919
tcracwb_rd2 0.1920
tcracwb_rd3 0.1925
tcracwb_rd4 0.2344
tcracwb_rd5 0.2711
tcracwb_rd6 0.3096
tcracwb_rd7 0.3463
tcwbcra_wr0 0.2458
tcwbcra_wr1 0.2501
tcwbcra_wr2 0.2538
tcwbcra_wr3 0.2603
tcwbcra_wr4 0.3115
tcwbcra_wr5 0.3469
tcwbcra_wr6 0.3940
tcwbcra_wr7 0.4286
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.0926
tckal 0.0897
tckbh 0.0958
tckbl 0.0907
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.0902
taas 0.0928
tcenbs 0.0960
tabs 0.0993
tdbs 0.0373
temaas 0.4065
temasas 0.4065
temabs 0.4461
ttenas 0.1737
ttcenas 0.0905
ttaas 0.0948
ttenbs 0.2348
ttcenbs 0.0965
ttabs 0.1030
ttdbs 0.0382
tsias 0.1911
tseas 0.1911
tdftrambypas 0.1493
tdftrambypbs 0.1493
tsibs 0.0373
tsebs 0.2348
tcolldisnas 0.4065
tcolldisnbs 0.4461
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0398
tcenaf_ret1nfh 0.4558
tcenaf_ret1nrh 0.2536
taah 0.0695
tcenbh 0.0422
tcenbf_ret1nfh 0.4558
tcenbf_ret1nrh 0.2536
tabh 0.0637
tdbh 0.0950
temaah 0.6293
temasah 0.6293
temabh 0.6267
ttenah 0.0764
ttcenah 0.0410
ttcenaf_ret1nfh 0.4558
ttcenaf_ret1nrh 0.2536
ttaah 0.0695
ttenbh 0.1045
ttcenbh 0.0435
ttcenbf_ret1nfh 0.4558
ttcenbf_ret1nrh 0.2536
ttabh 0.0637
ttdbh 0.0950
tret1nf_dftrambypfh 0.0241
tret1nr_dftrambypfh 0.4558
tret1nf_cenbrh 0.0241
tret1nf_cenarh 0.0226
tret1nf_tcenarh 0.0226
tret1nf_tcenbrh 0.0241
tret1nr_tcenbrh 0.4558
tret1nr_tcenarh 0.4162
tret1nr_cenbrh 0.4558
tret1nr_cenarh 0.4162
tsiah 0.0756
tseah 0.6293
tdftrambypah 0.6293
tdftrambypbh 0.4558
tdftrambypr_ret1nfh 0.4558
tdftrambypr_ret1nrh 0.2536
tsibh 0.0950
tsebh 0.1045
tcolldisnah 0.6293
tcolldisnbh 0.6267
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0105
icap_cena 0.0018
icap_aa 0.0012
icap_clkb 0.0106
icap_cenb 0.0015
icap_ab 0.0012
icap_db 0.0019
icap_emaa 0.0059
icap_emasa 0.0021
icap_emab 0.0057
icap_tena 0.0010
icap_tcena 0.0016
icap_taa 0.0014
icap_tenb 0.0012
icap_tcenb 0.0016
icap_tab 0.0014
icap_tdb 0.0016
icap_sia 0.0015
icap_sea 0.0019
icap_dftrambyp 0.0021
icap_sib 0.0056
icap_seb 0.0019
icap_colldisn 0.0024
icap_ret1n 0.0035
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 0.047469
icc_standby_p_chipdisable 0.315359
icc_standby_c_ret1 0.049704
icc_standby_p_ret1 0.029192
icc_standby_c_selective_precharge 0.043909
icc_standby_p_selective_precharge 0.300193
icc_c_rd0_a 3.684e-05
icc_c_rd1_a 3.686e-05
icc_c_rd2_a 3.688e-05
icc_c_rd3_a 3.699e-05
icc_c_rd4_a 3.716e-05
icc_c_rd5_a 3.721e-05
icc_c_rd6_a 3.740e-05
icc_c_rd7_a 3.740e-05
icc_p_rd0_a 7.939e-04
icc_p_rd1_a 7.939e-04
icc_p_rd2_a 7.945e-04
icc_p_rd3_a 7.945e-04
icc_p_rd4_a 7.945e-04
icc_p_rd5_a 7.973e-04
icc_p_rd6_a 7.989e-04
icc_p_rd7_a 7.991e-04
icc_c_wr0_b 4.675e-05
icc_c_wr1_b 4.677e-05
icc_c_wr2_b 4.678e-05
icc_c_wr3_b 4.689e-05
icc_c_wr4_b 4.706e-05
icc_c_wr5_b 4.712e-05
icc_c_wr6_b 4.731e-05
icc_c_wr7_b 4.731e-05
icc_p_wr0_b 8.078e-04
icc_p_wr1_b 8.078e-04
icc_p_wr2_b 8.084e-04
icc_p_wr3_b 8.084e-04
icc_p_wr4_b 8.084e-04
icc_p_wr5_b 8.112e-04
icc_p_wr6_b 8.128e-04
icc_p_wr7_b 8.130e-04
icc_c_desela 0.000e+00
icc_p_desela 6.071e-05
icc_c_deselb 0.000e+00
icc_p_deselb 1.273e-04
icc_c_peak 3.469816
icc_p_peak 17.441054
icc_c_inrush 2.619715
icc_p_inrush 12.101938

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models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ff_0p99v_0p99v_125c.ps Normal file
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models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v Normal file
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/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
/* common_memcomp Version: 4.0.5.2-amci */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_32x19_wm0_rtl_top
// Words: 32
// User Bits: 19
// Mux: 2
// Drive: 6
// Write Mask: Off
// Extra Margin Adjustment: On
// Redundancy: off
// Redundant Rows: 0
// Redundant Columns: 2
// Test Muxes On
// Ser: none
// Retention: on
// Power Gating: off
//
// Creation Date: Mon Nov 11 12:01:10 2019
// Version: r4p0
//
// Verified
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
`timescale 1ns/1ps
module rf2_32x19_wm0_rtl_top (
CENYA,
AYA,
CENYB,
AYB,
QA,
SOA,
SOB,
CLKA,
CENA,
AA,
CLKB,
CENB,
AB,
DB,
EMAA,
EMASA,
EMAB,
TENA,
TCENA,
TAA,
TENB,
TCENB,
TAB,
TDB,
RET1N,
SIA,
SEA,
DFTRAMBYP,
SIB,
SEB,
COLLDISN
);
output CENYA;
output [4:0] AYA;
output CENYB;
output [4:0] AYB;
output [18:0] QA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [4:0] AA;
input CLKB;
input CENB;
input [4:0] AB;
input [18:0] DB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [4:0] TAA;
input TENB;
input TCENB;
input [4:0] TAB;
input [18:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
wire [18:0] QOA;
wire [18:0] DIB;
assign QA = QOA;
assign DIB = DB;
rf2_32x19_wm0_fr_top u0 (
.CENYA(CENYA),
.AYA(AYA),
.CENYB(CENYB),
.AYB(AYB),
.QOA(QOA),
.SOA(SOA),
.SOB(SOB),
.CLKA(CLKA),
.CENA(CENA),
.AA(AA),
.CLKB(CLKB),
.CENB(CENB),
.AB(AB),
.DIB(DIB),
.EMAA(EMAA),
.EMASA(EMASA),
.EMAB(EMAB),
.TENA(TENA),
.TCENA(TCENA),
.TAA(TAA),
.TENB(TENB),
.TCENB(TCENB),
.TAB(TAB),
.TDB(TDB),
.RET1N(RET1N),
.SIA(SIA),
.SEA(SEA),
.DFTRAMBYP(DFTRAMBYP),
.SIB(SIB),
.SEB(SEB),
.COLLDISN(COLLDISN)
);
endmodule
module rf2_32x19_wm0_fr_top (
CENYA,
AYA,
CENYB,
AYB,
QOA,
SOA,
SOB,
CLKA,
CENA,
AA,
CLKB,
CENB,
AB,
DIB,
EMAA,
EMASA,
EMAB,
TENA,
TCENA,
TAA,
TENB,
TCENB,
TAB,
TDB,
RET1N,
SIA,
SEA,
DFTRAMBYP,
SIB,
SEB,
COLLDISN
);
output CENYA;
output [4:0] AYA;
output CENYB;
output [4:0] AYB;
output [18:0] QOA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [4:0] AA;
input CLKB;
input CENB;
input [4:0] AB;
input [18:0] DIB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [4:0] TAA;
input TENB;
input TCENB;
input [4:0] TAB;
input [18:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
wire [18:0] DB;
wire [18:0] QA;
assign DB=DIB;
assign QOA=QA;
rf2_32x19_wm0 u0 (
.CENYA(CENYA),
.AYA(AYA),
.CENYB(CENYB),
.AYB(AYB),
.QA(QA),
.SOA(SOA),
.SOB(SOB),
.CLKA(CLKA),
.CENA(CENA),
.AA(AA),
.CLKB(CLKB),
.CENB(CENB),
.AB(AB),
.DB(DB),
.EMAA(EMAA),
.EMASA(EMASA),
.EMAB(EMAB),
.TENA(TENA),
.TCENA(TCENA),
.TAA(TAA),
.TENB(TENB),
.TCENB(TCENB),
.TAB(TAB),
.TDB(TDB),
.RET1N(RET1N),
.SIA(SIA),
.SEA(SEA),
.DFTRAMBYP(DFTRAMBYP),
.SIB(SIB),
.SEB(SEB),
.COLLDISN(COLLDISN)
);
endmodule // rf2_32x19_wm0_fr_top

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models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Mon Nov 11 11:59:17 2019
#
# Instance Options:
# Instance Name: rf2_32x19_wm0
# Number of Words: 32
# Number of Bits: 19
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: off
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_32x19_wm0 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 669
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.81 0.81
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 5.76886e-05nF
VDDPE VSSE 1.27989e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 0.76535mA
VDDPE VSSE 0.93511mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 6.34575e-05nF
VDDPE VSSE 7.30835e-04nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 0.84189mA
VDDPE VSSE 4.18352mA
}
Cpd avm_read_write {
VDDCE VSSE 7.36082e-05nF
VDDPE VSSE 1.50204e-03nF
}
PEAK_I avm_read_write {
VDDCE VSSE 1.25799mA
VDDPE VSSE 5.12310mA
}
Cpd avm_read_desel {
VDDCE VSSE 3.25605e-05nF
VDDPE VSSE 7.35075e-04nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 0.64128mA
VDDPE VSSE 3.47188mA
}
Cpd avm_desel_write {
VDDCE VSSE 4.10477e-05nF
VDDPE VSSE 7.66967e-04nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 0.62343mA
VDDPE VSSE 3.82429mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.45177e-06nF
VDDPE VSSE 2.05103e-03nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.13288mA
VDDPE VSSE 3.77962mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.45177e-06nF
VDDPE VSSE 2.05103e-03nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.13288mA
VDDPE VSSE 3.77962mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.69190e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.87989e-05nF
}
LEAKAGE_I {
VDDCE VSSE 4.42400e-05mA
VDDPE VSSE 7.31600e-05mA
}
tsu 0.25018ns
ck2q_delay 0.654227ns
tr_q 0.0348014ns
tf_q 0.0395567ns
CHARACTERIZATION_MODE accurate
}

322
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.dat Normal file
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@ -0,0 +1,322 @@
#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Mon Nov 11 11:59:38 2019
#
# Instance Options:
# Instance Name: rf2_32x19_wm0
# Number of Words: 32
# Number of Bits: 19
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: off
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name ss_0p81v_0p81v_m40c
S N
geomx 21.1650
geomy 100.9400
volt 0.8100
temp -40.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.2145
ttcenacenya 0.2108
ttenacenyapu 0.3031
ttenacenyanu 0.3532
tdftrambypcenya 0.2178
taaaya 0.2110
ttaaaya 0.2184
ttenaayapu 0.3903
ttenaayanu 0.3746
tdftrambypaya 0.2078
tcenbcenyb 0.2113
ttcenbcenyb 0.2108
ttenbcenybpu 0.3062
ttenbcenybnu 0.3744
tdftrambypcenyb 0.2168
tabayb 0.2105
ttabayb 0.2161
ttenbaybpu 0.4138
ttenbaybnu 0.3794
tdftrambypayb 0.2083
taccqa_rd0 0.6468
taccqa_rd1 0.6493
taccqa_rd2 0.6522
taccqa_rd3 0.6542
taccqa_rd4 0.7720
taccqa_rd5 0.8868
taccqa_rd6 1.0184
taccqa_rd7 1.1326
taccqa_scan0 0.6468
taccqa_scan1 0.6493
taccqa_scan2 0.6522
taccqa_scan3 0.6542
taccqa_scan4 0.7720
taccqa_scan5 0.8868
taccqa_scan6 1.0184
taccqa_scan7 1.1326
tclkasoa_rd0 0.7505
tclkasoa_rd1 0.7530
tclkasoa_rd2 0.7559
tclkasoa_rd3 0.7580
tclkasoa_rd4 0.8757
tclkasoa_rd5 0.9905
tclkasoa_rd6 1.1222
tclkasoa_rd7 1.2364
tclkasoa_scan0 0.7505
tclkasoa_scan1 0.7530
tclkasoa_scan2 0.7559
tclkasoa_scan3 0.7580
tclkasoa_scan4 0.8757
tclkasoa_scan5 0.9905
tclkasoa_scan6 1.1222
tclkasoa_scan7 1.2364
tclkbsob 0.4116
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 3.3060
kload_aya 2.7500
kload_cenyb 3.3440
kload_ayb 2.7720
kload_qa 1.0935
kload_soa 2.7600
kload_sob 3.1660
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.9449
tcyca_ema1 0.9474
tcyca_ema2 0.9504
tcyca_ema3 0.9524
tcyca_ema4 1.0720
tcyca_ema5 1.1885
tcyca_ema6 1.3221
tcyca_ema7 1.4380
tcycb_ema0 1.2005
tcycb_ema1 1.2125
tcycb_ema2 1.2291
tcycb_ema3 1.2494
tcycb_ema4 1.3876
tcycb_ema5 1.5019
tcycb_ema6 1.6521
tcycb_ema7 1.7664
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.4248
tcracwb_rd1 0.4273
tcracwb_rd2 0.4302
tcracwb_rd3 0.4322
tcracwb_rd4 0.5500
tcracwb_rd5 0.6648
tcracwb_rd6 0.7964
tcracwb_rd7 0.9106
tcwbcra_wr0 0.6462
tcwbcra_wr1 0.6580
tcwbcra_wr2 0.6743
tcwbcra_wr3 0.6944
tcwbcra_wr4 0.8306
tcwbcra_wr5 0.9431
tcwbcra_wr6 1.0911
tcwbcra_wr7 1.2037
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.1790
tckal 0.1936
tckbh 0.1813
tckbl 0.1760
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.2125
taas 0.2502
tcenbs 0.2141
tabs 0.2561
tdbs 0.2167
temaas 1.0358
temasas 1.0358
temabs 1.3328
ttenas 0.4407
ttcenas 0.2138
ttaas 0.2589
ttenbs 0.5692
ttcenbs 0.2147
ttabs 0.2633
ttdbs 0.2206
tsias 0.4848
tseas 0.4848
tdftrambypas 0.4140
tdftrambypbs 0.4140
tsibs 0.2167
tsebs 0.5692
tcolldisnas 1.0358
tcolldisnbs 1.3328
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0854
tcenaf_ret1nfh 1.3136
tcenaf_ret1nrh 0.6293
taah 0.1392
tcenbh 0.0857
tcenbf_ret1nfh 1.3136
tcenbf_ret1nrh 0.6293
tabh 0.1263
tdbh 0.1864
temaah 1.6903
temasah 1.6903
temabh 1.8306
ttenah 0.1531
ttcenah 0.0871
ttcenaf_ret1nfh 1.3136
ttcenaf_ret1nrh 0.6293
ttaah 0.1392
ttenbh 0.2050
ttcenbh 0.0870
ttcenbf_ret1nfh 1.3136
ttcenbf_ret1nrh 0.6293
ttabh 0.1263
ttdbh 0.1864
tret1nf_dftrambypfh 0.0537
tret1nr_dftrambypfh 1.3136
tret1nf_cenbrh 0.0537
tret1nf_cenarh 0.0534
tret1nf_tcenarh 0.0534
tret1nf_tcenbrh 0.0537
tret1nr_tcenbrh 1.3136
tret1nr_tcenarh 1.0166
tret1nr_cenbrh 1.3136
tret1nr_cenarh 1.0166
tsiah 0.1247
tseah 1.6903
tdftrambypah 1.6903
tdftrambypbh 1.3136
tdftrambypr_ret1nfh 1.3136
tdftrambypr_ret1nrh 0.6293
tsibh 0.1864
tsebh 0.2050
tcolldisnah 1.6903
tcolldisnbh 1.8306
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0087
icap_cena 0.0014
icap_aa 0.0017
icap_clkb 0.0088
icap_cenb 0.0011
icap_ab 0.0015
icap_db 0.0018
icap_emaa 0.0056
icap_emasa 0.0021
icap_emab 0.0054
icap_tena 0.0008
icap_tcena 0.0012
icap_taa 0.0016
icap_tenb 0.0009
icap_tcenb 0.0012
icap_tab 0.0014
icap_tdb 0.0015
icap_sia 0.0011
icap_sea 0.0016
icap_dftrambyp 0.0016
icap_sib 0.0054
icap_seb 0.0017
icap_colldisn 0.0021
icap_ret1n 0.0032
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 4.424e-05
icc_standby_p_chipdisable 7.316e-05
icc_standby_c_ret1 4.397e-05
icc_standby_p_ret1 4.152e-07
icc_standby_c_selective_precharge 4.344e-05
icc_standby_p_selective_precharge 6.081e-05
icc_c_rd0_a 2.630e-05
icc_c_rd1_a 2.635e-05
icc_c_rd2_a 2.637e-05
icc_c_rd3_a 2.637e-05
icc_c_rd4_a 2.637e-05
icc_c_rd5_a 2.637e-05
icc_c_rd6_a 2.659e-05
icc_c_rd7_a 2.659e-05
icc_p_rd0_a 5.954e-04
icc_p_rd1_a 5.954e-04
icc_p_rd2_a 5.954e-04
icc_p_rd3_a 5.954e-04
icc_p_rd4_a 5.954e-04
icc_p_rd5_a 5.954e-04
icc_p_rd6_a 5.954e-04
icc_p_rd7_a 5.954e-04
icc_c_wr0_b 3.317e-05
icc_c_wr1_b 3.322e-05
icc_c_wr2_b 3.325e-05
icc_c_wr3_b 3.325e-05
icc_c_wr4_b 3.325e-05
icc_c_wr5_b 3.325e-05
icc_c_wr6_b 3.346e-05
icc_c_wr7_b 3.347e-05
icc_p_wr0_b 6.212e-04
icc_p_wr1_b 6.212e-04
icc_p_wr2_b 6.212e-04
icc_p_wr3_b 6.212e-04
icc_p_wr4_b 6.212e-04
icc_p_wr5_b 6.212e-04
icc_p_wr6_b 6.213e-04
icc_p_wr7_b 6.213e-04
icc_c_desela 0.000e+00
icc_p_desela 4.150e-05
icc_c_deselb 0.000e+00
icc_p_deselb 9.250e-05
icc_c_peak 1.25799
icc_p_peak 5.123099
icc_c_inrush 0.896377
icc_p_inrush 4.158242

13667
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.lib Normal file
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5288
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_ss_0p81v_0p81v_m40c.ps Normal file
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162
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Mon Nov 11 11:59:23 2019
#
# Instance Options:
# Instance Name: rf2_32x19_wm0
# Number of Words: 32
# Number of Bits: 19
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: off
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_32x19_wm0 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 669
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.9 0.9
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 5.98446e-05nF
VDDPE VSSE 1.30733e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 1.43021mA
VDDPE VSSE 1.70642mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 6.58291e-05nF
VDDPE VSSE 7.54664e-04nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 1.57323mA
VDDPE VSSE 7.73124mA
}
Cpd avm_read_write {
VDDCE VSSE 7.64447e-05nF
VDDPE VSSE 1.56253e-03nF
}
PEAK_I avm_read_write {
VDDCE VSSE 2.11022mA
VDDPE VSSE 10.03899mA
}
Cpd avm_read_desel {
VDDCE VSSE 3.33525e-05nF
VDDPE VSSE 7.72578e-04nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 1.06661mA
VDDPE VSSE 6.66464mA
}
Cpd avm_desel_write {
VDDCE VSSE 4.30921e-05nF
VDDPE VSSE 7.89953e-04nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 1.03387mA
VDDPE VSSE 6.82145mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.40553e-06nF
VDDPE VSSE 2.14259e-03nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.27129mA
VDDPE VSSE 6.93612mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.40553e-06nF
VDDPE VSSE 2.14259e-03nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.27129mA
VDDPE VSSE 6.93612mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.77000e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.96666e-05nF
}
LEAKAGE_I {
VDDCE VSSE 3.86400e-04mA
VDDPE VSSE 2.12300e-03mA
}
tsu 0.126538ns
ck2q_delay 0.353328ns
tr_q 0.0186942ns
tf_q 0.0218482ns
CHARACTERIZATION_MODE accurate
}

322
models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_tt_0p90v_0p90v_25c.dat Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Mon Nov 11 11:59:43 2019
#
# Instance Options:
# Instance Name: rf2_32x19_wm0
# Number of Words: 32
# Number of Bits: 19
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: off
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name tt_0p90v_0p90v_25c
S N
geomx 21.1650
geomy 100.9400
volt 0.9000
temp 25.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.1187
ttcenacenya 0.1176
ttenacenyapu 0.1613
ttenacenyanu 0.1884
tdftrambypcenya 0.1213
taaaya 0.1038
ttaaaya 0.1082
ttenaayapu 0.1878
ttenaayanu 0.1834
tdftrambypaya 0.1113
tcenbcenyb 0.1195
ttcenbcenyb 0.1185
ttenbcenybpu 0.1658
ttenbcenybnu 0.2026
tdftrambypcenyb 0.1187
tabayb 0.1040
ttabayb 0.1062
ttenbaybpu 0.2038
ttenbaybnu 0.1937
tdftrambypayb 0.1118
taccqa_rd0 0.3506
taccqa_rd1 0.3517
taccqa_rd2 0.3527
taccqa_rd3 0.3533
taccqa_rd4 0.4111
taccqa_rd5 0.4628
taccqa_rd6 0.5189
taccqa_rd7 0.5701
taccqa_scan0 0.3506
taccqa_scan1 0.3517
taccqa_scan2 0.3527
taccqa_scan3 0.3533
taccqa_scan4 0.4111
taccqa_scan5 0.4628
taccqa_scan6 0.5189
taccqa_scan7 0.5701
tclkasoa_rd0 0.3843
tclkasoa_rd1 0.3853
tclkasoa_rd2 0.3863
tclkasoa_rd3 0.3870
tclkasoa_rd4 0.4447
tclkasoa_rd5 0.4965
tclkasoa_rd6 0.5526
tclkasoa_rd7 0.6037
tclkasoa_scan0 0.3843
tclkasoa_scan1 0.3853
tclkasoa_scan2 0.3863
tclkasoa_scan3 0.3870
tclkasoa_scan4 0.4447
tclkasoa_scan5 0.4965
tclkasoa_scan6 0.5526
tclkasoa_scan7 0.6037
tclkbsob 0.2155
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 2.0800
kload_aya 1.6620
kload_cenyb 1.9640
kload_ayb 1.6740
kload_qa 0.6365
kload_soa 1.7020
kload_sob 1.8420
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.4965
tcyca_ema1 0.4976
tcyca_ema2 0.4986
tcyca_ema3 0.4992
tcyca_ema4 0.5578
tcyca_ema5 0.6103
tcyca_ema6 0.6673
tcyca_ema7 0.7193
tcycb_ema0 0.5696
tcycb_ema1 0.5756
tcycb_ema2 0.5818
tcycb_ema3 0.5909
tcycb_ema4 0.6613
tcycb_ema5 0.7136
tcycb_ema6 0.7812
tcycb_ema7 0.8325
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.2328
tcracwb_rd1 0.2338
tcracwb_rd2 0.2348
tcracwb_rd3 0.2355
tcracwb_rd4 0.2932
tcracwb_rd5 0.3449
tcracwb_rd6 0.4011
tcracwb_rd7 0.4522
tcwbcra_wr0 0.3248
tcwbcra_wr1 0.3307
tcwbcra_wr2 0.3369
tcwbcra_wr3 0.3458
tcwbcra_wr4 0.4152
tcwbcra_wr5 0.4667
tcwbcra_wr6 0.5333
tcwbcra_wr7 0.5838
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.1133
tckal 0.1131
tckbh 0.1159
tckbl 0.1128
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.1176
taas 0.1265
tcenbs 0.1240
tabs 0.1337
tdbs 0.0714
temaas 0.5390
temasas 0.5390
temabs 0.6306
ttenas 0.2339
ttcenas 0.1176
ttaas 0.1310
ttenbs 0.3090
ttcenbs 0.1252
ttabs 0.1373
ttdbs 0.0737
tsias 0.2573
tseas 0.2573
tdftrambypas 0.2083
tdftrambypbs 0.2083
tsibs 0.0714
tsebs 0.3090
tcolldisnas 0.5390
tcolldisnbs 0.6306
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0489
tcenaf_ret1nfh 0.6340
tcenaf_ret1nrh 0.3362
taah 0.0821
tcenbh 0.0492
tcenbf_ret1nfh 0.6340
tcenbf_ret1nrh 0.3362
tabh 0.0765
tdbh 0.1126
temaah 0.8454
temasah 0.8454
temabh 0.8756
ttenah 0.0903
ttcenah 0.0517
ttcenaf_ret1nfh 0.6340
ttcenaf_ret1nrh 0.3362
ttaah 0.0821
ttenbh 0.1239
ttcenbh 0.0507
ttcenbf_ret1nfh 0.6340
ttcenbf_ret1nrh 0.3362
ttabh 0.0765
ttdbh 0.1126
tret1nf_dftrambypfh 0.0313
tret1nr_dftrambypfh 0.6340
tret1nf_cenbrh 0.0313
tret1nf_cenarh 0.0294
tret1nf_tcenarh 0.0294
tret1nf_tcenbrh 0.0313
tret1nr_tcenbrh 0.6340
tret1nr_tcenarh 0.5424
tret1nr_cenbrh 0.6340
tret1nr_cenarh 0.5424
tsiah 0.0817
tseah 0.8454
tdftrambypah 0.8454
tdftrambypbh 0.6340
tdftrambypr_ret1nfh 0.6340
tdftrambypr_ret1nrh 0.3362
tsibh 0.1126
tsebh 0.1239
tcolldisnah 0.8454
tcolldisnbh 0.8756
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0091
icap_cena 0.0013
icap_aa 0.0016
icap_clkb 0.0097
icap_cenb 0.0013
icap_ab 0.0016
icap_db 0.0019
icap_emaa 0.0058
icap_emasa 0.0025
icap_emab 0.0056
icap_tena 0.0009
icap_tcena 0.0014
icap_taa 0.0015
icap_tenb 0.0010
icap_tcenb 0.0014
icap_tab 0.0016
icap_tdb 0.0016
icap_sia 0.0012
icap_sea 0.0016
icap_dftrambyp 0.0021
icap_sib 0.0058
icap_seb 0.0019
icap_colldisn 0.0021
icap_ret1n 0.0034
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 3.864e-04
icc_standby_p_chipdisable 2.123e-03
icc_standby_c_ret1 3.727e-04
icc_standby_p_ret1 1.273e-04
icc_standby_c_selective_precharge 3.566e-04
icc_standby_p_selective_precharge 2.022e-03
icc_c_rd0_a 2.999e-05
icc_c_rd1_a 3.000e-05
icc_c_rd2_a 3.000e-05
icc_c_rd3_a 3.002e-05
icc_c_rd4_a 3.019e-05
icc_c_rd5_a 3.019e-05
icc_c_rd6_a 3.019e-05
icc_c_rd7_a 3.028e-05
icc_p_rd0_a 6.947e-04
icc_p_rd1_a 6.947e-04
icc_p_rd2_a 6.953e-04
icc_p_rd3_a 6.953e-04
icc_p_rd4_a 6.965e-04
icc_p_rd5_a 6.968e-04
icc_p_rd6_a 6.972e-04
icc_p_rd7_a 6.990e-04
icc_c_wr0_b 3.875e-05
icc_c_wr1_b 3.877e-05
icc_c_wr2_b 3.877e-05
icc_c_wr3_b 3.878e-05
icc_c_wr4_b 3.896e-05
icc_c_wr5_b 3.896e-05
icc_c_wr6_b 3.896e-05
icc_c_wr7_b 3.904e-05
icc_p_wr0_b 7.104e-04
icc_p_wr1_b 7.104e-04
icc_p_wr2_b 7.110e-04
icc_p_wr3_b 7.110e-04
icc_p_wr4_b 7.122e-04
icc_p_wr5_b 7.125e-04
icc_p_wr6_b 7.128e-04
icc_p_wr7_b 7.146e-04
icc_c_desela 0.000e+00
icc_p_desela 4.837e-05
icc_c_deselb 0.000e+00
icc_p_deselb 1.066e-04
icc_c_peak 2.110219
icc_p_peak 10.038987
icc_c_inrush 1.662267
icc_p_inrush 7.731237

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