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Quartus + GPR evaluation

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This commit is contained in:
felsabbagh3 2019-09-10 20:23:01 -04:00
parent 4e8da1811a
commit 8d143d7739
68 changed files with 5345 additions and 3066 deletions
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kernel/vortex_test.elf
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2
kernel/vx_main.c
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@ -36,7 +36,7 @@ int main()
initialize_mats();
// matrix multiplication
// // matrix multiplication
// vx_sq_mat_mult(x, y, z, MAT_DIM);
// vx_print_str("\n\nMatrix multiplication\n");
// print_matrix(z);

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rtl/.DS_Store vendored
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0
rtl/interfaces/._VX_forward_csr_response_inter.sv → rtl/._VX_gpr_syn.v
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2
rtl/Makefile
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@ -3,7 +3,7 @@ all: RUNFILE
VERILATOR:
verilator --compiler gcc -Wall -cc Vortex.v -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
verilator --compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVortex.mk)

103
rtl/VX_decode.v
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@ -21,7 +21,7 @@ module VX_decode(
// Outputs
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
VX_warp_ctl_inter VX_warp_ctl,
output reg out_clone_stall,
output reg out_gpr_stall,
output reg out_branch_stall
);
@ -98,81 +98,42 @@ module VX_decode(
assign VX_fwd_req_de.src2 = VX_frE_to_bckE_req.rs2;
assign VX_fwd_req_de.warp_num = VX_frE_to_bckE_req.warp_num;
`ifdef ONLY
wire[31:0] glob_a_reg_data[`NT_M1:0];
wire[31:0] glob_b_reg_data[`NT_M1:0];
reg glob_clone_stall;
VX_gpr_read_inter VX_gpr_read();
assign VX_gpr_read.rs1 = VX_frE_to_bckE_req.rs1;
assign VX_gpr_read.rs2 = VX_frE_to_bckE_req.rs2;
assign VX_gpr_read.warp_num = VX_frE_to_bckE_req.warp_num;
wire curr_warp_zero = in_warp_num == 0;
wire context_zero_valid = (in_wb_warp_num == 0);
wire real_zero_isclone = is_clone && (in_warp_num == 0);
VX_context VX_Context_zero(
.clk (clk),
.in_warp (curr_warp_zero),
.in_wb_warp (context_zero_valid),
.in_valid (in_wb_valid),
.in_rd (VX_writeback_inter.rd),
.in_src1 (VX_frE_to_bckE_req.rs1),
.in_src2 (VX_frE_to_bckE_req.rs2),
.in_curr_PC (in_curr_PC),
.in_is_clone (real_zero_isclone),
.in_is_jal (is_jal),
.in_src1_fwd (in_src1_fwd),
.in_src1_fwd_data (in_src1_fwd_data),
.in_src2_fwd (in_src2_fwd),
.in_src2_fwd_data (in_src2_fwd_data),
.in_write_register(write_register),
.in_write_data (in_write_data),
.out_a_reg_data (glob_a_reg_data),
.out_b_reg_data (glob_b_reg_data),
.out_clone_stall (glob_clone_stall),
.w0_t0_registers (w0_t0_registers)
VX_gpr_jal_inter VX_gpr_jal();
assign VX_gpr_jal.is_jal = is_jal;
assign VX_gpr_jal.curr_PC = in_curr_PC;
VX_gpr_clone_inter VX_gpr_clone();
assign VX_gpr_clone.is_clone = is_clone;
assign VX_gpr_clone.warp_num = VX_frE_to_bckE_req.warp_num;
VX_gpr_wspawn_inter VX_gpr_wspawn();
assign VX_gpr_wspawn.is_wspawn = is_wspawn;
assign VX_gpr_wspawn.which_wspawn = in_which_wspawn;
// assign VX_gpr_wspawn.warp_num = VX_frE_to_bckE_req.warp_num;
VX_gpr_wrapper vx_grp_wrapper(
.clk (clk),
.VX_writeback_inter(VX_writeback_inter),
.VX_fwd_rsp (VX_fwd_rsp),
.VX_gpr_read (VX_gpr_read),
.VX_gpr_jal (VX_gpr_jal),
.VX_gpr_clone (VX_gpr_clone),
.VX_gpr_wspawn (VX_gpr_wspawn),
.out_a_reg_data (VX_frE_to_bckE_req.a_reg_data),
.out_b_reg_data (VX_frE_to_bckE_req.b_reg_data),
.out_gpr_stall(out_gpr_stall)
);
assign VX_frE_to_bckE_req.a_reg_data = glob_a_reg_data;
assign VX_frE_to_bckE_req.b_reg_data = glob_b_reg_data;
assign out_clone_stall = glob_clone_stall;
`else
VX_gpr_read_inter VX_gpr_read();
assign VX_gpr_read.rs1 = VX_frE_to_bckE_req.rs1;
assign VX_gpr_read.rs2 = VX_frE_to_bckE_req.rs2;
assign VX_gpr_read.warp_num = VX_frE_to_bckE_req.warp_num;
VX_gpr_jal_inter VX_gpr_jal();
assign VX_gpr_jal.is_jal = is_jal;
assign VX_gpr_jal.curr_PC = in_curr_PC;
VX_gpr_clone_inter VX_gpr_clone();
assign VX_gpr_clone.is_clone = is_clone;
assign VX_gpr_clone.warp_num = VX_frE_to_bckE_req.warp_num;
VX_gpr_wspawn_inter VX_gpr_wspawn();
assign VX_gpr_wspawn.is_wspawn = is_wspawn;
assign VX_gpr_wspawn.which_wspawn = in_which_wspawn;
// assign VX_gpr_wspawn.warp_num = VX_frE_to_bckE_req.warp_num;
VX_gpr_wrapper vx_grp_wrapper(
.clk (clk),
.VX_writeback_inter(VX_writeback_inter),
.VX_fwd_rsp (VX_fwd_rsp),
.VX_gpr_read (VX_gpr_read),
.VX_gpr_jal (VX_gpr_jal),
.VX_gpr_clone (VX_gpr_clone),
.VX_gpr_wspawn (VX_gpr_wspawn),
.out_a_reg_data (VX_frE_to_bckE_req.a_reg_data),
.out_b_reg_data (VX_frE_to_bckE_req.b_reg_data),
.out_clone_stall(out_clone_stall)
);
`endif

61
rtl/VX_fetch.v
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@ -8,7 +8,7 @@ module VX_fetch (
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_gpr_stall,
VX_icache_response_inter icache_response,
VX_icache_request_inter icache_request,
@ -31,10 +31,10 @@ module VX_fetch (
wire in_freeze = out_delay || in_memory_delay;
wire in_thread_mask[`NT_M1:0];
// wire in_thread_mask[`NT_M1:0];
genvar ind;
for (ind = 0; ind <= `NT_M1; ind = ind + 1) assign in_thread_mask[ind] = VX_warp_ctl.thread_mask[ind];
// genvar ind;
// for (ind = 0; ind <= `NT_M1; ind = ind + 1) assign in_thread_mask[ind] = VX_warp_ctl.thread_mask[ind];
@ -62,17 +62,12 @@ module VX_fetch (
// end
// end
wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
wire add_warp = in_wspawn && !in_ebreak && !in_gpr_stall;
wire remove_warp = in_ebreak && !in_wspawn && !in_gpr_stall;
always @(posedge clk or posedge reset) begin
if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
warp_num <= 0;
`ifndef ONLY
end else if (!warp_glob_valid[warp_num+1]) begin
// $display("Skipping one");
warp_num <= warp_num + 2;
`endif
end else begin
warp_num <= warp_num + 1;
end
@ -94,45 +89,16 @@ module VX_fetch (
assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_freeze;
assign stall = in_gpr_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_freeze;
assign out_which_wspawn = (warp_state+1);
`ifdef ONLY
// wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
// wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
// wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
// wire warp_zero_stall = stall || (warp_num != 0);
// wire warp_zero_wspawn = (0 == 0) ? 0 : (in_wspawn && ((warp_state+1) == 0));
// wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
// wire warp_zero_remove = remove_warp && (in_decode_warp_num == 0);
// // always @(*) begin : proc_
// // if (warp_zero_remove) $display("4Removing warp: %h", 0);
// // end
// VX_warp VX_Warp(
// .clk (clk),
// .reset (reset),
// .stall (warp_zero_stall),
// .remove (warp_zero_remove),
// .in_thread_mask(in_thread_mask),
// .in_change_mask(warp_zero_change_mask),
// .in_jal (warp_zero_jal),
// .in_jal_dest (in_jal_dest),
// .in_branch_dir (warp_zero_branch),
// .in_branch_dest(in_branch_dest),
// .in_wspawn (warp_zero_wspawn),
// .in_wspawn_pc (warp_zero_wspawn_pc),
// .out_PC (out_PC),
// .out_valid (out_valid)
// );
`else
wire[31:0] warp_glob_pc[`NW-1:0];
wire warp_glob_valid[`NW-1:0][`NT_M1:0];
wire[`NW-1:0][31:0] warp_glob_pc;
wire[`NW-1:0][`NT_M1:0] warp_glob_valid;
genvar cur_warp;
generate
for (cur_warp = 0; cur_warp < `NW; cur_warp = cur_warp + 1)
@ -145,16 +111,12 @@ module VX_fetch (
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
// always @(*) begin : proc_
// if (warp_zero_remove) $display("4Removing warp: %h", cur_warp);
// end
VX_warp VX_Warp(
.clk (clk),
.reset (reset),
.stall (warp_zero_stall),
.remove (warp_zero_remove),
.in_thread_mask(in_thread_mask),
.in_thread_mask(VX_warp_ctl.thread_mask),
.in_change_mask(warp_zero_change_mask),
.in_jal (warp_zero_jal),
.in_jal_dest (VX_jal_rsp.jal_dest),
@ -169,8 +131,9 @@ module VX_fetch (
endgenerate
reg[31:0] out_PC_var;
reg out_valid_var[`NT_M1:0];
reg[`NT_M1:0] out_valid_var;
always @(*) begin : help
integer g;

10
rtl/VX_front_end.v
View file

@ -38,7 +38,7 @@ VX_inst_meta_inter fd_inst_meta_de();
// From decode
wire decode_branch_stall;
wire decode_clone_stall;
wire decode_gpr_stall;
wire total_freeze = memory_delay || fetch_delay;
@ -51,7 +51,7 @@ VX_fetch vx_fetch(
.in_branch_stall (decode_branch_stall),
.in_fwd_stall (forwarding_fwd_stall),
.in_branch_stall_exe(execute_branch_stall),
.in_clone_stall (decode_clone_stall),
.in_gpr_stall (decode_gpr_stall),
.VX_jal_rsp (VX_jal_rsp),
.icache_response (icache_response_fe),
.VX_warp_ctl (VX_warp_ctl),
@ -69,7 +69,7 @@ VX_f_d_reg vx_f_d_reg(
.reset (reset),
.in_fwd_stall (forwarding_fwd_stall),
.in_freeze (total_freeze),
.in_clone_stall (decode_clone_stall),
.in_gpr_stall (decode_gpr_stall),
.fe_inst_meta_fd(fe_inst_meta_fd),
.fd_inst_meta_de(fd_inst_meta_de)
);
@ -85,7 +85,7 @@ VX_decode vx_decode(
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_fwd_req_de (VX_fwd_req_de),
.VX_warp_ctl (VX_warp_ctl),
.out_clone_stall (decode_clone_stall),
.out_gpr_stall (decode_gpr_stall),
.out_branch_stall (decode_branch_stall)
);
@ -96,7 +96,7 @@ VX_d_e_reg vx_d_e_reg(
.in_fwd_stall (forwarding_fwd_stall),
.in_branch_stall(execute_branch_stall),
.in_freeze (total_freeze),
.in_clone_stall (decode_clone_stall),
.in_gpr_stall (decode_gpr_stall),
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_bckE_req (VX_bckE_req)
);

72
rtl/VX_gpr.v
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@ -4,7 +4,6 @@
module VX_gpr (
input wire clk,
input wire valid_write_request,
input wire valid_read_request,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
@ -20,23 +19,60 @@ module VX_gpr (
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
// assign read_enable = valid_request;
genvar thread_index;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
if (VX_writeback_inter.wb_valid[thread_index]) begin
gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
end
end
end
end
// // Using Registers
// integer thread_index;
// always_ff@(posedge clk)
// begin
// if (write_enable) begin
// for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
// if (VX_writeback_inter.wb_valid[thread_index]) begin
// gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
// end
// end
// end
// out_a_reg_data <= gpr[VX_gpr_read.rs1];
// out_b_reg_data <= gpr[VX_gpr_read.rs2];
// end
// USING RAM blocks
// First RAM
integer thread_index_1;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index_1 = 0; thread_index_1 <= `NT_M1; thread_index_1 = thread_index_1 + 1) begin
if (VX_writeback_inter.wb_valid[thread_index_1]) begin
gpr[VX_writeback_inter.rd][thread_index_1] <= VX_writeback_inter.write_data[thread_index_1];
end
end
end
end
always @(negedge clk) begin
out_a_reg_data <= gpr[VX_gpr_read.rs1];
end
// Second RAM
integer thread_index_2;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index_2 = 0; thread_index_2 <= `NT_M1; thread_index_2 = thread_index_2 + 1) begin
if (VX_writeback_inter.wb_valid[thread_index_2]) begin
gpr[VX_writeback_inter.rd][thread_index_2] <= VX_writeback_inter.write_data[thread_index_2];
end
end
end
end
always @(negedge clk) begin
out_b_reg_data <= gpr[VX_gpr_read.rs2];
end
always @(negedge clk) begin
if (valid_read_request) begin
out_a_reg_data <= gpr[VX_gpr_read.rs1];
out_b_reg_data <= gpr[VX_gpr_read.rs2];
end
end
endmodule

173
rtl/VX_gpr_syn.v Normal file
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@ -0,0 +1,173 @@
`include "VX_define.v"
module VX_gpr_syn (
input wire clk,
// VX_gpr_read_inter VX_gpr_read,
// VX_wb_inter VX_writeback_inter,
// VX_forward_response_inter VX_fwd_rsp,
// VX_gpr_jal_inter VX_gpr_jal,
// VX_gpr_clone_inter VX_gpr_clone,
// VX_gpr_wspawn_inter VX_gpr_wspawn,
////////////////////////////////
input wire[4:0] rs1,
input wire[4:0] rs2,
input wire[`NW_M1:0] warp_num,
input wire[`NT_M1:0][31:0] write_data,
input wire[4:0] rd,
input wire[1:0] wb,
input wire[`NT_M1:0] wb_valid,
input wire[`NW_M1:0] wb_warp_num,
/////////
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data,
output wire out_gpr_stall
);
VX_gpr_read_inter VX_gpr_read();
assign VX_gpr_read.rs1 = rs1;
assign VX_gpr_read.rs2 = rs2;
assign VX_gpr_read.warp_num = warp_num;
VX_wb_inter VX_writeback_inter();
assign VX_writeback_inter.write_data = write_data;
assign VX_writeback_inter.rd = rd;
assign VX_writeback_inter.wb = wb;
assign VX_writeback_inter.wb_valid = wb_valid;
assign VX_writeback_inter.wb_warp_num = wb_warp_num;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
// wire[`NT_M1:0][31:0] jal_data;
// genvar index;
// for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
// assign out_a_reg_data = VX_gpr_jal.is_jal ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num];
// assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num];
// wire[31:0][31:0] w0_t0_registers;
// wire[`NW-1:0] temp_clone_stall;
// assign out_gpr_stall = (|temp_clone_stall);
// wire curr_warp_zero = VX_gpr_read.warp_num == 0;
// wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
// wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
// wire write_register = (VX_writeback_inter.wb != 2'h0) ? (1'b1) : (1'b0);
// VX_context VX_Context_zero(
// .clk (clk),
// .in_warp (curr_warp_zero),
// .in_wb_warp (context_zero_valid),
// .in_valid (VX_writeback_inter.wb_valid),
// .in_rd (VX_writeback_inter.rd),
// .in_src1 (VX_gpr_read.rs1),
// .in_src2 (VX_gpr_read.rs2),
// .in_is_clone (real_zero_isclone),
// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
// .in_write_register(write_register),
// .in_write_data (VX_writeback_inter.write_data),
// .out_a_reg_data (temp_a_reg_data[0]),
// .out_b_reg_data (temp_b_reg_data[0]),
// .out_clone_stall (temp_clone_stall[0]),
// .w0_t0_registers (w0_t0_registers)
// );
// genvar r;
// generate
// for (r = 1; r < `NW; r = r + 1) begin
// wire context_glob_valid = (VX_writeback_inter.wb_warp_num == r);
// wire curr_warp_glob = VX_gpr_read.warp_num == r;
// wire real_wspawn = VX_gpr_wspawn.is_wspawn && (VX_gpr_wspawn.which_wspawn == r);
// wire real_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == r);
// VX_context_slave VX_Context_one(
// .clk (clk),
// .in_warp (curr_warp_glob),
// .in_wb_warp (context_glob_valid),
// .in_valid (VX_writeback_inter.wb_valid),
// .in_rd (VX_writeback_inter.rd),
// .in_src1 (VX_gpr_read.rs1),
// .in_src2 (VX_gpr_read.rs2),
// .in_is_clone (real_isclone),
// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
// .in_write_register(write_register),
// .in_write_data (VX_writeback_inter.write_data),
// .in_wspawn_regs (w0_t0_registers),
// .in_wspawn (real_wspawn),
// .out_a_reg_data (temp_a_reg_data[r]),
// .out_b_reg_data (temp_b_reg_data[r]),
// .out_clone_stall (temp_clone_stall[r])
// );
// end
// endgenerate
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
assign out_a_reg_data = temp_a_reg_data[VX_gpr_read.warp_num];
assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num];
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
VX_gpr vx_gpr(
.clk (clk),
.valid_write_request(valid_write_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data[warp_index]),
.out_b_reg_data (temp_b_reg_data[warp_index])
);
end
endgenerate
assign out_gpr_stall = 0;
// // WSPAWN FSM
// reg[3:0] wspawn_state;
// VX_gpr_read_inter VX_wspawn_gpr_read();
// VX_wb_inter VX_wspawn_wb_inter();
// VX_wspawn_gpr_read.rs1
// always @(posedge clk) begin
// if ((in_wspawn) && wspawn_state == 0) begin
// wspawn_state <= 10;
// end else if (wspawn_state == 1) begin
// wspawn_state <= 0;
// end else if (wspawn_state > 0) begin
// wspawn_state <= wspawn_state - 1;
// end
// end
// assign out_gpr_stall = ((wspawn_state == 0) && VX_gpr_wspawn.is_wspawn) || (VX_gpr_wspawn.is_wspawn > 1);;
endmodule

104
rtl/VX_gpr_wrapper.v
View file

@ -12,50 +12,29 @@ module VX_gpr_wrapper (
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data,
output wire out_clone_stall
output wire out_gpr_stall
);
wire[`NT_M1:0][31:0] temp_a_reg_data;
wire[`NT_M1:0][31:0] temp_b_reg_data;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] jal_data;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
// wire[`NT_M1:0][31:0] jal_data;
// genvar index;
// for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data));
assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data);
wire[`NW-1:0] temp_clone_stall = 0;
assign out_clone_stall = (|temp_clone_stall);
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
wire valid_read_request = warp_index == VX_gpr_read.warp_num;
VX_gpr vx_gpr(
.clk (clk),
.valid_write_request(valid_write_request),
.valid_read_request (valid_read_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data),
.out_b_reg_data (temp_b_reg_data)
);
end
endgenerate
// assign out_a_reg_data = VX_gpr_jal.is_jal ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num];
// assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num];
// wire[31:0][31:0] w0_t0_registers;
// wire[`NW-1:0] temp_clone_stall;
// assign out_gpr_stall = (|temp_clone_stall);
// wire curr_warp_zero = VX_gpr_read.warp_num == 0;
// wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
// wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
@ -114,4 +93,59 @@ module VX_gpr_wrapper (
// end
// endgenerate
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] jal_data;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data[VX_gpr_read.warp_num]));
assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data[VX_gpr_read.warp_num]);
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
VX_gpr vx_gpr(
.clk (clk),
.valid_write_request(valid_write_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data[warp_index]),
.out_b_reg_data (temp_b_reg_data[warp_index])
);
end
endgenerate
assign out_gpr_stall = 0;
// // WSPAWN FSM
// reg[3:0] wspawn_state;
// VX_gpr_read_inter VX_wspawn_gpr_read();
// VX_wb_inter VX_wspawn_wb_inter();
// VX_wspawn_gpr_read.rs1
// always @(posedge clk) begin
// if ((in_wspawn) && wspawn_state == 0) begin
// wspawn_state <= 10;
// end else if (wspawn_state == 1) begin
// wspawn_state <= 0;
// end else if (wspawn_state > 0) begin
// wspawn_state <= wspawn_state - 1;
// end
// end
// assign out_gpr_stall = ((wspawn_state == 0) && VX_gpr_wspawn.is_wspawn) || (VX_gpr_wspawn.is_wspawn > 1);;
endmodule

38
rtl/VX_shared_memory.v
View file

@ -1,38 +0,0 @@
`include "VX_define.v"
// Old SM file
module VX_shared_memory(
input wire clk,
input wire[31:0] in_address[`NT_M1:0],
input wire[2:0] in_mem_read,
input wire[2:0] in_mem_write,
input wire in_valid[`NT_M1:0],
input wire[31:0] in_data[`NT_M1:0],
output reg[31:0] out_data[`NT_M1:0]
);
reg[31:0] mem[255:0]; // 2^2 * 2^8 = 2^10 = 1kb of memory
always @(posedge clk)
begin
if ((in_mem_write == `SW_MEM_WRITE) && in_valid)
begin
mem[in_address[0][9:2]] <= in_data;
end
if (in_mem_read == `LW_MEM_READ)
begin
assign out_data[0] = mem[in_address[0][9:2]];
end
end
endmodule // VX_shared_memory

8
rtl/VX_warp.v
View file

@ -6,7 +6,7 @@ module VX_warp (
input wire reset,
input wire stall,
input wire remove,
input wire in_thread_mask[`NT_M1:0],
input wire[`NT_M1:0] in_thread_mask,
input wire in_change_mask,
input wire in_jal,
input wire[31:0] in_jal_dest,
@ -16,15 +16,15 @@ module VX_warp (
input wire[31:0] in_wspawn_pc,
output wire[31:0] out_PC,
output wire out_valid[`NT_M1:0]
output wire[`NT_M1:0] out_valid
);
reg[31:0] real_PC;
var[31:0] temp_PC;
var[31:0] use_PC;
reg valid[`NT_M1:0];
reg[`NT_M1:0] valid;
reg valid_zero[`NT_M1:0];
reg[`NT_M1:0] valid_zero;
integer ini_cur_th = 0;
initial begin

30
rtl/Vortex.qpf
View file

@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
# Date created = 20:33:29 May 12, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.0"
DATE = "20:33:29 May 12, 2019"
# Revisions
PROJECT_REVISION = "Vortex"

0
rtl/interfaces/._VX_forward_mem_inter.sv → rtl/interfaces/._VX_forward_csr_response_inter.v
View file

0
rtl/interfaces/._VX_gpr_read_inter.sv → rtl/interfaces/._VX_forward_mem_inter.v
View file

BIN
rtl/interfaces/._VX_gpr_read_inter.v Normal file
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Binary file not shown.

15
rtl/interfaces/VX_branch_response_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_BRANCH_RSP
@ -11,19 +11,6 @@ interface VX_branch_response_inter ();
wire[31:0] branch_dest;
wire[`NW_M1:0] branch_warp_num;
// source-side view
modport snk (
input branch_dir,
input branch_dest
);
// source-side view
modport src (
output branch_dir,
output branch_dest
);
endinterface

17
rtl/interfaces/VX_csr_write_request_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_CSR_W_REQ
@ -11,21 +11,6 @@ interface VX_csr_write_request_inter ();
wire[11:0] csr_address;
wire[31:0] csr_result;
// source-side view
modport snk (
input is_csr,
input csr_address,
input csr_result
);
// source-side view
modport src (
output is_csr,
output csr_address,
output csr_result
);
endinterface

22
rtl/interfaces/VX_dcache_request_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_DCACHE_REQ
@ -13,26 +13,6 @@ interface VX_dcache_request_inter ();
wire out_cache_driver_in_valid[`NT_M1:0];
wire[31:0] out_cache_driver_in_data[`NT_M1:0];
// source-side view
modport snk (
input out_cache_driver_in_address,
input out_cache_driver_in_mem_read,
input out_cache_driver_in_mem_write,
input out_cache_driver_in_valid,
input out_cache_driver_in_data
);
// source-side view
modport src (
output out_cache_driver_in_address,
output out_cache_driver_in_mem_read,
output out_cache_driver_in_mem_write,
output out_cache_driver_in_valid,
output out_cache_driver_in_data
);
endinterface

14
rtl/interfaces/VX_dcache_response_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_DCACHE_RSP
@ -9,18 +9,6 @@ interface VX_dcache_response_inter ();
wire[31:0] in_cache_driver_out_data[`NT_M1:0];
// source-side view
modport snk (
input in_cache_driver_out_data
);
// source-side view
modport src (
output in_cache_driver_out_data
);
endinterface

32
rtl/interfaces/VX_forward_csr_response_inter.sv
View file

@ -1,32 +0,0 @@
`include "VX_define.v"
`ifndef VX_FWD_CSR_RSP
`define VX_FWD_CSR_RSP
interface VX_forward_csr_response_inter ();
/* verilator lint_off UNUSED */
wire csr_fwd;
wire[31:0] csr_fwd_data;
/* verilator lint_on UNUSED */
// source-side view
modport snk (
input csr_fwd,
input csr_fwd_data
);
// source-side view
modport src (
output csr_fwd,
output csr_fwd_data
);
endinterface
`endif

17
rtl/interfaces/VX_forward_csr_response_inter.v Normal file
View file

@ -0,0 +1,17 @@
`include "../VX_define.v"
`ifndef VX_FWD_CSR_RSP
`define VX_FWD_CSR_RSP
interface VX_forward_csr_response_inter ();
/* verilator lint_off UNUSED */
wire csr_fwd;
wire[31:0] csr_fwd_data;
/* verilator lint_on UNUSED */
endinterface
`endif

22
rtl/interfaces/VX_forward_exe_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_EXE
@ -13,26 +13,6 @@ interface VX_forward_exe_inter ();
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output PC_next,
output warp_num
);
endinterface

42
rtl/interfaces/VX_forward_mem_inter.sv
View file

@ -1,42 +0,0 @@
`include "VX_define.v"
`ifndef VX_FWD_MEM
`define VX_FWD_MEM
interface VX_forward_mem_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_data;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input mem_data,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output mem_data,
output PC_next,
output warp_num
);
endinterface
`endif

20
rtl/interfaces/VX_forward_mem_inter.v Normal file
View file

@ -0,0 +1,20 @@
`include "../VX_define.v"
`ifndef VX_FWD_MEM
`define VX_FWD_MEM
interface VX_forward_mem_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_data;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
endinterface
`endif

17
rtl/interfaces/VX_forward_reqeust_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_REQ
@ -11,21 +11,6 @@ interface VX_forward_reqeust_inter ();
wire[4:0] src2;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input src1,
input src2,
input warp_num
);
// source-side view
modport src (
output src1,
output src2,
output warp_num
);
endinterface

20
rtl/interfaces/VX_forward_response_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_RSP
@ -12,24 +12,6 @@ interface VX_forward_response_inter ();
wire[`NT_M1:0][31:0] src1_fwd_data;
wire[`NT_M1:0][31:0] src2_fwd_data;
// source-side view
modport snk (
input src1_fwd,
input src2_fwd,
input src1_fwd_data,
input src2_fwd_data
);
// source-side view
modport src (
output src1_fwd,
output src2_fwd,
output src1_fwd_data,
output src2_fwd_data
);
endinterface

23
rtl/interfaces/VX_forward_wb_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_WB
@ -14,27 +14,6 @@ interface VX_forward_wb_inter ();
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input mem_data,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output mem_data,
output PC_next,
output warp_num
);
endinterface

55
rtl/interfaces/VX_frE_to_bckE_req_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FrE_to_BE_INTER
@ -30,59 +30,6 @@ interface VX_frE_to_bckE_req_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input csr_address,
input is_csr,
input csr_mask,
input rd,
input rs1,
input rs2,
input a_reg_data,
input b_reg_data,
input alu_op,
input wb,
input rs2_src,
input itype_immed,
input mem_read,
input mem_write,
input branch_type,
input upper_immed,
input curr_PC,
input jal,
input jal_offset,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
output csr_address,
output is_csr,
output csr_mask,
output rd,
output rs1,
output rs2,
output a_reg_data,
output b_reg_data,
output alu_op,
output wb,
output rs2_src,
output itype_immed,
output mem_read,
output mem_write,
output branch_type,
output upper_immed,
output curr_PC,
output jal,
output jal_offset,
output PC_next,
output valid,
output warp_num
);
endinterface

23
rtl/interfaces/VX_gpr_clone_inter.v
View file

@ -1,27 +1,16 @@
`include "../VX_define.v"
`ifndef VX_GPR_CLONE_INTER
`define VX_GPR_CLONE_INTER
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
modport snk (
input is_clone,
input warp_num
);
modport src (
output is_clone,
output warp_num
);
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface

14
rtl/interfaces/VX_gpr_jal_inter.v
View file

@ -1,4 +1,4 @@
`include "../VX_define.v"
`ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER
@ -7,18 +7,6 @@
interface VX_gpr_jal_inter ();
wire is_jal;
wire[31:0] curr_PC;
modport snk (
input is_jal,
input curr_PC
);
modport src (
output is_jal,
output curr_PC
);
endinterface

2
rtl/interfaces/VX_gpr_read_inter.sv → rtl/interfaces/VX_gpr_read_inter.v
View file

@ -1,4 +1,4 @@
`include "../VX_define.v"
`ifndef VX_GPR_READ
`define VX_GPR_READ

14
rtl/interfaces/VX_gpr_wspawn_inter.v
View file

@ -1,4 +1,4 @@
`include "../VX_define.v"
`ifndef VX_GPR_WSPAWN_INTER
`define VX_GPR_WSPAWN_INTER
@ -11,18 +11,6 @@ interface VX_gpr_wspawn_inter ();
// wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
modport snk (
input is_wspawn,
input which_wspawn
);
modport src (
output is_wspawn,
output which_wspawn
);
endinterface

14
rtl/interfaces/VX_icache_request_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_ICACHE_REQ
@ -9,18 +9,6 @@ interface VX_icache_request_inter ();
wire[31:0] pc_address;
// source-side view
modport snk (
input pc_address
);
// source-side view
modport src (
output pc_address
);
endinterface

13
rtl/interfaces/VX_icache_response_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_ICACHE_RSP
@ -11,17 +11,6 @@ interface VX_icache_response_inter ();
// wire stall;
wire[31:0] instruction;
// source-side view
modport snk (
input instruction
);
// source-side view
modport src (
output instruction
);
endinterface

25
rtl/interfaces/VX_inst_mem_wb_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_MEM_WB_INST_INTER
@ -15,29 +15,6 @@ interface VX_inst_mem_wb_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
output alu_result,
output mem_result,
output rd,
output wb,
output PC_next,
output valid,
output warp_num
);
endinterface

18
rtl/interfaces/VX_inst_meta_inter.v
View file

@ -1,4 +1,4 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_F_D_INTER
@ -10,22 +10,6 @@ interface VX_inst_meta_inter ();
wire[`NW_M1:0] warp_num;
wire[`NT_M1:0] valid;
// source-side view
modport snk (
input instruction,
input inst_pc,
input warp_num,
input valid
);
// sink-side view
modport src (
output instruction,
output inst_pc,
output warp_num,
output valid
);
endinterface

20
rtl/interfaces/VX_jal_response_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_JAL_RSP
@ -10,23 +10,7 @@ interface VX_jal_response_inter ();
wire jal;
wire[31:0] jal_dest;
wire[`NW_M1:0] jal_warp_num;
// source-side view
modport snk (
input jal,
input jal_dest,
input jal_warp_num
);
// source-side view
modport src (
output jal,
output jal_dest,
output jal_warp_num
);
endinterface

43
rtl/interfaces/VX_mem_req_inter.v
View file

@ -1,3 +1,9 @@
`include "../VX_define.v"
`ifndef VX_MEM_REQ_IN
`define VX_MEM_REQ_IN
interface VX_mem_req_inter ();
wire[`NT_M1:0][31:0] alu_result;
@ -16,40 +22,7 @@ interface VX_mem_req_inter ();
wire[`NW_M1:0] warp_num;
modport snk (
input alu_result,
input mem_read,
input mem_write,
input rd,
input wb,
input rs1,
input rs2,
input rd2,
input PC_next,
input curr_PC,
input branch_offset,
input branch_type,
input valid,
input warp_num
);
endinterface
modport src (
output alu_result,
output mem_read,
output mem_write,
output rd,
output wb,
output rs1,
output rs2,
output rd2,
output PC_next,
output curr_PC,
output branch_offset,
output branch_type,
output valid,
output warp_num
);
endinterface
`endif

25
rtl/interfaces/VX_mw_wb_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_MW_WB_INTER
@ -15,29 +15,6 @@ interface VX_mw_wb_inter ();
wire[`NT_M1:0] valid;
wire [`NW_M1:0] warp_num;
// source-side view
modport snk (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
endinterface

23
rtl/interfaces/VX_warp_ctl_inter.v
View file

@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_WARP_CTL_INTER
@ -14,27 +14,6 @@ interface VX_warp_ctl_inter ();
wire[31:0] wspawn_pc;
wire ebreak;
// source-side view
modport snk (
input warp_num,
input change_mask,
input thread_mask,
input wspawn,
input wspawn_pc,
input ebreak
);
// source-side view
modport src (
output warp_num,
output change_mask,
output thread_mask,
output wspawn,
output wspawn_pc,
output ebreak
);
endinterface

20
rtl/interfaces/VX_wb_inter.v
View file

@ -1,3 +1,4 @@
`include "../VX_define.v"
`ifndef VX_WB_INTER
@ -12,25 +13,6 @@ interface VX_wb_inter ();
wire[`NT_M1:0] wb_valid;
wire[`NW_M1:0] wb_warp_num;
modport snk (
input write_data,
input rd,
input wb,
input wb_valid,
input wb_warp_num
);
modport src (
output write_data,
output rd,
output wb,
output wb_valid,
output wb_warp_num
);
endinterface

1695
rtl/obj_dir/VVX_gpr_syn.cpp Normal file
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129
rtl/obj_dir/VVX_gpr_syn.h Normal file
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@ -0,0 +1,129 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_gpr_syn_H_
#define _VVX_gpr_syn_H_
#include "verilated.h"
class VVX_gpr_syn__Syms;
//----------
VL_MODULE(VVX_gpr_syn) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(rs1,4,0);
VL_IN8(rs2,4,0);
VL_IN8(warp_num,3,0);
VL_IN8(rd,4,0);
VL_IN8(wb,1,0);
VL_IN8(wb_valid,3,0);
VL_IN8(wb_warp_num,3,0);
VL_OUT8(out_gpr_stall,0,0);
VL_INW(write_data,127,0,4);
VL_OUTW(out_a_reg_data,127,0,4);
VL_OUTW(out_b_reg_data,127,0,4);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIGW(VX_gpr_wrapper__DOT__temp_a_reg_data,1023,0,32);
VL_SIGW(VX_gpr_wrapper__DOT__temp_b_reg_data,1023,0,32);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_gpr_syn__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_gpr_syn); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_gpr_syn(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_gpr_syn();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_gpr_syn__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_gpr_syn__Syms* symsp, bool first);
private:
static QData _change_request(VVX_gpr_syn__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__4(VVX_gpr_syn__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(VVX_gpr_syn__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__1(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _sequent__TOP__2(VVX_gpr_syn__Syms* __restrict vlSymsp);
static void _settle__TOP__3(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

53
rtl/obj_dir/VVX_gpr_syn.mk Normal file
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@ -0,0 +1,53 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_gpr_syn.mk
default: VVX_gpr_syn__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_gpr_syn
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_gpr_syn
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include VVX_gpr_syn_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
rtl/obj_dir/VVX_gpr_syn__Syms.cpp Normal file
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@ -0,0 +1,19 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_gpr_syn__Syms.h"
#include "VVX_gpr_syn.h"
// FUNCTIONS
VVX_gpr_syn__Syms::VVX_gpr_syn__Syms(VVX_gpr_syn* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

35
rtl/obj_dir/VVX_gpr_syn__Syms.h Normal file
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@ -0,0 +1,35 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _VVX_gpr_syn__Syms_H_
#define _VVX_gpr_syn__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "VVX_gpr_syn.h"
// SYMS CLASS
class VVX_gpr_syn__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVX_gpr_syn* TOPp;
// CREATORS
VVX_gpr_syn__Syms(VVX_gpr_syn* topp, const char* namep);
~VVX_gpr_syn__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVX_gpr_syn__ver.d Normal file
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@ -0,0 +1 @@
obj_dir/VVX_gpr_syn.cpp obj_dir/VVX_gpr_syn.h obj_dir/VVX_gpr_syn.mk obj_dir/VVX_gpr_syn__Syms.cpp obj_dir/VVX_gpr_syn__Syms.h obj_dir/VVX_gpr_syn__ver.d obj_dir/VVX_gpr_syn_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_define.v VX_gpr.v VX_gpr_syn.v interfaces/../VX_define.v interfaces/VX_gpr_read_inter.v interfaces/VX_wb_inter.v

17
rtl/obj_dir/VVX_gpr_syn__verFiles.dat Normal file
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@ -0,0 +1,17 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "VX_gpr_syn.v -cc -Iinterfaces"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
S 1179 894272 1568146678 0 1568146678 0 "VX_gpr.v"
S 5776 894945 1568156400 0 1568156400 0 "VX_gpr_syn.v"
S 1676 1565244 1567474434 0 1567474434 0 "interfaces/../VX_define.v"
S 193 894834 1568154198 0 1568154198 0 "interfaces/VX_gpr_read_inter.v"
S 273 894835 1568154164 0 1568154164 0 "interfaces/VX_wb_inter.v"
T 103876 895616 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.cpp"
T 6427 894948 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.h"
T 1458 895150 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.mk"
T 550 894947 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__Syms.cpp"
T 789 894946 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__Syms.h"
T 363 895151 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__ver.d"
T 0 0 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__verFiles.dat"
T 1257 894949 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn_classes.mk"

40
rtl/obj_dir/VVX_gpr_syn_classes.mk Normal file
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@ -0,0 +1,40 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_gpr_syn.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
VM_TRACE_THREADED = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_gpr_syn \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_gpr_syn__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

BIN
rtl/obj_dir/VVortex
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4644
rtl/obj_dir/VVortex.cpp
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147
rtl/obj_dir/VVortex.h
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@ -71,22 +71,40 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_count,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__add_warp,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__remove_warp,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__warp_zero_stall,0,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_valid,31,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_valid_var,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_jalrs,0,0);
@ -108,6 +126,8 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_back_end__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
@ -118,28 +138,27 @@ VL_MODULE(VVortex) {
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__data_read,11,0);
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_pc,255,0,8);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_PC_var,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value,71,0,3);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__jal_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
@ -158,26 +177,6 @@ VL_MODULE(VVortex) {
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__in_thread_mask[4],0,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_pc[8],31,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_valid[8][4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_valid_var[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__in_valid[4],0,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
@ -192,6 +191,14 @@ VL_MODULE(VVortex) {
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
@ -201,6 +208,18 @@ VL_MODULE(VVortex) {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
@ -209,22 +228,6 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES

BIN
rtl/obj_dir/VVortex__ALL.a
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BIN
rtl/obj_dir/VVortex__ALLcls.o
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2
rtl/obj_dir/VVortex__ver.d
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@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.sv interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.sv interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v interfaces//../VX_define.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.v interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.v interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v

117
rtl/obj_dir/VVortex__verFiles.dat
View file

@ -1,72 +1,73 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -Wall -cc Vortex.v -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3"
C "--compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v"
S 2767 1703128 1567984522 0 1567984522 0 "VX_back_end.v"
S 1837 1768199 1567984564 0 1567984564 0 "VX_csr_handler.v"
S 13387 891321 1568075916 0 1568075916 0 "VX_decode.v"
S 12015 891625 1568083962 0 1568083962 0 "VX_decode.v"
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
S 3835 891130 1568052328 0 1568052328 0 "VX_execute.v"
S 6520 1598760 1567980382 0 1567980382 0 "VX_fetch.v"
S 5000 892191 1568138876 0 1568138876 0 "VX_fetch.v"
S 6148 1701713 1567982096 0 1567982096 0 "VX_forwarding.v"
S 2719 1701603 1567981038 0 1567981038 0 "VX_front_end.v"
S 2701 891626 1568084006 0 1568084006 0 "VX_front_end.v"
S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v"
S 1147 891129 1568081586 0 1568081586 0 "VX_gpr.v"
S 4212 891132 1568081646 0 1568081646 0 "VX_gpr_wrapper.v"
S 2099 895597 1568160868 0 1568160868 0 "VX_gpr.v"
S 5323 894943 1568156252 0 1568156252 0 "VX_gpr_wrapper.v"
S 2584 1768087 1567983338 0 1567983338 0 "VX_memory.v"
S 1915 1565256 1567474434 0 1567474434 0 "VX_warp.v"
S 1903 893490 1568138384 0 1568138384 0 "VX_warp.v"
S 1597 1704649 1567981924 0 1567981924 0 "VX_writeback.v"
S 4392 1703129 1567985238 0 1567985238 0 "Vortex.v"
S 389 1610834 1567980040 0 1567980040 0 "interfaces//VX_branch_response_inter.v"
S 407 890646 1568049566 0 1568049566 0 "interfaces//VX_csr_write_request_inter.v"
S 823 1703164 1567983106 0 1567983106 0 "interfaces//VX_dcache_request_inter.v"
S 334 1768090 1567983128 0 1567983128 0 "interfaces//VX_dcache_response_inter.v"
S 528 1573270 1567972030 0 1567972030 0 "interfaces//VX_forward_exe_inter.v"
S 610 1573271 1567971856 0 1567971856 0 "interfaces//VX_forward_mem_inter.sv"
S 377 1582724 1567978250 0 1567978250 0 "interfaces//VX_forward_reqeust_inter.v"
S 520 1573373 1567970758 0 1567970758 0 "interfaces//VX_forward_response_inter.v"
S 595 1573167 1567968126 0 1567968126 0 "interfaces//VX_forward_wb_inter.v"
S 1689 1571958 1567565366 0 1567565366 0 "interfaces//VX_frE_to_bckE_req_inter.v"
S 345 891319 1568075890 0 1568075890 0 "interfaces//VX_gpr_clone_inter.v"
S 256 891318 1568075982 0 1568075982 0 "interfaces//VX_gpr_jal_inter.v"
S 168 891192 1568075672 0 1568075672 0 "interfaces//VX_gpr_read_inter.sv"
S 392 891320 1568075898 0 1568075898 0 "interfaces//VX_gpr_wspawn_inter.v"
S 279 1578590 1567975102 0 1567975102 0 "interfaces//VX_icache_request_inter.v"
S 315 1578593 1567975152 0 1567975152 0 "interfaces//VX_icache_response_inter.v"
S 679 1573336 1567972210 0 1567972210 0 "interfaces//VX_inst_mem_wb_inter.v"
S 444 1571666 1567552516 0 1567552516 0 "interfaces//VX_inst_meta_inter.v"
S 392 1599286 1567980328 0 1567980328 0 "interfaces//VX_jal_response_inter.v"
S 995 1572568 1567701364 0 1567701364 0 "interfaces//VX_mem_req_inter.v"
S 654 1573355 1567969270 0 1567969270 0 "interfaces//VX_mw_wb_inter.v"
S 603 1571976 1567568452 0 1567568452 0 "interfaces//VX_warp_ctl_inter.v"
S 459 890638 1568049504 0 1568049504 0 "interfaces//VX_wb_inter.v"
T 664405 891161 1568081662 0 1568081662 0 "obj_dir/VVortex.cpp"
T 21432 891159 1568081662 0 1568081662 0 "obj_dir/VVortex.h"
T 1791 891296 1568081662 0 1568081662 0 "obj_dir/VVortex.mk"
T 914 891284 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 891283 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 891176 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 891173 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 891156 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 891154 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 1059 891282 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1142 891185 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 891292 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 891291 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 891288 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 891287 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 891290 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 891289 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 891286 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 891285 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 891294 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 891293 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 891142 1568081662 0 1568081662 0 "obj_dir/VVortex__Syms.cpp"
T 1855 891137 1568081662 0 1568081662 0 "obj_dir/VVortex__Syms.h"
T 2052 891297 1568081662 0 1568081662 0 "obj_dir/VVortex__ver.d"
T 0 0 1568081662 0 1568081662 0 "obj_dir/VVortex__verFiles.dat"
T 1530 891295 1568081662 0 1568081662 0 "obj_dir/VVortex_classes.mk"
S 6179 1572602 1567698562 0 1567698562 0 "pipe_regs//VX_d_e_reg.v"
S 1676 1565244 1567474434 0 1567474434 0 "interfaces//../VX_define.v"
S 227 894833 1568155500 0 1568155500 0 "interfaces//VX_branch_response_inter.v"
S 212 894856 1568154236 0 1568154236 0 "interfaces//VX_csr_write_request_inter.v"
S 373 894855 1568154234 0 1568154234 0 "interfaces//VX_dcache_request_inter.v"
S 186 894854 1568154230 0 1568154230 0 "interfaces//VX_dcache_response_inter.v"
S 282 894852 1568154224 0 1568154224 0 "interfaces//VX_forward_exe_inter.v"
S 327 894851 1568154222 0 1568154222 0 "interfaces//VX_forward_mem_inter.v"
S 204 894850 1568154218 0 1568154218 0 "interfaces//VX_forward_reqeust_inter.v"
S 273 894849 1568154216 0 1568154216 0 "interfaces//VX_forward_response_inter.v"
S 313 894848 1568154210 0 1568154210 0 "interfaces//VX_forward_wb_inter.v"
S 833 894847 1568154206 0 1568154206 0 "interfaces//VX_frE_to_bckE_req_inter.v"
S 253 894846 1568154204 0 1568154204 0 "interfaces//VX_gpr_clone_inter.v"
S 173 894845 1568154200 0 1568154200 0 "interfaces//VX_gpr_jal_inter.v"
S 193 894834 1568154198 0 1568154198 0 "interfaces//VX_gpr_read_inter.v"
S 293 894844 1568154194 0 1568154194 0 "interfaces//VX_gpr_wspawn_inter.v"
S 159 894843 1568154192 0 1568154192 0 "interfaces//VX_icache_request_inter.v"
S 194 894842 1568154188 0 1568154188 0 "interfaces//VX_icache_response_inter.v"
S 366 894841 1568154186 0 1568154186 0 "interfaces//VX_inst_mem_wb_inter.v"
S 237 894840 1568154182 0 1568154182 0 "interfaces//VX_inst_meta_inter.v"
S 205 894839 1568154180 0 1568154180 0 "interfaces//VX_jal_response_inter.v"
S 557 894838 1568154176 0 1568154176 0 "interfaces//VX_mem_req_inter.v"
S 348 894837 1568154174 0 1568154174 0 "interfaces//VX_mw_wb_inter.v"
S 297 894836 1568154170 0 1568154170 0 "interfaces//VX_warp_ctl_inter.v"
S 273 894835 1568154164 0 1568154164 0 "interfaces//VX_wb_inter.v"
T 768547 894861 1568160870 0 1568160870 0 "obj_dir/VVortex.cpp"
T 22072 894859 1568160870 0 1568160870 0 "obj_dir/VVortex.h"
T 1791 894923 1568160870 0 1568160870 0 "obj_dir/VVortex.mk"
T 914 894911 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 894910 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 894907 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 894906 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 894905 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 894904 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 1059 894909 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1142 894908 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 894919 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 894918 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 894915 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 894914 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 894917 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 894916 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 894913 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 894912 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 894921 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 894920 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 894858 1568160870 0 1568160870 0 "obj_dir/VVortex__Syms.cpp"
T 1855 894857 1568160870 0 1568160870 0 "obj_dir/VVortex__Syms.h"
T 2077 894924 1568160870 0 1568160870 0 "obj_dir/VVortex__ver.d"
T 0 0 1568160870 0 1568160870 0 "obj_dir/VVortex__verFiles.dat"
T 1530 894922 1568160870 0 1568160870 0 "obj_dir/VVortex_classes.mk"
S 1884 891629 1568084068 0 1568084068 0 "pipe_regs//VX_d_e_reg.v"
S 1538 1573254 1567973402 0 1567973402 0 "pipe_regs//VX_e_m_reg.v"
S 755 1591921 1567978394 0 1567978394 0 "pipe_regs//VX_f_d_reg.v"
S 751 891628 1568084040 0 1568084040 0 "pipe_regs//VX_f_d_reg.v"
S 688 1573273 1567972184 0 1567972184 0 "pipe_regs//VX_m_w_reg.v"

BIN
rtl/obj_dir/test_bench.o
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Binary file not shown.

135
rtl/pipe_regs/VX_d_e_reg.v
View file

@ -8,7 +8,7 @@ module VX_d_e_reg (
input wire in_fwd_stall,
input wire in_branch_stall,
input wire in_freeze,
input wire in_clone_stall,
input wire in_gpr_stall,
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
@ -17,7 +17,7 @@ module VX_d_e_reg (
wire stall = in_freeze;
wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_gpr_stall == `STALL);
VX_generic_register #(.N(490)) d_e_reg
@ -31,137 +31,6 @@ module VX_d_e_reg (
);
// wire[`NT_M1:0][31:0] temp_out_a_reg_data;
// wire[`NT_M1:0][31:0] temp_out_b_reg_data;
// wire[`NT_M1:0] temp_out_valid;
// genvar index;
// for (index = 0; index <= `NT_M1; index = index + 1) begin
// assign out_valid[index] = temp_out_valid[index];
// assign out_a_reg_data[index] = temp_out_a_reg_data[index];
// assign out_b_reg_data[index] = temp_out_b_reg_data[index];
// end
// reg[4:0] rd;
// reg[4:0] rs1;
// reg[4:0] rs2;
// reg[31:0] a_reg_data[`NT_M1:0];
// reg[31:0] b_reg_data[`NT_M1:0];
// reg[4:0] alu_op;
// reg[1:0] wb;
// reg[31:0] PC_next_out;
// reg rs2_src;
// reg[31:0] itype_immed;
// reg[2:0] mem_read;
// reg[2:0] mem_write;
// reg[2:0] branch_type;
// reg[19:0] upper_immed;
// reg[11:0] csr_address;
// reg is_csr;
// reg[31:0] csr_mask;
// reg[31:0] curr_PC;
// reg jal;
// reg[31:0] jal_offset;
// reg valid[`NT_M1:0];
// reg[31:0] reg_data_z[`NT_M1:0];
// reg valid_z[`NT_M1:0];
// reg[`NW_M1:0] warp_num;
// integer ini_reg;
// initial begin
// rd = 0;
// rs1 = 0;
// for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
// begin
// a_reg_data[ini_reg] = 0;
// b_reg_data[ini_reg] = 0;
// reg_data_z[ini_reg] = 0;
// valid[ini_reg] = 0;
// valid_z[ini_reg] = 0;
// end
// rs2 = 0;
// alu_op = 0;
// wb = `NO_WB;
// PC_next_out = 0;
// rs2_src = 0;
// itype_immed = 0;
// mem_read = `NO_MEM_READ;
// mem_write = `NO_MEM_WRITE;
// branch_type = `NO_BRANCH;
// upper_immed = 0;
// csr_address = 0;
// is_csr = 0;
// csr_mask = 0;
// curr_PC = 0;
// jal = `NO_JUMP;
// jal_offset = 0;
// warp_num = 0;
// end
// wire stalling;
// assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
// Freeze stall
// Stalling flush
// assign out_rd = rd;
// assign out_rs1 = rs1;
// assign out_rs2 = rs2;
// assign out_a_reg_data = a_reg_data;
// assign out_b_reg_data = b_reg_data;
// assign out_alu_op = alu_op;
// assign out_wb = wb;
// assign out_PC_next = PC_next_out;
// assign out_rs2_src = rs2_src;
// assign out_itype_immed = itype_immed;
// assign out_mem_read = mem_read;
// assign out_mem_write = mem_write;
// assign out_branch_type = branch_type;
// assign out_upper_immed = upper_immed;
// assign out_csr_address = csr_address;
// assign out_is_csr = is_csr;
// assign out_csr_mask = csr_mask;
// assign out_jal = jal;
// assign out_jal_offset = jal_offset;
// assign out_curr_PC = curr_PC;
// assign out_valid = valid;
// assign out_warp_num = warp_num;
// always @(posedge clk) begin
// if (in_freeze == 1'h0) begin
// rd <= stalling ? 5'h0 : in_rd;
// rs1 <= stalling ? 5'h0 : in_rs1;
// rs2 <= stalling ? 5'h0 : in_rs2;
// a_reg_data <= stalling ? reg_data_z : in_a_reg_data;
// b_reg_data <= stalling ? reg_data_z : in_b_reg_data;
// alu_op <= stalling ? `NO_ALU : in_alu_op;
// wb <= stalling ? `NO_WB : in_wb;
// PC_next_out <= stalling ? 32'h0 : in_PC_next;
// rs2_src <= stalling ? `RS2_REG : in_rs2_src;
// itype_immed <= stalling ? 32'hdeadbeef : in_itype_immed;
// mem_read <= stalling ? `NO_MEM_READ : in_mem_read;
// mem_write <= stalling ? `NO_MEM_WRITE: in_mem_write;
// branch_type <= stalling ? `NO_BRANCH : in_branch_type;
// upper_immed <= stalling ? 20'h0 : in_upper_immed;
// csr_address <= stalling ? 12'h0 : in_csr_address;
// is_csr <= stalling ? 1'h0 : in_is_csr;
// csr_mask <= stalling ? 32'h0 : in_csr_mask;
// jal <= stalling ? `NO_JUMP : in_jal;
// jal_offset <= stalling ? 32'h0 : in_jal_offset;
// curr_PC <= stalling ? 32'h0 : in_curr_PC;
// valid <= stalling ? valid_z : in_valid;
// warp_num <= stalling ? 0 : in_warp_num;
// end
// end
endmodule

4
rtl/pipe_regs/VX_f_d_reg.v
View file

@ -5,7 +5,7 @@ module VX_f_d_reg (
input wire reset,
input wire in_fwd_stall,
input wire in_freeze,
input wire in_clone_stall,
input wire in_gpr_stall,
VX_inst_meta_inter fe_inst_meta_fd,
VX_inst_meta_inter fd_inst_meta_de
@ -13,7 +13,7 @@ module VX_f_d_reg (
);
wire flush = 1'b0;
wire stall = in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall;
wire stall = in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_gpr_stall;

BIN
rtl/quartus/._Makefile Normal file
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BIN
rtl/quartus/._project.tcl Normal file
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70
rtl/quartus/Makefile Normal file
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@ -0,0 +1,70 @@
PROJECT = VX_gpr_syn
TOP_LEVEL_ENTITY = VX_gpr_syn
SRC_FILE = VX_gpr_syn.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N4F45I3SG
# Executable Configuration
SYN_ARGS = --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt
syn: smart.log $(PROJECT).syn.rpt
fit: smart.log $(PROJECT).fit.rpt
asm: smart.log $(PROJECT).asm.rpt
sta: smart.log $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES)
/tools/reconfig/intel/18.0/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt
/tools/reconfig/intel/18.0/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
/tools/reconfig/intel/18.0/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
/tools/reconfig/intel/18.0/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
/tools/reconfig/intel/18.0/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
/tools/reconfig/intel/18.0/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox

86
rtl/quartus/project.tcl Normal file
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@ -0,0 +1,86 @@
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name SEARCH_PATH ../
set_global_assignment -name VERILOG_FILE ../VX_define.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
set_global_assignment -name VERILOG_FILE ../VX_alu.v
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
set_global_assignment -name VERILOG_FILE ../VX_context.v
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
set_global_assignment -name VERILOG_FILE ../VX_decode.v
set_global_assignment -name VERILOG_FILE ../VX_define.v
set_global_assignment -name VERILOG_FILE ../VX_execute.v
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
set_global_assignment -name VERILOG_FILE ../VX_memory.v
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
set_global_assignment -name VERILOG_FILE ../VX_warp.v
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
set_global_assignment -name VERILOG_FILE ../Vortex.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
project_close
# set_global_assignment -name VERILOG_FILE $opts(src)

40
rtl/quartus/vortex.ini Normal file
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@ -0,0 +1,40 @@
load_package flow
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
# pins configuration
package require cmdline
proc make_all_pins_virtual { args } {
set options {\
{ "exclude.arg" "" "List of signals to exclude" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
remove_all_instance_assignments -name VIRTUAL_PIN
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
} else {
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
}
}
export_assignments
}
make_all_pins_virtual -exclude { clk, reset }

2
rtl/clk_const.sdc → rtl/quartus/vortex.sdc
View file

@ -1 +1 @@
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

2
rtl/results.txt
View file

@ -3,5 +3,5 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00015
# time to simulate: 2.17e-314 milliseconds
# time to simulate: 2.22726e-314 milliseconds
# GRADE: Failed on test: 4294967295