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minor update
This commit is contained in:
Blaise Tine
parent
37555b1208
commit
8d1baf677d
2 changed files with 31 additions and 33 deletions
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@ -259,7 +259,7 @@ config2()
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AXI_BUS=1 ./ci/blackbox.sh --driver=rtlsim --app=mstress
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# test 128-bit MEM block
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CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128" ./ci/blackbox.sh --driver=opae --app=mstress
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CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=opae --app=mstress
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# test XLEN-bit MEM block
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CONFIGS="-DMEM_BLOCK_SIZE=$XSIZE" ./ci/blackbox.sh --driver=opae --app=mstress
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@ -1,30 +1,28 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`include "VX_define.vh"
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`IGNORE_WARNINGS_BEGIN
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`include "vortex_afu.vh"
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`IGNORE_WARNINGS_END
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`include "VX_define.vh"
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module vortex_afu_shim import local_mem_cfg_pkg::*; import ccip_if_pkg::*; (
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// global signals
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input clk,
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input reset,
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// IF signals between CCI and AFU
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input logic vcp2af_sRxPort_c0_TxAlmFull,
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input logic vcp2af_sRxPort_c0_TxAlmFull,
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input logic vcp2af_sRxPort_c1_TxAlmFull,
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input t_ccip_vc vcp2af_sRxPort_c0_hdr_vc_used,
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@ -35,15 +33,15 @@ module vortex_afu_shim import local_mem_cfg_pkg::*; import ccip_if_pkg::*; (
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input t_ccip_c0_rsp vcp2af_sRxPort_c0_hdr_resp_type,
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input t_ccip_mdata vcp2af_sRxPort_c0_hdr_mdata,
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input t_ccip_clData vcp2af_sRxPort_c0_data,
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input logic vcp2af_sRxPort_c0_rspValid,
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input logic vcp2af_sRxPort_c0_mmioRdValid,
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input logic vcp2af_sRxPort_c0_mmioWrValid,
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input logic vcp2af_sRxPort_c0_rspValid,
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input logic vcp2af_sRxPort_c0_mmioRdValid,
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input logic vcp2af_sRxPort_c0_mmioWrValid,
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input t_ccip_mmioAddr vcp2af_sRxPort_c0_ReqMmioHdr_address,
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input logic [1:0] vcp2af_sRxPort_c0_ReqMmioHdr_length,
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input logic [1:0] vcp2af_sRxPort_c0_ReqMmioHdr_length,
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input logic vcp2af_sRxPort_c0_ReqMmioHdr_rsvd,
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input t_ccip_tid vcp2af_sRxPort_c0_ReqMmioHdr_tid,
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input t_ccip_tid vcp2af_sRxPort_c0_ReqMmioHdr_tid,
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input t_ccip_vc vcp2af_sRxPort_c1_hdr_vc_used,
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input logic vcp2af_sRxPort_c1_hdr_rsvd1,
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input logic vcp2af_sRxPort_c1_hdr_hit_miss,
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@ -51,34 +49,34 @@ module vortex_afu_shim import local_mem_cfg_pkg::*; import ccip_if_pkg::*; (
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input logic vcp2af_sRxPort_c1_hdr_rsvd0,
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input t_ccip_clNum vcp2af_sRxPort_c1_hdr_cl_num,
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input t_ccip_c1_rsp vcp2af_sRxPort_c1_hdr_resp_type,
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input t_ccip_mdata vcp2af_sRxPort_c1_hdr_mdata,
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input logic vcp2af_sRxPort_c1_rspValid,
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input t_ccip_mdata vcp2af_sRxPort_c1_hdr_mdata,
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input logic vcp2af_sRxPort_c1_rspValid,
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output t_ccip_vc af2cp_sTxPort_c0_hdr_vc_sel,
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output logic [1:0] af2cp_sTxPort_c0_hdr_rsvd1,
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output logic [1:0] af2cp_sTxPort_c0_hdr_rsvd1,
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output t_ccip_clLen af2cp_sTxPort_c0_hdr_cl_len,
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output t_ccip_c0_req af2cp_sTxPort_c0_hdr_req_type,
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output logic [5:0] af2cp_sTxPort_c0_hdr_rsvd0,
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output logic [5:0] af2cp_sTxPort_c0_hdr_rsvd0,
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output t_ccip_clAddr af2cp_sTxPort_c0_hdr_address,
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output t_ccip_mdata af2cp_sTxPort_c0_hdr_mdata,
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output logic af2cp_sTxPort_c0_valid,
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output logic af2cp_sTxPort_c0_valid,
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output logic [5:0] af2cp_sTxPort_c1_hdr_rsvd2,
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output t_ccip_vc af2cp_sTxPort_c1_hdr_vc_sel,
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output logic af2cp_sTxPort_c1_hdr_sop,
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output logic af2cp_sTxPort_c1_hdr_rsvd1,
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output logic af2cp_sTxPort_c1_hdr_rsvd1,
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output t_ccip_clLen af2cp_sTxPort_c1_hdr_cl_len,
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output t_ccip_c1_req af2cp_sTxPort_c1_hdr_req_type,
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output logic [5:0] af2cp_sTxPort_c1_hdr_rsvd0,
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output logic [5:0] af2cp_sTxPort_c1_hdr_rsvd0,
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output t_ccip_clAddr af2cp_sTxPort_c1_hdr_address,
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output t_ccip_mdata af2cp_sTxPort_c1_hdr_mdata,
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output t_ccip_clData af2cp_sTxPort_c1_data,
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output logic af2cp_sTxPort_c1_valid,
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output t_ccip_clData af2cp_sTxPort_c1_data,
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output logic af2cp_sTxPort_c1_valid,
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output t_ccip_tid af2cp_sTxPort_c2_hdr_tid,
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output logic af2cp_sTxPort_c2_mmioRdValid,
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output t_ccip_mmioData af2cp_sTxPort_c2_data,
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output logic af2cp_sTxPort_c2_mmioRdValid,
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output t_ccip_mmioData af2cp_sTxPort_c2_data,
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// Avalon signals for local memory access
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output t_local_mem_data avs_writedata [`PLATFORM_PARAM_LOCAL_MEMORY_BANKS],
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input t_local_mem_data avs_readdata [`PLATFORM_PARAM_LOCAL_MEMORY_BANKS],
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@ -119,7 +117,7 @@ always @ (*) begin
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c0_RxHdr.reqMmioHdr.address = vcp2af_sRxPort_c0_ReqMmioHdr_address;
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c0_RxHdr.reqMmioHdr.length = vcp2af_sRxPort_c0_ReqMmioHdr_length;
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c0_RxHdr.reqMmioHdr.rsvd = vcp2af_sRxPort_c0_ReqMmioHdr_rsvd;
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c0_RxHdr.reqMmioHdr.tid = vcp2af_sRxPort_c0_ReqMmioHdr_tid;
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c0_RxHdr.reqMmioHdr.tid = vcp2af_sRxPort_c0_ReqMmioHdr_tid;
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end else begin
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c0_RxHdr.rspMemHdr.vc_used = vcp2af_sRxPort_c0_hdr_vc_used;
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c0_RxHdr.rspMemHdr.rsvd1 = vcp2af_sRxPort_c0_hdr_rsvd1;
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@ -134,7 +132,7 @@ end
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assign cp2af_sRxPort.c0TxAlmFull = vcp2af_sRxPort_c0_TxAlmFull;
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assign cp2af_sRxPort.c1TxAlmFull = vcp2af_sRxPort_c1_TxAlmFull;
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assign cp2af_sRxPort.c0.hdr = c0_RxHdr;
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assign cp2af_sRxPort.c0.hdr = c0_RxHdr;
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assign cp2af_sRxPort.c0.data = vcp2af_sRxPort_c0_data;
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assign cp2af_sRxPort.c0.rspValid = vcp2af_sRxPort_c0_rspValid;
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assign cp2af_sRxPort.c0.mmioRdValid = vcp2af_sRxPort_c0_mmioRdValid;
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@ -147,8 +145,8 @@ assign cp2af_sRxPort.c1.hdr.format = vcp2af_sRxPort_c1_hdr_format;
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assign cp2af_sRxPort.c1.hdr.rsvd0 = vcp2af_sRxPort_c1_hdr_rsvd0;
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assign cp2af_sRxPort.c1.hdr.cl_num = vcp2af_sRxPort_c1_hdr_cl_num;
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assign cp2af_sRxPort.c1.hdr.resp_type = vcp2af_sRxPort_c1_hdr_resp_type;
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assign cp2af_sRxPort.c1.hdr.mdata = vcp2af_sRxPort_c1_hdr_mdata;
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assign cp2af_sRxPort.c1.rspValid = vcp2af_sRxPort_c1_rspValid;
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assign cp2af_sRxPort.c1.hdr.mdata = vcp2af_sRxPort_c1_hdr_mdata;
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assign cp2af_sRxPort.c1.rspValid = vcp2af_sRxPort_c1_rspValid;
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assign af2cp_sTxPort_c0_hdr_vc_sel = af2cp_sTxPort.c0.hdr.vc_sel;
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assign af2cp_sTxPort_c0_hdr_rsvd1 = af2cp_sTxPort.c0.hdr.rsvd1;
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@ -168,11 +166,11 @@ assign af2cp_sTxPort_c1_hdr_req_type = af2cp_sTxPort.c1.hdr.req_type;
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assign af2cp_sTxPort_c1_hdr_rsvd0 = af2cp_sTxPort.c1.hdr.rsvd0;
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assign af2cp_sTxPort_c1_hdr_address = af2cp_sTxPort.c1.hdr.address;
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assign af2cp_sTxPort_c1_hdr_mdata = af2cp_sTxPort.c1.hdr.mdata;
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assign af2cp_sTxPort_c1_data = af2cp_sTxPort.c1.data;
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assign af2cp_sTxPort_c1_data = af2cp_sTxPort.c1.data;
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assign af2cp_sTxPort_c1_valid = af2cp_sTxPort.c1.valid;
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assign af2cp_sTxPort_c2_hdr_tid = af2cp_sTxPort.c2.hdr.tid;
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assign af2cp_sTxPort_c2_mmioRdValid = af2cp_sTxPort.c2.mmioRdValid;
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assign af2cp_sTxPort_c2_hdr_tid = af2cp_sTxPort.c2.hdr.tid;
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assign af2cp_sTxPort_c2_mmioRdValid = af2cp_sTxPort.c2.mmioRdValid;
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assign af2cp_sTxPort_c2_data = af2cp_sTxPort.c2.data;
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endmodule
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