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minor updates

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This commit is contained in:
Blaise Tine 2024-09-05 21:29:01 -07:00
parent cf9172b8fc
commit 8db77ea1cd
7 changed files with 14 additions and 16 deletions
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3
hw/rtl/VX_cluster.sv
View file

@ -119,7 +119,8 @@ module VX_cluster import VX_gpu_pkg::*; #(
///////////////////////////////////////////////////////////////////////////
VX_dcr_bus_if socket_dcr_bus_tmp_if();
assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
wire is_dcr_base_addr = (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && is_dcr_base_addr;
assign socket_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
assign socket_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;

13
hw/syn/xilinx/scripts/xsim.tcl
View file

@ -14,12 +14,9 @@
# limitations under the License.
#
#log_wave -r *
#run all
#exit
log_wave -r *
open_vcd xsim_dump.vcd
log_vcd /*
run all
close_vcd
exit
#open_vcd xsim_dump.vcd
#log_vcd /*
#run all
#close_vcd

2
hw/syn/xilinx/xrt/Makefile
View file

@ -117,7 +117,7 @@ endif
# Debugging
ifdef DEBUG
VPP_FLAGS += -g --debug.protocol all
VPP_FLAGS += -g --optimize 0 --debug.protocol all
ifneq ($(TARGET), hw)
VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
CFLAGS += -DDEBUG_LEVEL=$(DEBUG) $(DBG_TRACE_FLAGS)

6
hw/syn/xilinx/xrt/xrt.ini → hw/syn/xilinx/xrt/xrt.ini.in
View file

@ -1,9 +1,9 @@
[Runtime]
[Runtime]
runtime_log=console
[Emulation]
#debug_mode=batch
#user_pre_sim_script=xsim.tcl
debug_mode=batch
user_pre_sim_script=@VORTEX_HOME@/hw/syn/xilinx/scripts/xsim.tcl
[Debug]
profile=true

2
sim/opaesim/opae_sim.cpp
View file

@ -125,7 +125,7 @@ public:
}
int init() {
// force random values for unitialized signals
// force random values for uninitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);

2
sim/rtlsim/processor.cpp
View file

@ -98,7 +98,7 @@ void sim_trace_enable(bool enable) {
class Processor::Impl {
public:
Impl() : dram_sim_(MEM_CLOCK_RATIO) {
// force random values for unitialized signals
// force random values for uninitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);

2
sim/xrtsim/xrt_sim.cpp
View file

@ -112,7 +112,7 @@ public:
}
int init() {
// force random values for unitialized signals
// force random values for uninitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);