mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
xilinx synthesis debugging fixes
This commit is contained in:
Blaise Tine
parent
8908f3e006
commit
8e3bd5696b
8 changed files with 107 additions and 56 deletions
|
|
@ -299,6 +299,39 @@ module VX_afu_wrap #(
|
|||
|
||||
// SCOPE //////////////////////////////////////////////////////////////////////
|
||||
|
||||
`ifdef DBG_SCOPE_AFU
|
||||
`ifdef SCOPE
|
||||
`define TRIGGERS { \
|
||||
reset, \
|
||||
ap_reset, \
|
||||
ap_start, \
|
||||
ap_done, \
|
||||
ap_idle, \
|
||||
interrupt, \
|
||||
vx_busy_wait, \
|
||||
vx_busy, \
|
||||
vx_reset \
|
||||
}
|
||||
`define PROBES { \
|
||||
vx_pending_writes \
|
||||
}
|
||||
VX_scope_tap #(
|
||||
.SCOPE_ID (0),
|
||||
.TRIGGERW ($bits(`TRIGGERS)),
|
||||
.PROBEW ($bits(`PROBES))
|
||||
) scope_tap (
|
||||
.clk (clk),
|
||||
.reset (scope_reset_w[0]),
|
||||
.start (1'b0),
|
||||
.stop (1'b0),
|
||||
.triggers (`TRIGGERS),
|
||||
.probes (`PROBES),
|
||||
.bus_in (scope_bus_in_w[0]),
|
||||
.bus_out (scope_bus_out_w[0])
|
||||
);
|
||||
`else
|
||||
`SCOPE_IO_UNUSED_W(0)
|
||||
`endif
|
||||
`ifdef CHIPSCOPE
|
||||
ila_afu ila_afu_inst (
|
||||
.clk (clk),
|
||||
|
|
@ -320,40 +353,6 @@ module VX_afu_wrap #(
|
|||
})
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef DBG_SCOPE_AFU
|
||||
`define TRIGGERS { \
|
||||
reset, \
|
||||
ap_reset, \
|
||||
ap_start, \
|
||||
ap_done, \
|
||||
ap_idle, \
|
||||
interrupt, \
|
||||
vx_busy_wait, \
|
||||
vx_busy, \
|
||||
vx_reset \
|
||||
}
|
||||
|
||||
`define PROBES { \
|
||||
vx_pending_writes \
|
||||
}
|
||||
|
||||
VX_scope_tap #(
|
||||
.SCOPE_ID (0),
|
||||
.TRIGGERW ($bits(`TRIGGERS)),
|
||||
.PROBEW ($bits(`PROBES))
|
||||
) scope_tap (
|
||||
.clk (clk),
|
||||
.reset (scope_reset_w[0]),
|
||||
.start (1'b0),
|
||||
.stop (1'b0),
|
||||
.triggers (`TRIGGERS),
|
||||
.probes (`PROBES),
|
||||
.bus_in (scope_bus_in_w[0]),
|
||||
.bus_out (scope_bus_out_w[0])
|
||||
);
|
||||
`else
|
||||
`SCOPE_IO_UNUSED_W(0)
|
||||
`endif
|
||||
|
||||
`ifdef SIMULATION
|
||||
|
|
|
|||
|
|
@ -132,6 +132,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
|
|||
assign icache_bus_if.rsp_ready = fetch_if.ready;
|
||||
|
||||
`ifdef DBG_SCOPE_FETCH
|
||||
`ifdef SCOPE
|
||||
wire schedule_fire = schedule_if.valid && schedule_if.ready;
|
||||
wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
|
||||
VX_scope_tap #(
|
||||
|
|
@ -162,6 +163,15 @@ module VX_fetch import VX_gpu_pkg::*; #(
|
|||
`else
|
||||
`SCOPE_IO_UNUSED()
|
||||
`endif
|
||||
`ifdef CHIPSCOPE
|
||||
ila_fetch ila_fetch_inst (
|
||||
.clk (clk),
|
||||
.probe0 ({schedule_if.valid, schedule_if.data, schedule_if.ready}),
|
||||
.probe1 ({icache_bus_if.req_valid, icache_bus_if.req_data, icache_bus_if.req_ready}),
|
||||
.probe2 ({icache_bus_if.rsp_valid, icache_bus_if.rsp_data, icache_bus_if.rsp_ready})
|
||||
);
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef DBG_TRACE_MEM
|
||||
always @(posedge clk) begin
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
|
|||
);
|
||||
|
||||
`ifdef DBG_SCOPE_ISSUE
|
||||
`ifdef SCOPE
|
||||
wire operands_if_fire = operands_if.valid && operands_if.ready;
|
||||
wire operands_if_not_ready = ~operands_if.ready;
|
||||
wire writeback_if_valid = writeback_if.valid;
|
||||
|
|
@ -131,6 +132,16 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
|
|||
`else
|
||||
`SCOPE_IO_UNUSED()
|
||||
`endif
|
||||
`ifdef CHIPSCOPE
|
||||
ila_issue ila_issue_inst (
|
||||
.clk (clk),
|
||||
.probe0 ({decode_if.valid, decode_if.data, decode_if.ready}),
|
||||
.probe1 ({scoreboard_if.valid, scoreboard_if.data, scoreboard_if.ready}),
|
||||
.probe2 ({operands_if.valid, operands_if.data, operands_if.ready}),
|
||||
.probe3 ({writeback_if.valid, writeback_if.data})
|
||||
);
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef DBG_TRACE_PIPELINE
|
||||
always @(posedge clk) begin
|
||||
|
|
|
|||
|
|
@ -341,7 +341,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
|
|||
.core_req_tag (mem_req_tag),
|
||||
.core_req_ready (mem_req_ready),
|
||||
`UNUSED_PIN (core_req_empty),
|
||||
`UNUSED_PIN (core_req_sent),
|
||||
`UNUSED_PIN (core_write_notify),
|
||||
|
||||
// Output response
|
||||
.core_rsp_valid (mem_rsp_valid),
|
||||
|
|
@ -535,6 +535,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
|
|||
`endif
|
||||
|
||||
`ifdef DBG_SCOPE_LSU
|
||||
`ifdef SCOPE
|
||||
VX_scope_tap #(
|
||||
.SCOPE_ID (3),
|
||||
.TRIGGERW (3),
|
||||
|
|
@ -552,5 +553,14 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
|
|||
`else
|
||||
`SCOPE_IO_UNUSED()
|
||||
`endif
|
||||
`ifdef CHIPSCOPE
|
||||
ila_lsu ila_lsu_inst (
|
||||
.clk (clk),
|
||||
.probe0 ({execute_if.valid, execute_if.data, execute_if.ready}),
|
||||
.probe1 ({lsu_mem_if.req_valid, lsu_mem_if.req_data, lsu_mem_if.req_ready}),
|
||||
.probe2 ({lsu_mem_if.rsp_valid, lsu_mem_if.rsp_data, lsu_mem_if.rsp_ready})
|
||||
);
|
||||
`endif
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -8,6 +8,9 @@ xbutil validate --device 0000:09:00.1 --verbose
|
|||
vivado -mode batch -source xilinx_ip_gen.tcl -tclargs ip/xilinx_u50_gen3x16_xdma_5_202210_1
|
||||
|
||||
# build FPGA
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u55c_gen3x16_xdma_3_202210_1 make > build_u55c_hw_emu_base_1c.log 2>&1 &
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u55c_gen3x16_xdma_3_202210_1 make > build_u55c_hw_base_1c.log 2>&1 &
|
||||
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_1c.log 2>&1 &
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_1c.log 2>&1 &
|
||||
|
||||
|
|
@ -25,14 +28,21 @@ PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make
|
|||
# debug hw_emu using xsim
|
||||
xsim --gui xilinx_u50_gen3x16_xdma_5_202210_1-0-vortex_afu.wdb &
|
||||
|
||||
# debug hw using ILA
|
||||
# h/w debugging using ILA
|
||||
## (1) check for ILA support
|
||||
platforminfo --json="hardwarePlatform.extensions.chipscope_debug" xilinx_u50_gen3x16_xdma_5_202210_1
|
||||
## (2) chedk for XVC full path to get device id
|
||||
ls /dev/xfpga/xvc_pub*
|
||||
ls /dev/xvc_pub*
|
||||
debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server
|
||||
debug_hw --xvc_pcie /dev/xvc_pub.u0 --hw_server
|
||||
## (3) start h/w server
|
||||
debug_hw --xvc_pcie /dev/xfpga/xvc_pub.<deviceid> --hw_server
|
||||
## (4) start application and pause
|
||||
## (5) start vivado to connect to h/w server and select ILA probes
|
||||
debug_hw --vivado --host localhost --ltx_file ./build_xilinx_u50_gen3x16_xdma_5_202210_1_hw/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
|
||||
make chipscope TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1
|
||||
## (6) resume application
|
||||
|
||||
# supported ILA Makefie targets
|
||||
TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make hw_server
|
||||
TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make chipscope
|
||||
|
||||
# analyze build report
|
||||
vitis_analyzer build_xilinx_u50_gen3x16_xdma_5_202210_1_hw_4c/bin/vortex_afu.xclbin.link_summary
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE
|
|||
DBG_TRACE_FLAGS += -DDBG_TRACE_MEM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_OM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
|
||||
|
||||
# Control logic analyzer monitors
|
||||
|
|
@ -60,6 +63,9 @@ DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
|
|||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_TEX
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_OM
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
|
||||
|
||||
# cluster configuration
|
||||
|
|
@ -77,8 +83,11 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
|||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/include -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src -J$(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/cvfpu/src
|
||||
endif
|
||||
TEX_INCLUDE = -I$(RTL_DIR)/tex
|
||||
RASTER_INCLUDE = -I$(RTL_DIR)/raster
|
||||
OM_INCLUDE = -I$(RTL_DIR)/om
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR)
|
||||
RTL_INCLUDE += $(FPU_INCLUDE)
|
||||
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(OM_INCLUDE)
|
||||
|
||||
# Kernel compiler global settings
|
||||
VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
|
||||
|
|
@ -179,17 +188,18 @@ $(BIN_DIR)/emconfig.json:
|
|||
mkdir -p $(BIN_DIR); cd $(BUILD_DIR); emconfigutil --platform $(PLATFORM) --od ../$(BIN_DIR)
|
||||
|
||||
report: $(XCLBIN_CONTAINER)
|
||||
ifeq ($(TARGET),$(findstring $(TARGET), hw))
|
||||
cp $(BUILD_DIR)/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log $(BUILD_DIR)/bin/runme.log
|
||||
ifeq ($(TARGET), hw)
|
||||
cp $(BUILD_DIR)/_x/logs/link/vivado.log $(BUILD_DIR)/bin/vivado.log
|
||||
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_full_util_routed.rpt $(BUILD_DIR)/bin/synthesis.log
|
||||
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin/timing.log
|
||||
[ -f "$(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx" ] && cp $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx $(BUILD_DIR)/bin/debug_nets.ltx
|
||||
endif
|
||||
|
||||
hwserver:
|
||||
debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server &
|
||||
|
||||
chipscope:
|
||||
debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
|
||||
debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/bin/debug_nets.ltx &
|
||||
|
||||
clean:
|
||||
$(RMDIR) $(BUILD_DIR)
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ if {[file exists "${xoname}"]} {
|
|||
|
||||
set argv [list ${build_dir}/ip]
|
||||
set argc 1
|
||||
source ${script_path}/xilinx_ip_gen.tcl
|
||||
source ${tool_dir}/xilinx_ip_gen.tcl
|
||||
|
||||
set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
|
||||
set argc 4
|
||||
|
|
|
|||
|
|
@ -89,9 +89,9 @@ if { $chipscope == 1 } {
|
|||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {8192} \
|
||||
CONFIG.C_NUM_OF_PROBES {3} \
|
||||
CONFIG.C_PROBE0_WIDTH {128} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_PROBE2_WIDTH {128} \
|
||||
CONFIG.C_PROBE0_WIDTH {40} \
|
||||
CONFIG.C_PROBE1_WIDTH {80} \
|
||||
CONFIG.C_PROBE2_WIDTH {40} \
|
||||
CONFIG.ALL_PROBE_SAME_MU {false} \
|
||||
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
|
||||
] [get_ips ila_fetch]
|
||||
|
|
@ -102,9 +102,11 @@ if { $chipscope == 1 } {
|
|||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {8192} \
|
||||
CONFIG.C_NUM_OF_PROBES {2} \
|
||||
CONFIG.C_PROBE0_WIDTH {256} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_NUM_OF_PROBES {4} \
|
||||
CONFIG.C_PROBE0_WIDTH {112} \
|
||||
CONFIG.C_PROBE1_WIDTH {112} \
|
||||
CONFIG.C_PROBE2_WIDTH {280} \
|
||||
CONFIG.C_PROBE3_WIDTH {112} \
|
||||
CONFIG.ALL_PROBE_SAME_MU {false} \
|
||||
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
|
||||
] [get_ips ila_issue]
|
||||
|
|
@ -115,11 +117,10 @@ if { $chipscope == 1 } {
|
|||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {8192} \
|
||||
CONFIG.C_NUM_OF_PROBES {4} \
|
||||
CONFIG.C_PROBE0_WIDTH {256} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_PROBE2_WIDTH {288} \
|
||||
CONFIG.C_PROBE3_WIDTH {256} \
|
||||
CONFIG.C_NUM_OF_PROBES {3} \
|
||||
CONFIG.C_PROBE0_WIDTH {288} \
|
||||
CONFIG.C_PROBE1_WIDTH {152} \
|
||||
CONFIG.C_PROBE2_WIDTH {72} \
|
||||
CONFIG.ALL_PROBE_SAME_MU {false} \
|
||||
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
|
||||
] [get_ips ila_lsu]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue