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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
96a03a3edf
commit
8fa78ef059
5 changed files with 67 additions and 59 deletions
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@ -35,6 +35,8 @@ module VX_tex_addr_gen #(
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output wire mem_req_valid,
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output wire [`NUM_THREADS-1:0] mem_req_tmask,
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output wire [`TEX_FILTER_BITS-1:0] mem_req_filter,
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output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u,
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output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v,
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output wire [REQ_TAG_WIDTH-1:0] mem_req_tag,
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output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
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input wire mem_req_ready
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@ -114,14 +116,14 @@ module VX_tex_addr_gen #(
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wire stall_out = mem_req_valid && ~mem_req_ready;
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VX_pipe_register #(
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.DATAW (1 + `NUM_THREADS + `TEX_FILTER_BITS + REQ_TAG_WIDTH + (`NUM_THREADS * 4 * 32)),
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.DATAW (1 + `NUM_THREADS + `TEX_FILTER_BITS + REQ_TAG_WIDTH + (`NUM_THREADS * 4 * 32) + (`NUM_THREADS * `FIXED_FRAC)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({valid_in, req_tmask, filter, req_tag, addr}),
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.data_out ({mem_req_valid, mem_req_tmask, mem_req_filter, mem_req_tag, mem_req_addr})
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.data_in ({valid_in, req_tmask, filter, req_tag, addr, u[0], v[0]}),
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.data_out ({mem_req_valid, mem_req_tmask, mem_req_filter, mem_req_tag, mem_req_addr, mem_req_u, mem_req_v})
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);
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assign ready_in = ~stall_out;
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@ -26,6 +26,8 @@
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`define MAX_COLOR_WIDTH 8
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`define NUM_COLOR_CHANNEL 4
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`define TEX_COLOR_BITS 32
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`define R5G6B5 `TEX_FORMAT_BITS'h1
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`define R8G8B8 `TEX_FORMAT_BITS'h2
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`define R8G8B8A8 `TEX_FORMAT_BITS'h3
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@ -7,48 +7,42 @@ module VX_tex_format #(
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input wire [`TEX_FORMAT_BITS-1:0] format,
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output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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output wire [`MAX_COLOR_BITS-1:0] R,
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output wire [`MAX_COLOR_BITS-1:0] G,
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output wire [`MAX_COLOR_BITS-1:0] B,
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output wire [`MAX_COLOR_BITS-1:0] A
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output wire [`TEX_COLOR_BITS-1:0] R,
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output wire [`TEX_COLOR_BITS-1:0] G,
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output wire [`TEX_COLOR_BITS-1:0] B,
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output wire [`TEX_COLOR_BITS-1:0] A
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
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reg [`MAX_COLOR_BITS-1:0] R_r;
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reg [`MAX_COLOR_BITS-1:0] G_r;
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reg [`MAX_COLOR_BITS-1:0] B_r;
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reg [`MAX_COLOR_BITS-1:0] A_r;
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reg [`TEX_COLOR_BITS-1:0] R_r;
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reg [`TEX_COLOR_BITS-1:0] G_r;
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reg [`TEX_COLOR_BITS-1:0] B_r;
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reg [`TEX_COLOR_BITS-1:0] A_r;
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always @(*) begin
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case (format)
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`R5G6B5:
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R_r = `MAX_COLOR_BITS'(texel_data[15:11]);
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G_r = `MAX_COLOR_BITS'(texel_data[10:5]);
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B_r = `MAX_COLOR_BITS'(texel_data[4:0]);
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A_r = {`MAX_COLOR_BITS{1'b0}};
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`R5G6B5: begin
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R_r = `TEX_COLOR_BITS'(texel_data[15:11]);
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G_r = `TEX_COLOR_BITS'(texel_data[10:5]);
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B_r = `TEX_COLOR_BITS'(texel_data[4:0]);
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A_r = {`TEX_COLOR_BITS{1'b0}};
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color_enable_r = 4'b1110;
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`R8G8B8:
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R_r = `MAX_COLOR_BITS'(texel_data[23:16]);
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G_r = `MAX_COLOR_BITS'(texel_data[15:8]);
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B_r = `MAX_COLOR_BITS'(texel_data[7:0]);
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A_r = {`MAX_COLOR_BITS{1'b0}};
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color_enable_r = 4'b1110;
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`R8G8B8A8:
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R_r = `MAX_COLOR_BITS'(texel_data[31:24]);
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G_r = `MAX_COLOR_BITS'(texel_data[23:16]);
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B_r = `MAX_COLOR_BITS'(texel_data[15:8]);
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A_r = `MAX_COLOR_BITS'(texel_data[7:0]);
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color_enable_r = 4'b1111;
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default:
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R_r = `MAX_COLOR_BITS'(texel_data[23:16]);
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G_r = `MAX_COLOR_BITS'(texel_data[15:8]);
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B_r = `MAX_COLOR_BITS'(texel_data[7:0]);
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A_r = {`MAX_COLOR_BITS{1'b0}};
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end
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`R8G8B8: begin
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R_r = `TEX_COLOR_BITS'(texel_data[23:16]);
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G_r = `TEX_COLOR_BITS'(texel_data[15:8]);
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B_r = `TEX_COLOR_BITS'(texel_data[7:0]);
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A_r = {`TEX_COLOR_BITS{1'b0}};
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color_enable_r = 4'b1110;
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end
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default: begin // `R8G8B8A8:
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R_r = `TEX_COLOR_BITS'(texel_data[31:24]);
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G_r = `TEX_COLOR_BITS'(texel_data[23:16]);
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B_r = `TEX_COLOR_BITS'(texel_data[15:8]);
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A_r = `TEX_COLOR_BITS'(texel_data[7:0]);
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color_enable_r = 4'b1111;
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end
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endcase
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end
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@ -15,8 +15,8 @@ module VX_tex_sampler #(
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input wire req_wb,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [3:0][`FIXED_FRAC-1:0] req_ufrac,
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input wire [3:0][`FIXED_FRAC-1:0] req_vfrac,
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input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_u,
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input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_v,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels,
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output wire req_ready,
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@ -18,7 +18,8 @@ module VX_tex_unit #(
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VX_tex_rsp_if tex_rsp_if
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);
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localparam REQ_TAG_WIDTH = `TEX_FORMAT_BITS + `NW_BITS + 32 + `NR_BITS + 1;
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localparam REQ_TAG_WIDTH_A = `TEX_FORMAT_BITS + `NW_BITS + 32 + `NR_BITS + 1;
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localparam REQ_TAG_WIDTH_M = (2 * `NUM_THREADS * `FIXED_FRAC) + REQ_TAG_WIDTH_A;
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (reset)
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@ -70,19 +71,21 @@ module VX_tex_unit #(
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wire mem_req_valid;
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wire [`NUM_THREADS-1:0] mem_req_tmask;
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wire [`TEX_FILTER_BITS-1:0] mem_req_filter;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
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wire [REQ_TAG_WIDTH-1:0] mem_req_tag;
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wire [REQ_TAG_WIDTH_A-1:0] mem_req_tag;
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wire mem_req_ready;
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wire mem_rsp_valid;
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wire [`NUM_THREADS-1:0] mem_rsp_tmask;
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wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter;
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wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
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wire [REQ_TAG_WIDTH-1:0] mem_rsp_tag;
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wire [REQ_TAG_WIDTH_M-1:0] mem_rsp_tag;
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wire mem_rsp_ready;
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VX_tex_addr_gen #(
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.REQ_TAG_WIDTH (REQ_TAG_WIDTH)
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.REQ_TAG_WIDTH (REQ_TAG_WIDTH_A)
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) tex_addr_gen (
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.clk (clk),
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.reset (reset),
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@ -108,6 +111,8 @@ module VX_tex_unit #(
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.mem_req_valid (mem_req_valid),
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.mem_req_tmask (mem_req_tmask),
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.mem_req_filter (mem_req_filter),
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.mem_req_u (mem_req_u),
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.mem_req_v (mem_req_v),
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.mem_req_tag (mem_req_tag),
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.mem_req_addr (mem_req_addr),
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.mem_req_ready (mem_req_ready)
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@ -117,7 +122,7 @@ module VX_tex_unit #(
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VX_tex_memory #(
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.CORE_ID (CORE_ID),
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.REQ_TAG_WIDTH (REQ_TAG_WIDTH)
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.REQ_TAG_WIDTH (REQ_TAG_WIDTH_M)
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) tex_memory (
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.clk (clk),
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.reset (reset),
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@ -131,7 +136,7 @@ module VX_tex_unit #(
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.req_tmask (mem_req_tmask),
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.req_filter(mem_req_filter),
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.req_addr (mem_req_addr),
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.req_tag (mem_req_tag),
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.req_tag ({mem_req_u, mem_req_v, mem_req_tag}),
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.req_ready (mem_req_ready),
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// outputs
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@ -146,12 +151,14 @@ module VX_tex_unit #(
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// apply sampler
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wire [`TEX_FORMAT_BITS-1:0] rsp_format;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] rsp_u;
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wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] rsp_v;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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assign {rsp_format, rsp_wid, rsp_PC, rsp_rd, rsp_wb} = mem_rsp_tag;
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assign {rsp_format, rsp_u, rsp_v, rsp_wid, rsp_PC, rsp_rd, rsp_wb} = mem_rsp_tag;
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VX_tex_sampler #(
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.CORE_ID (CORE_ID)
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@ -165,6 +172,8 @@ module VX_tex_unit #(
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.req_texels (mem_rsp_data),
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.req_filter (mem_rsp_filter),
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.req_format (rsp_format),
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.req_u (rsp_u),
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.req_v (rsp_v),
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.req_wid (rsp_wid),
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.req_PC (rsp_PC),
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.req_rd (rsp_rd),
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@ -183,19 +192,20 @@ module VX_tex_unit #(
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);
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (tex_csr_if.write_enable
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&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0)
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&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES))) begin
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$display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
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$display("%t: core%0d-tex_csr: CSR_TEX0_PITCH, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]);
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for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
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always @(posedge clk) begin
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if (tex_csr_if.write_enable
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&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(i)
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&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(i+1))) begin
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$display("%t: core%0d-tex_csr: csr_tex%d_addr, csr_data=%0h", $time, CORE_ID, i, tex_addr[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_format, csr_data=%0h", $time, CORE_ID, i, tex_format[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_width, csr_data=%0h", $time, CORE_ID, i, tex_width[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_height, csr_data=%0h", $time, CORE_ID, i, tex_height[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_stride, csr_data=%0h", $time, CORE_ID, i, tex_stride[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_wrap_u, csr_data=%0h", $time, CORE_ID, i, tex_wrap_u[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_wrap_v, csr_data=%0h", $time, CORE_ID, i, tex_wrap_v[i]);
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$display("%t: core%0d-tex_csr: csr_tex%d_filter, csr_data=%0h", $time, CORE_ID, i, tex_filter[i]);
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end
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end
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end
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`endif
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