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fixed Modelsim build errors

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This commit is contained in:
Blaise Tine 2020-03-26 03:56:44 -04:00
parent 9621acff5b
commit 8fd742edd8
1 changed files with 5 additions and 8 deletions
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13
rtl/VX_alu.v
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@ -25,6 +25,9 @@ module VX_alu(
wire[63:0] mul_data_a, mul_data_b;
wire[63:0] mul_result;
wire[31:0] ALU_in1;
wire[31:0] ALU_in2;
VX_divide #(
.WIDTHN(32),
.WIDTHD(32),
@ -123,9 +126,6 @@ module VX_alu(
`ifdef SYN_FUNC
wire which_in2;
wire[31:0] ALU_in1;
wire[31:0] ALU_in2;
wire[31:0] upper_immed;
assign which_in2 = in_rs2_src == `RS2_IMMED;
@ -164,10 +164,7 @@ module VX_alu(
end
`else
wire which_in2;
wire[31:0] ALU_in1;
wire[31:0] ALU_in2;
wire which_in2;
wire[31:0] upper_immed;
@ -209,4 +206,4 @@ module VX_alu(
end
`endif
endmodule : VX_alu
endmodule : VX_alu