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read/write test works with core_req_t

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This commit is contained in:
trmontgomery 2020-07-18 19:25:03 -04:00
parent 2fc65f4a7d
commit 8ffc65f22f
3 changed files with 104 additions and 64 deletions
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108
hw/unit_tests/cache/cachesim.cpp vendored
View file

@ -60,8 +60,8 @@ void CacheSim::step() {
cache_->clk = 1;
this->eval();
//this->eval_reqs();
//this->eval_rsps();
this->eval_reqs();
this->eval_rsps();
this->eval_dram_bus();
}
@ -82,7 +82,7 @@ void CacheSim::run(){
this->step();
// execute program
while (!core_reqq_.empty()) {
while (!core_req_vec_.empty()) {
for(int i = 0; i < 10; ++i){
if(i == 1){
@ -98,9 +98,9 @@ void CacheSim::clear_req(){
cache_->core_req_valid = 0;
}
/*
void CacheSim::send_req(core_req_t *req){
core_reqq_.push(req);
core_req_vec_.push(req);
}
bool CacheSim::get_core_req_ready(){
@ -110,7 +110,6 @@ bool CacheSim::get_core_req_ready(){
bool CacheSim::get_core_rsp_ready(){
return cache_->core_rsp_ready;
}
*/
void CacheSim::set_core_req(){
cache_->core_req_valid = 0xf;
@ -143,46 +142,41 @@ void CacheSim::set_core_req2(){
}
void CacheSim::get_core_rsp(){
std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
char check = cache_->core_req_valid;
std::cout << "core_req_valid: " << check << std::endl;
std::cout << std::hex << "core_req_data: " << cache_->core_req_data << std::endl;
std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl;
}
void CacheSim::get_dram_req(){
std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl;
std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl;
std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl;
std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl;
std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl;
std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl;
}
void CacheSim::get_dram_rsp(){
std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl;
std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl;
std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl;
std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
}
void CacheSim::eval_reqs(){
//check to see if cache is accepting reqs
/*if(!core_reqq_.empty() && cache_->core_req_ready){
core_req_t *req = core_reqq_.front();
if(!core_req_vec_.empty() && cache_->core_req_ready){
core_req_t *req = core_req_vec_.front();
std::cout << "Display Req Data Contents " << std::endl;
std::cout << std::hex << "Data[0]: " << req->data[0] << std::endl;
std::cout << std::hex << "Data[1]: " << req->data[1] << std::endl;
std::cout << std::hex << "Data[2]: " << req->data[2] << std::endl;
std::cout << std::hex << "Data[3]: " << req->data[3] << std::endl;
cache_->core_req_valid = req->valid;
cache_->core_req_rw = req->rw;
cache_->core_req_byteen = req->byteen;
cache_->core_req_addr = req->addr;
cache_->core_req_data = req->data;
cache_->core_req_addr[0] = req->addr[0];
cache_->core_req_addr[1] = req->addr[1];
cache_->core_req_addr[2] = req->addr[2];
cache_->core_req_addr[3] = req->addr[3];
cache_->core_req_data[0] = req->data[0];
cache_->core_req_data[1] = req->data[1];
cache_->core_req_data[2] = req->data[2];
cache_->core_req_data[3] = req->data[3];
cache_->core_req_tag = req->tag;
}*/
std::cout << "Display Cache Data inputs: " << std::endl;
get_core_req();
core_req_vec_.pop();
std::cout << "Req Popped" << std::endl;
}
}
void CacheSim::eval_rsps(){
@ -268,3 +262,37 @@ void CacheSim::eval_dram_bus() {
cache_->dram_req_ready = ~dram_stalled;
}
//DEBUG
void CacheSim::get_core_rsp(){
std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
}
void CacheSim::get_core_req(){
char check = cache_->core_req_valid;
std::cout << std::hex << "core_req_valid: " << check << std::endl;
std::cout << std::hex << "core_req_data[0]: " << cache_->core_req_data[0] << std::endl;
std::cout << std::hex << "core_req_data[1]: " << cache_->core_req_data[1] << std::endl;
std::cout << std::hex << "core_req_data[2]: " << cache_->core_req_data[2] << std::endl;
std::cout << std::hex << "core_req_data[3]: " << cache_->core_req_data[3] << std::endl;
std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl;
}
void CacheSim::get_dram_req(){
std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl;
std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl;
std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl;
std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl;
std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl;
std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl;
}
void CacheSim::get_dram_rsp(){
std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl;
std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl;
std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl;
std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
}

12
hw/unit_tests/cache/cachesim.h vendored
View file

@ -27,13 +27,12 @@ typedef struct {
} dram_req_t;
typedef struct {
bool valid = 1;
unsigned rw;
char valid;
char rw;
unsigned byteen;
unsigned int *addr[4];
unsigned int *data[4];
unsigned *addr;
unsigned *data;
unsigned tag;
bool responded;
} core_req_t;
class CacheSim {
@ -60,6 +59,7 @@ public:
void get_dram_req();
void get_core_rsp();
void get_core_req();
bool get_core_req_ready();
bool get_core_rsp_ready();
void get_dram_rsp();
@ -73,7 +73,7 @@ private:
void eval_rsps();
void eval_dram_bus();
std::queue<core_req_t*> core_reqq_;
std::queue<core_req_t*> core_req_vec_;
std::vector<dram_req_t> dram_rsp_vec_;
int dram_rsp_active_;

48
hw/unit_tests/cache/testbench.cpp vendored
View file

@ -11,24 +11,47 @@ int main(int argc, char **argv)
RAM ram;
CacheSim cachesim;
cachesim.attach_ram(&ram);
unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
//write req
core_req_t* write = new core_req_t;
write->valid = 0xf;
write->rw = 0xf;
write->byteen = 0xffff;
write->addr = addr;
write->data = data;
write->tag = 0xff;
//read req
core_req_t* read = new core_req_t;
read->valid = 0xf;
read->rw = 0;
read->byteen = 0xffff;
read->addr = addr;
read->data = addr;
read->tag = 0xff;
// reset the device
cachesim.reset();
//queue reqs
cachesim.send_req(write);
cachesim.send_req(read);
cachesim.step();
//cachesim.get_core_req();
//write block to cache
cachesim.set_core_req();
// cachesim.set_core_req();
for (int i = 0; i < 100; ++i){
if(i == 1){
/*if(i == 1){
cachesim.clear_req();
}
}*/
cachesim.step();
cachesim.get_core_rsp();
}
cachesim.get_core_req();
// read block
cachesim.set_core_req2();
//cachesim.set_core_req2();
for (int i = 0; i < 100; ++i){
if(i == 1){
//read block from cache
@ -36,18 +59,7 @@ int main(int argc, char **argv)
}
cachesim.step();
cachesim.get_core_rsp();
}
/*
core_req_t *write;
write->valid = 1;
//write.tag = 0xff; //TODO: make a reasonable tag
//write.addr[0] = 0x11111111;
//write.addr[1] = 0x22222222;
//write.addr[2] = 0x33333333;
//write.addr[3] = 0x44444444;
//write.
*/
return 0;
}