fixed trace format consistency

sim/simx/cache_sim.cpp

@@ -400,7 +400,7 @@ public:
 				continue;
 
 			auto& mem_rsp = mem_rsp_port.front();
-			DT(3, simobject_->name() << "-dram-" << mem_rsp);
+			DT(3, simobject_->name() << "-bank" << bank_id << " fill-rsp: " << mem_rsp);
 			pipeline_req.type = bank_req_t::Fill;
 			pipeline_req.tag = mem_rsp.tag;
 			mem_rsp_port.pop();
@@ -473,7 +473,6 @@ public:
 				++perf_stats_.reads;
 
 			// remove request
-			DT(3, simobject_->name() << "-core-" << core_req);
 			auto time = core_req_port.pop();
 			perf_stats_.pipeline_stalls += (SimPlatform::instance().cycles() - time);
 		}
@@ -493,23 +492,21 @@ private:
 		uint64_t tag = mem_rsp.tag >> params_.log2_num_inputs;
 		MemRsp core_rsp{tag, mem_rsp.cid, mem_rsp.uuid};
 		simobject_->CoreRspPorts.at(req_id).push(core_rsp, config_.latency);
-		DT(3, simobject_->name() << "-core-" << core_rsp);
+		DT(3, simobject_->name() << " core-rsp: " << core_rsp);
 	}
 
 	void processBypassRequest(const MemReq& core_req, uint32_t req_id) {
-		DT(3, simobject_->name() << "-core-" << core_req);
-
 		{
 			MemReq mem_req(core_req);
 			mem_req.tag = (core_req.tag << params_.log2_num_inputs) + req_id;
 			bypass_switch_->ReqIn.at(1).push(mem_req, 1);
-			DT(3, simobject_->name() << "-dram-" << mem_req);
+			DT(3, simobject_->name() << " dram-req: " << mem_req);
 		}
 
 		if (core_req.write && config_.write_reponse) {
 			MemRsp core_rsp{core_req.tag, core_req.cid, core_req.uuid};
 			simobject_->CoreRspPorts.at(req_id).push(core_rsp, 1);
-			DT(3, simobject_->name() << "-core-" << core_rsp);
+			DT(3, simobject_->name() << " core-rsp: " << core_rsp);
 		}
 	}
 
@@ -539,7 +536,7 @@ private:
 							continue;
 						MemRsp core_rsp{info.req_tag, pipeline_req.cid, pipeline_req.uuid};
 						simobject_->CoreRspPorts.at(info.req_id).push(core_rsp, config_.latency);
-						DT(3, simobject_->name() << "-replay-" << core_rsp);
+						DT(3, simobject_->name() << "-bank" << bank_id << " replay: " << core_rsp);
 					}
 				}
 			} break;
@@ -583,7 +580,7 @@ private:
 							mem_req.cid   = pipeline_req.cid;
 							mem_req.uuid  = pipeline_req.uuid;
 							mem_req_ports_.at(bank_id).push(mem_req, 1);
-							DT(3, simobject_->name() << "-writethrough-" << mem_req);
+							DT(3, simobject_->name() << "-bank" << bank_id << " writethrough: " << mem_req);
 						} else {
 							// mark line as dirty
 							hit_line.dirty = true;
@@ -596,7 +593,7 @@ private:
 								continue;
 							MemRsp core_rsp{info.req_tag, pipeline_req.cid, pipeline_req.uuid};
 							simobject_->CoreRspPorts.at(info.req_id).push(core_rsp, config_.latency);
-							DT(3, simobject_->name() << "-core-" << core_rsp);
+							DT(3, simobject_->name() << "-bank" << bank_id << " core-rsp: " << core_rsp);
 						}
 					}
 				} else {
@@ -615,7 +612,7 @@ private:
 							mem_req.write = true;
 							mem_req.cid   = pipeline_req.cid;
 							mem_req_ports_.at(bank_id).push(mem_req, 1);
-							DT(3, simobject_->name() << "-writeback-" << mem_req);
+							DT(3, simobject_->name() << "-bank" << bank_id << " writeback: " << mem_req);
 							++perf_stats_.evictions;
 						}
 					}
@@ -629,7 +626,7 @@ private:
 							mem_req.cid   = pipeline_req.cid;
 							mem_req.uuid  = pipeline_req.uuid;
 							mem_req_ports_.at(bank_id).push(mem_req, 1);
-							DT(3, simobject_->name() << "-writethrough-" << mem_req);
+							DT(3, simobject_->name() << "-bank" << bank_id << " writethrough: " << mem_req);
 						}
 						// send core response
 						if (config_.write_reponse) {
@@ -638,7 +635,7 @@ private:
 									continue;
 								MemRsp core_rsp{info.req_tag, pipeline_req.cid, pipeline_req.uuid};
 								simobject_->CoreRspPorts.at(info.req_id).push(core_rsp, config_.latency);
-								DT(3, simobject_->name() << "-core-" << core_rsp);
+								DT(3, simobject_->name() << "-bank" << bank_id << " core-rsp: " << core_rsp);
 							}
 						}
 					} else {
@@ -657,7 +654,7 @@ private:
 							mem_req.cid   = pipeline_req.cid;
 							mem_req.uuid  = pipeline_req.uuid;
 							mem_req_ports_.at(bank_id).push(mem_req, 1);
-							DT(3, simobject_->name() << "-dram-" << mem_req);
+							DT(3, simobject_->name() << "-bank" << bank_id << " fill: " << mem_req);
 							++pending_fill_reqs_;
 						}
 					}

sim/simx/func_unit.cpp

@@ -49,7 +49,7 @@ void AluUnit::tick() {
 		default:
 			std::abort();
 		}
-		DT(3, this->name() << ": op" << trace->alu_type << ", " << *trace);
+		DT(3, this->name() << ": op=" << trace->alu_type << ", " << *trace);
 		if (trace->eop && trace->fetch_stall) {
 			core_->resume(trace->wid);
 		}
@@ -120,7 +120,7 @@ void LsuUnit::tick() {
 			continue;
 		auto& state = states_.at(b);
 		auto& lsu_rsp = lsu_rsp_port.front();
-		DT(3, this->name() << "-" << lsu_rsp);
+		DT(3, this->name() << " mem-rsp: " << lsu_rsp);
 		auto& entry = state.pending_rd_reqs.at(lsu_rsp.tag);
 		auto trace = entry.trace;
 		assert(!entry.mask.none());
@@ -145,7 +145,7 @@ void LsuUnit::tick() {
 				continue;
 			Outputs.at(iw).push(state.fence_trace, 1);
 			state.fence_lock = false;
-			DT(3, this->name() << "-fence-unlock: " << state.fence_trace);
+			DT(3, this->name() << " fence-unlock: " << state.fence_trace);
 		}
 
 		// check input queue
@@ -159,7 +159,7 @@ void LsuUnit::tick() {
 			// schedule fence lock
 			state.fence_trace = trace;
 			state.fence_lock = true;
-			DT(3, this->name() << "-fence-lock: " << *trace);
+			DT(3, this->name() << " fence-lock: " << *trace);
 			// remove input
 			input.pop();
 			continue;
@@ -170,7 +170,7 @@ void LsuUnit::tick() {
 		// check pending queue capacity
 		if (!is_write && state.pending_rd_reqs.full()) {
 			if (!trace->log_once(true)) {
-				DT(4, "*** " << this->name() << "-queue-full: " << *trace);
+				DT(4, "*** " << this->name() << " queue-full: " << *trace);
 			}
 			continue;
 		} else {
@@ -200,7 +200,7 @@ void LsuUnit::tick() {
 
 		// send memory request
 		core_->lsu_demux_.at(block_idx)->ReqIn.push(lsu_req);
-		DT(3, this->name() << "-" << lsu_req);
+		DT(3, this->name() << " mem-req: " << lsu_req);
 
 		// update stats
 		auto num_addrs = lsu_req.mask.count();

sim/simx/local_mem.cpp

@@ -82,7 +82,7 @@ public:
 				continue;
 			}
 
-			DT(4, simobject_->name() << "-" << core_req);
+			DT(4, simobject_->name() << " mem-req" << req_id << ": "<< core_req);
 
 			in_used_banks.at(bank_id) = true;
 

sim/simx/mem_coalescer.cpp

@@ -45,7 +45,7 @@ void MemCoalescer::tick() {
   // process incoming responses
   if (!RspOut.empty()) {
     auto& out_rsp = RspOut.front();
-    DT(4, this->name() << "-" << out_rsp);
+    DT(4, this->name() << " mem-rsp: " << out_rsp);
     auto& entry = pending_rd_reqs_.at(out_rsp.tag);
 
     BitVector<> rsp_mask(input_size_);
@@ -89,7 +89,7 @@ void MemCoalescer::tick() {
 
   // ensure we can allocate a response tag
   if (pending_rd_reqs_.full()) {
-    DT(4, "*** " << this->name() << "-queue-full: " << in_req);
+    DT(4, "*** " << this->name() << " queue-full: " << in_req);
     return;
   }
 
@@ -145,7 +145,7 @@ void MemCoalescer::tick() {
 
   // send memory request
   ReqOut.push(out_req, delay_);
-  DT(4, this->name() << "-" << out_req << ", coalesced=" << cur_mask.count());
+  DT(4, this->name() << " mem-req: coalesced=" << cur_mask.count() << ", " << out_req);
 
   // update sent mask
   sent_mask_ |= cur_mask;

sim/simx/mem_sim.cpp

@@ -74,7 +74,7 @@ public:
 				if (!rsp_args->request.write) {
 					MemRsp mem_rsp{rsp_args->request.tag, rsp_args->request.cid, rsp_args->request.uuid};
 					rsp_args->simobject->MemRspPort.push(mem_rsp, 1);
-					DT(3, rsp_args->simobject->name() << "-" << mem_rsp);
+					DT(3, rsp_args->simobject->name() << " mem-rsp: " << mem_rsp);
 				}
 				delete rsp_args;
 			},
@@ -93,7 +93,7 @@ public:
 			++perf_stats_.reads;
 		}
 
-		DT(3, simobject_->name() << "-" << mem_req);
+		DT(3, simobject_->name() << " mem-req: " << mem_req);
 
 		simobject_->MemReqPort.pop();
 	}

sim/simx/types.cpp

@@ -35,13 +35,13 @@ void LocalMemDemux::tick() {
   // process incoming responses
   if (!RspLmem.empty()) {
     auto& out_rsp = RspLmem.front();
-    DT(4, this->name() << "-" << out_rsp);
+    DT(4, this->name() << " lmem-rsp: " << out_rsp);
     RspIn.push(out_rsp, 1);
     RspLmem.pop();
   }
   if (!RspDC.empty()) {
     auto& out_rsp = RspDC.front();
-    DT(4, this->name() << "-" << out_rsp);
+    DT(4, this->name() << " dc-rsp: " << out_rsp);
     RspIn.push(out_rsp, 1);
     RspDC.pop();
   }
@@ -73,12 +73,12 @@ void LocalMemDemux::tick() {
 
     if (!out_dc_req.mask.none()) {
       ReqDC.push(out_dc_req, delay_);
-      DT(4, this->name() << "-" << out_dc_req);
+      DT(4, this->name() << " dc-req: " << out_dc_req);
     }
 
     if (!out_lmem_req.mask.none()) {
       ReqLmem.push(out_lmem_req, delay_);
-      DT(4, this->name() << "-" << out_lmem_req);
+      DT(4, this->name() << " lmem-req: " << out_lmem_req);
     }
     ReqIn.pop();
   }
@@ -109,7 +109,7 @@ void LsuMemAdapter::tick() {
     if (RspOut.at(i).empty())
       continue;
     auto& out_rsp = RspOut.at(i).front();
-    DT(4, this->name() << "-" << out_rsp);
+    DT(4, this->name() << " rsp" << i << ": " << out_rsp);
 
     // build memory response
     LsuRsp in_rsp(input_size);
@@ -155,7 +155,7 @@ void LsuMemAdapter::tick() {
 
         // send memory request
         ReqOut.at(i).push(out_req, delay_);
-        DT(4, this->name() << "-" << out_req);
+        DT(4, this->name() << " req" << i << ": " << out_req);
       }
     }
     ReqIn.pop();

sim/simx/types.h

@@ -260,7 +260,7 @@ struct LsuReq {
 };
 
 inline std::ostream &operator<<(std::ostream &os, const LsuReq& req) {
-  os << "lsu-req: rw=" << req.write << ", mask=" << req.mask << ", ";
+  os << "rw=" << req.write << ", mask=" << req.mask << ", ";
   for (size_t i = 0; i < req.mask.size(); ++i) {
     os << "addr" << i << "=";
     if (req.mask.test(i)) {
@@ -292,7 +292,7 @@ struct LsuRsp {
 };
 
 inline std::ostream &operator<<(std::ostream &os, const LsuRsp& rsp) {
-  os << "lsu-rsp: mask=" << rsp.mask << ", tag=" << rsp.tag << ", cid=" << rsp.cid;
+  os << "mask=" << rsp.mask << ", tag=" << rsp.tag << ", cid=" << rsp.cid;
   os << " (#" << std::dec << rsp.uuid << ")";
   return os;
 }
@@ -323,7 +323,7 @@ struct MemReq {
 };
 
 inline std::ostream &operator<<(std::ostream &os, const MemReq& req) {
-  os << "mem-req: rw=" << req.write << ", ";
+  os << "rw=" << req.write << ", ";
   os << "addr=0x" << std::hex << req.addr << ", type=" << req.type;
   os << std::dec << ", tag=" << req.tag << ", cid=" << req.cid;
   os << " (#" << std::dec << req.uuid << ")";
@@ -345,7 +345,7 @@ struct MemRsp {
 };
 
 inline std::ostream &operator<<(std::ostream &os, const MemRsp& rsp) {
-  os << "mem-rsp: tag=" << rsp.tag << ", cid=" << rsp.cid;
+  os << "tag=" << rsp.tag << ", cid=" << rsp.cid;
   os << " (#" << std::dec << rsp.uuid << ")";
   return os;
 }
@@ -574,7 +574,7 @@ public:
           i = rsp.tag & (R-1);
           rsp.tag >>= lg_num_reqs_;
         }
-        DT(4, this->name() << "-" << rsp);
+        DT(4, this->name() << " rsp" << o << ": " << rsp);
         uint32_t j = o * R + i;
         RspIn.at(j).push(rsp, 1);
         RspOut.at(o).pop();
@@ -593,7 +593,7 @@ public:
           if (lg_num_reqs_ != 0) {
             req.tag = (req.tag << lg_num_reqs_) | i;
           }
-          DT(4, this->name() << "-" << req);
+          DT(4, this->name() << " req" << j << ": " << req);
           ReqOut.at(o).push(req, delay_);
           req_in.pop();
           this->update_cursor(o, i);