fixed xilinx fpu ip dut synthesis

hw/syn/xilinx/dut/common.mk

@@ -25,7 +25,11 @@ project_1/sources.txt:
 
 build: $(PROJECT).xpr
 $(PROJECT).xpr: project_1/sources.txt
-	$(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR)
+ifdef FPU_IP
+	FPU_IP=project_1/ip $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR) $(SRC_DIR)/../scripts
+else
+	$(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR) $(SRC_DIR)/../scripts
+endif
 
 clean:
 	rm -rf project_1

hw/syn/xilinx/dut/core/Makefile

@@ -1,6 +1,7 @@
 PROJECT = VX_core_top
 TOP_LEVEL_ENTITY = $(PROJECT)
 SRC_FILE = $(PROJECT).sv
+FPU_IP = 1
 
 include ../../common.mk
 

hw/syn/xilinx/dut/fpu/Makefile

@@ -1,6 +1,7 @@
 PROJECT = VX_fpu_dsp
 TOP_LEVEL_ENTITY = $(PROJECT)
 SRC_FILE = $(PROJECT).sv
+FPU_IP = 1
 
 include ../../common.mk
 

hw/syn/xilinx/dut/project.tcl

@@ -14,9 +14,9 @@
 # Start time
 set start_time [clock seconds]
 
-if { $::argc != 5 } {
+if { $::argc != 6 } {
     puts "ERROR: Program \"$::argv0\" requires 5 arguments!\n"
-    puts "Usage: $::argv0 <top_module> <device_part> <vcs_file> <xdc_file> <tool_dir>\n"
+    puts "Usage: $::argv0 <top_module> <device_part> <vcs_file> <xdc_file> <tool_dir> <script_dir>\n"
     exit
 }
 
@@ -28,6 +28,7 @@ set device_part [lindex $::argv 1]
 set vcs_file [lindex $::argv 2]
 set xdc_file [lindex $::argv 3]
 set tool_dir [lindex $::argv 4]
+set script_dir [lindex $::argv 5]
 
 #puts top_module
 #puts $device_part
@@ -35,6 +36,14 @@ set tool_dir [lindex $::argv 4]
 #puts xdc_file
 #puts $tool_dir
 
+# create fpu ip
+if {[info exists ::env(FPU_IP)]} {
+  set ip_dir $::env(FPU_IP)
+  set argv [list $ip_dir $device_part]
+  set argc 2
+  source ${script_dir}/gen_ip.tcl
+}
+
 source "${tool_dir}/parse_vcs_list.tcl"
 set vlist [parse_vcs_list "${vcs_file}"]
 
@@ -61,25 +70,38 @@ foreach def $vdefines_list {
   set_property verilog_define $def $obj
 }
 
+# add fpu ip
+if {[info exists ::env(FPU_IP)]} {
+  set ip_dir $::env(FPU_IP)
+  add_files -norecurse -verbose ${ip_dir}/xil_fma/xil_fma.xci
+  add_files -norecurse -verbose ${ip_dir}/xil_fdiv/xil_fdiv.xci
+  add_files -norecurse -verbose ${ip_dir}/xil_fsqrt/xil_fsqrt.xci
+}
+
+update_compile_order -fileset sources_1
+
+set_property top $top_module [current_fileset]
+set_property \
+    -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} \
+    -value {-mode out_of_context -flatten_hierarchy "rebuilt"} \
+    -objects [get_runs synth_1]
+
 # Synthesis
-synth_design -top $top_module -include_dirs $vincludes_list -mode out_of_context -flatten_hierarchy none
+launch_runs synth_1
+wait_on_run synth_1
+open_run synth_1
 write_checkpoint -force post_synth.dcp
 report_utilization -file utilization.rpt -hierarchical -hierarchical_percentages
 
-# Optimize
-opt_design
-
-# Place
-place_design
-write_checkpoint -force post_place.dcp
-report_place_status -file place.rpt
-
-# Route
-route_design
-write_checkpoint -force post_route.dcp
-report_route_status -file route.rpt
+# Implementation
+launch_runs impl_1
+wait_on_run impl_1
+open_run impl_1
+write_checkpoint -force post_impl.dcp
 
 # Generate the synthesis report
+report_place_status -file place.rpt
+report_route_status -file route.rpt
 report_timing_summary -file timing.rpt
 report_power -file power.rpt
 report_drc -file drc.rpt

hw/syn/xilinx/dut/top/Makefile

@@ -1,6 +1,7 @@
 PROJECT = vortex_afu
 TOP_LEVEL_ENTITY = $(PROJECT)
 SRC_FILE = $(PROJECT).sv
+FPU_IP = 1
 
 include ../../common.mk
 

hw/syn/xilinx/dut/vortex/Makefile

@@ -1,6 +1,7 @@
 PROJECT = Vortex
 TOP_LEVEL_ENTITY = $(PROJECT)
 SRC_FILE = $(PROJECT).sv
+FPU_IP = 1
 
 include ../../common.mk
 

hw/syn/xilinx/sandbox/project.tcl.in

@@ -397,14 +397,16 @@ update_compile_order -fileset sources_1
 launch_runs synth_1
 wait_on_run synth_1
 open_run synth_1
+write_checkpoint -force post_synth.dcp
+report_utilization -file utilization.rpt -hierarchical -hierarchical_percentages
 
 # Implementation
 launch_runs impl_1
 wait_on_run impl_1
 open_run impl_1
+write_checkpoint -force post_impl.dcp
 
 # Generate reports
-report_utilization -file utilization.rpt -hierarchical -hierarchical_percentages
 report_place_status -file place.rpt
 report_route_status -file route.rpt
 report_timing_summary -file timing.rpt

hw/syn/xilinx/scripts/gen_ip.tcl

@@ -1,31 +1,36 @@
 # Copyright © 2019-2023
-# 
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 # http://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-if { $::argc != 1 } {
-    puts "ERROR: Program \"$::argv0\" requires 1 arguments!\n"
-    puts "Usage: $::argv0 <ip_dir>\n"
+if { $::argc < 1 || $::argc > 2 } {
+    puts "ERROR: Program \"$::argv0\" requires 1 or 2 arguments!\n"
+    puts "Usage: $::argv0 <ip_dir> [<device_part>]\n"
     exit
 }
 
 set ip_dir [lindex $::argv 0]
 
+# create_ip requires that a project is open in memory.
+if { $::argc == 2 } {
+    set device_part [lindex $::argv 1]
+    create_project -in_memory -part $device_part
+} else {
+    # Create project without specifying a device part
+    create_project -in_memory
+}
+
 # IP folder does not exist. Create IP folder
 file mkdir ${ip_dir}
 
-# create_ip requires that a project is open in memory. 
-# Create project but don't do anything with it
-create_project -in_memory
-
 create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fdiv -dir ${ip_dir}
 set_property -dict [list CONFIG.Component_Name {xil_fdiv} CONFIG.Operation_Type {Divide} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.C_Has_DIVIDE_BY_ZERO {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fdiv]
 

hw/syn/xilinx/scripts/package_kernel.tcl

@@ -1,10 +1,10 @@
 # Copyright © 2019-2023
-# 
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 # http://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -51,15 +51,15 @@ create_project -force kernel_pack $path_to_tmp_project
 add_files -norecurse ${vsources_list}
 
 set obj [get_filesets sources_1]
-set files [list \
+set ip_files [list \
  [file normalize "${build_dir}/ip/xil_fdiv/xil_fdiv.xci"] \
  [file normalize "${build_dir}/ip/xil_fma/xil_fma.xci"] \
  [file normalize "${build_dir}/ip/xil_fsqrt/xil_fsqrt.xci"] \
 ]
-add_files -verbose -norecurse -fileset $obj $files
+add_files -verbose -norecurse -fileset $obj $ip_files
 
 set_property include_dirs ${vincludes_list} [current_fileset]
-#set_property verilog_define ${vdefines_list} [current_fileset]
+set_property verilog_define ${vdefines_list} [current_fileset]
 
 set obj [get_filesets sources_1]
 set_property -verbose -name "top" -value ${krnl_name} -objects $obj
@@ -238,7 +238,7 @@ for {set i 0} {$i < 1} {incr i} {
     set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
     set_property address_offset [expr {0x040 + $i * 12}] $reg
     set_property size           [expr {8*8}]   $reg
-    set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg] 
+    set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
     set_property value m_axi_mem_$i $regparam
 }
 

hw/syn/xilinx/xrt/Makefile

@@ -163,7 +163,7 @@ $(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
 
 gen-xo: $(XO_CONTAINER)
 $(XO_CONTAINER): $(BUILD_DIR)/sources.txt
-	mkdir -p $(BUILD_DIR); cd $(BUILD_DIR);	$(VIVADO) -mode batch -source $(SRC_DIR)/scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
+	mkdir -p $(BUILD_DIR); cd $(BUILD_DIR);	$(VIVADO) -mode batch -source $(SRC_DIR)/../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
 
 gen-bin: $(XCLBIN_CONTAINER)
 $(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON)