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minor update

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This commit is contained in:
Blaise Tine 2024-10-17 11:25:17 -07:00
parent 077b682d7d
commit 91fee5da11
2 changed files with 17 additions and 14 deletions
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2
hw/rtl/cache/VX_cache_bank.sv vendored
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@ -440,7 +440,7 @@ module VX_cache_bank #(
end else begin
if (~crsp_queue_stall) begin
post_hazard <= rdw_hazard;
rdw_hazard <= do_write_st0 && valid_sel && ~(is_write_sel || (is_same_line && !WRITEBACK && (/*is_fill_sel ||*/is_flush_sel)));
rdw_hazard <= do_write_st0 && valid_sel && ~(is_write_sel || (is_same_line && !WRITEBACK && (is_fill_sel || is_flush_sel)));
end
end
end

29
hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -79,18 +79,20 @@ module VX_cache_data #(
wire [NUM_WAYS-1:0][BYTEEN_DATAW-1:0] byteen_wren;
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_byteen_wdata
wire evict = fill || flush;
wire evict_way_en = (NUM_WAYS == 1) || evict_way[i];
wire dirty_data = write; // only asserted on writes
wire dirty_wren = init || (write ? tag_matches[i] : evict_way_en);
wire dirty_wren = init || (evict && evict_way_en) || (write && tag_matches[i]);
if (DIRTY_BYTES != 0) begin : g_dirty_bytes
wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] bytes_data;
wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] bytes_wren;
for (genvar j = 0; j < `CS_WORDS_PER_LINE; ++j) begin : g_words
wire word_en = ((`CS_WORDS_PER_LINE == 1) || (word_idx == j));
wire [WORD_SIZE-1:0] write_mask = write_byteen & {WORD_SIZE{word_en && tag_matches[i]}};
assign bytes_data[j] = {WORD_SIZE{write}}; // only asserted on writes
assign bytes_wren[j] = {WORD_SIZE{init}} | (write ? write_mask : {WORD_SIZE{evict_way_en}});
wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_mask;
for (genvar j = 0; j < `CS_WORDS_PER_LINE; ++j) begin : g_write_mask
wire word_en = (`CS_WORDS_PER_LINE == 1) || (word_idx == j);
assign write_mask[j] = write_byteen & {WORD_SIZE{word_en}};
end
wire [LINE_SIZE-1:0] bytes_data = {LINE_SIZE{write}}; // only asserted on writes
wire [LINE_SIZE-1:0] bytes_wren = {LINE_SIZE{init}}
| {LINE_SIZE{evict && evict_way_en}}
| ({LINE_SIZE{write && tag_matches[i]}} & write_mask);
assign byteen_wdata[i] = {dirty_data, bytes_data};
assign byteen_wren[i] = {dirty_wren, bytes_wren};
end else begin : g_no_dirty_bytes
@ -145,13 +147,14 @@ module VX_cache_data #(
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_ways
wire fill_way_en = (NUM_WAYS == 1) || evict_way[i];
if (WRITE_ENABLE != 0) begin : g_we
wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_wren;
for (genvar j = 0; j < `CS_WORDS_PER_LINE; ++j) begin : g_write_wren
wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_mask;
for (genvar j = 0; j < `CS_WORDS_PER_LINE; ++j) begin : g_write_mask
wire word_en = (`CS_WORDS_PER_LINE == 1) || (word_idx == j);
assign write_wren[j] = write_byteen & {WORD_SIZE{word_en}};
assign write_mask[j] = write_byteen & {WORD_SIZE{word_en}};
end
assign line_wdata[i] = fill ? fill_data : {`CS_WORDS_PER_LINE{write_word}};
assign line_wren_w[i] = fill ? {LINE_SIZE{fill_way_en}} : (write_wren & {LINE_SIZE{tag_matches[i]}});
assign line_wdata[i] = (fill && fill_way_en) ? fill_data : {`CS_WORDS_PER_LINE{write_word}};
assign line_wren_w[i] = {LINE_SIZE{fill && fill_way_en}}
| ({LINE_SIZE{write && tag_matches[i]}} & write_mask);
end else begin : g_ro
`UNUSED_VAR (write)
`UNUSED_VAR (write_byteen)