mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
fpga build refactoring
This commit is contained in:
Blaise Tine
parent
2216a3059d
commit
95f057bc2e
16 changed files with 185 additions and 208 deletions
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@ -21,15 +21,17 @@ make -s
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1"
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# Build tests disabling extensions
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# disabling M extension
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CONFIGS=-DEXT_M_DISABLE make -C hw/simulate
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# disabling F extension
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CONFIGS=-DEXT_F_DISABLE make -C hw/simulate
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# disable shared memory
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CONFIGS=-DSM_ENABLE=0 make -C hw/simulate
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# test 128-bit DRAM bus
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CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS=4 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
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# using FPNEW core
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FPU_CORE=FPU_FPNEW ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
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# test 256-bit DRAM bus
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# test 128-bit DRAM bus
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CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS=4 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
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@ -82,8 +82,9 @@ endif
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VL_FLAGS += -DNOPAE
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CFLAGS += -DNOPAE
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# use DPI FPU
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VL_FLAGS += -DFPU_DPI
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# FPU backend
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FPU_CORE ?= FPU_DPI
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VL_FLAGS += -D$(FPU_CORE)
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PROJECT = libopae-c-vlsim.so
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@ -68,8 +68,9 @@ ifdef PERF
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CFLAGS += -DPERF_ENABLE
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endif
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# use DPI FPU
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VL_FLAGS += -DFPU_DPI
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# FPU backend
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FPU_CORE ?= FPU_DPI
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VL_FLAGS += -D$(FPU_CORE)
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PROJECT = libvortex.so
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# PROJECT = libvortex.dylib
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@ -243,7 +243,7 @@
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`define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0)
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// Block size in bytes
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`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
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`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
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// Word size in bytes
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`define IWORD_SIZE 4
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@ -10,9 +10,7 @@
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/* verilator lint_off IMPORTSTAR */
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import ccip_if_pkg::*;
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import local_mem_cfg_pkg::*;
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/* verilator lint_on IMPORTSTAR */
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`define MEM_BLOCK_SIZE LOCAL_MEM_DATA_N_BYTES
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/* verilator lint_on IMPORTSTAR */
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`include "VX_define.vh"
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@ -49,8 +49,9 @@ VL_FLAGS += verilator.vlt
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VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE)
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VL_FLAGS += --cc Vortex.v --top-module $(TOP)
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# Use FPNEW PFU core
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VL_FLAGS += -DFPU_FPNEW
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# FPU backend
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FPU_CORE ?= FPU_DPI
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VL_FLAGS += -D$(FPU_CORE)
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DBG_FLAGS += -DVCD_OUTPUT
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@ -1,11 +1,14 @@
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ASE_BUILD_DIR ?= build_ase
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FPGA_BUILD_DIR ?= build_fpga
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DEVICE_FAMILY ?= arria10
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RTL_DIR=../../rtl
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ifdef $(shell [[ '$(FPGA_CLASS)' =~ 'fpga-pac-s10' ]] && echo matched)
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DEVICE_FAMILY ?= stratix10
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else
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DEVICE_FAMILY ?= arria10
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ifeq ($(DEVICE_FAMILY),arria10)
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CFLAGS += -DMEM_BLOCK_SIZE=64
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endif
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ifeq ($(DEVICE_FAMILY),stratix10)
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CFLAGS += -DMEM_BLOCK_SIZE=16
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endif
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ifeq ($(shell which qsub-synth),)
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@ -14,22 +17,106 @@ else
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RUN_SYNTH=qsub-synth
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endif
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# control RTL debug print states
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DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA
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DBG_PRINT_FLAGS += -DDBG_PRINT_MEM
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DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
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DBG_PRINT_FLAGS += -DDBG_PRINT_AVS
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DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
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DBG_FLAGS += $(DBG_PRINT_FLAGS)
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DBG_FLAGS += -DDBG_CACHE_REQ_INFO
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CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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CONFIG8 := -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
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FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
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RTL_INCLUDE = -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/afu
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CFLAGS += $(RTL_INCLUDE)
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# Debugigng
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ifdef DEBUG
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CFLAGS += $(DBG_FLAGS)
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else
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CFLAGS += -DNDEBUG
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endif
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# Enable scope analyzer
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ifdef SCOPE
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CFLAGS += -DSCOPE
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endif
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# Enable perf counters
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ifdef PERF
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CFLAGS += -DPERF_ENABLE
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endif
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all: ase-1c
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gen-sources:
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./gen_sources.sh $(DEVICE_FAMILY) > sources.txt
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$(ASE_BUILD_DIR)_1c/Makefile:
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afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_1c
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ase-1c: gen-sources setup-ase-1c
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make -C $(ASE_BUILD_DIR)_1c
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cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
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$(ASE_BUILD_DIR)_2c/Makefile:
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afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_2c
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ase-2c: gen-sources setup-ase-2c
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make -C $(ASE_BUILD_DIR)_2c
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cp $(RTL_DIR)/fp_cores/altera/arria$(DEVICE_FAMILY)10/*.hex $(ASE_BUILD_DIR)_2c/work
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$(ASE_BUILD_DIR)_4c/Makefile:
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afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_4c
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ase-4c: gen-sources setup-ase-4c
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make -C $(ASE_BUILD_DIR)_4c
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cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_4c/work
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$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_1c
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$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_2c
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$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_4c
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$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_8c
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$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_16c
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$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_32c
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$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
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afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_64c
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gen-sources-1c:
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./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt
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gen-sources-2c:
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./gen_sources.sh $(CFLAGS) $(CONFIG2) > sources.txt
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gen-sources-4c:
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./gen_sources.sh $(CFLAGS) $(CONFIG4) > sources.txt
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gen-sources-8c:
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./gen_sources.sh $(CFLAGS) $(CONFIG8) > sources.txt
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gen-sources-16c:
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./gen_sources.sh $(CFLAGS) $(CONFIG16) > sources.txt
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gen-sources-32c:
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./gen_sources.sh $(CFLAGS) $(CONFIG32) > sources.txt
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gen-sources-64c:
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./gen_sources.sh $(CFLAGS) $(CONFIG64) > sources.txt
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# setup
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setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
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@ -37,36 +124,6 @@ setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile
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setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile
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$(ASE_BUILD_DIR)_1c/Makefile:
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afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
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$(ASE_BUILD_DIR)_2c/Makefile:
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afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c
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$(ASE_BUILD_DIR)_4c/Makefile:
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afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
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fpga-1c: gen-sources setup-fpga-1c
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cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
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fpga-2c: gen-sources setup-fpga-2c
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cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
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fpga-4c: gen-sources setup-fpga-4c
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cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
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fpga-8c: gen-sources setup-fpga-8c
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cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
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fpga-16c: gen-sources setup-fpga-16c
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cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
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fpga-32c: gen-sources setup-fpga-32c
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cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
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fpga-64c: gen-sources setup-fpga-64c
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cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
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setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
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setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf
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@ -81,35 +138,42 @@ setup-fpga-32c: $(FPGA_BUILD_DIR)_32c/build/dcp.qpf
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setup-fpga-64c: $(FPGA_BUILD_DIR)_64c/build/dcp.qpf
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$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
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afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
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# build
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$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
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afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c
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ase-1c: gen-sources-1c setup-ase-1c
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make -C $(ASE_BUILD_DIR)_1c
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cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
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$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
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afu_synth_setup -s sources_4c.txt $(FPGA_BUILD_DIR)_4c
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ase-2c: gen-sources-2c setup-ase-2c
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make -C $(ASE_BUILD_DIR)_2c
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cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_2c/work
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$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
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afu_synth_setup -s sources_8c.txt $(FPGA_BUILD_DIR)_8c
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ase-4c: gen-sources-4c setup-ase-4c
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make -C $(ASE_BUILD_DIR)_4c
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cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_4c/work
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$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
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afu_synth_setup -s sources_16c.txt $(FPGA_BUILD_DIR)_16c
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fpga-1c: gen-sources-1c setup-fpga-1c
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cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
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$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
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afu_synth_setup -s sources_32c.txt $(FPGA_BUILD_DIR)_32c
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fpga-2c: gen-sources-2c setup-fpga-2c
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cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
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$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
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afu_synth_setup -s sources_64c.txt $(FPGA_BUILD_DIR)_64c
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fpga-4c: gen-sources-4c setup-fpga-4c
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cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
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run-ase-1c:
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cd $(ASE_BUILD_DIR)_1c && make sim
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fpga-8c: gen-sources-8c setup-fpga-8c
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cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
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run-ase-2c:
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cd $(ASE_BUILD_DIR)_2c && make sim
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fpga-16c: gen-sources-16c setup-fpga-16c
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cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
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run-ase-4c:
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cd $(ASE_BUILD_DIR)_4c && make sim
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fpga-32c: gen-sources-32c setup-fpga-32c
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cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
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fpga-64c: gen-sources-64c setup-fpga-64c
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cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
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# cleanup
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clean-ase-1c:
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rm -rf $(ASE_BUILD_DIR)_1c sources.txt
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@ -97,15 +97,4 @@ tar -xvf vortex.vcd.tar.bz2
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lsof +D build_ase_1c
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# quick off synthesis
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make -C unittest clean && make -C unittest > unittest/build.log 2>&1 &
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make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 &
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make -C cache clean && make -C cache > cache/build.log 2>&1 &
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make -C core clean && make -C core > core/build.log 2>&1 &
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make -C vortex clean && make -C vortex > vortex/build.log 2>&1 &
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make -C top1 clean && make -C top1 > top1/build.log 2>&1 &
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make -C top2 clean && make -C top2 > top2/build.log 2>&1 &
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make -C top4 clean && make -C top4 > top4/build.log 2>&1 &
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make -C top8 clean && make -C top8 > top8/build.log 2>&1 &
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make -C top16 clean && make -C top16 > top16/build.log 2>&1 &
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make -C top32 clean && make -C top32 > top32/build.log 2>&1 &
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make -C top64 clean && make -C top64 > top64/build.log 2>&1 &
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make core
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@ -1,40 +1,46 @@
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#!/bin/bash
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rtl_dir="../../rtl"
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exclude_list="VX_fpu_fpnew.v"
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file_list=""
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device_family=$1
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macros=()
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includes=()
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add_dirs()
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{
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for dir in $*; do
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echo "+incdir+$dir"
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
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exclude=0
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for fe in $exclude_list; do
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if [[ $file =~ $fe ]]; then
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exclude=1
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fi
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done
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if [[ $exclude == 0 ]]; then
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file_list="$file_list $file"
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# parse command arguments
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while getopts D:I:h flag
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do
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case "${flag}" in
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D) macros+=( ${OPTARG} );;
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I) includes+=( ${OPTARG} );;
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h) echo "Usage: [-D macro] [-I include] [-h help]"
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exit 0
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;;
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\?)
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echo "Invalid option: -$OPTARG" 1>&2
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exit 1
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;;
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esac
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done
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# dump macros
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for value in ${macros[@]}; do
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echo "+define+$value"
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done
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# dump include directories
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for dir in ${includes[@]}; do
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echo "+incdir+$dir"
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done
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# dump source files
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for dir in ${includes[@]}; do
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
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exclude=0
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for fe in $exclude_list; do
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if [[ $file =~ $fe ]]; then
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exclude=1
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fi
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done
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if [[ $exclude == 0 ]]; then
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echo $file
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fi
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done
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}
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add_files()
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{
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for file in $*; do
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file_list="$file_list $file"
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done
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}
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add_dirs $rtl_dir/fp_cores/altera/$device_family
|
||||
|
||||
add_dirs $rtl_dir/libs $rtl_dir/interfaces $rtl_dir/fp_cores $rtl_dir/cache $rtl_dir $rtl_dir/afu
|
||||
|
||||
# dump file list
|
||||
for file in $file_list; do
|
||||
echo $file
|
||||
done
|
||||
|
|
@ -1,8 +1,5 @@
|
|||
+define+NUM_CORES=4
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
+define+NUM_CORES=4
|
||||
+define+NUM_CLUSTERS=4
|
||||
#+define+L3_ENABLE=1
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
vortex_afu16.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
+define+NUM_CORES=1
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+SCOPE
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
#+define+DBG_PRINT_CORE_ICACHE
|
||||
#+define+DBG_PRINT_CORE_DCACHE
|
||||
#+define+DBG_PRINT_CACHE_BANK
|
||||
#+define+DBG_PRINT_CACHE_MSHR
|
||||
#+define+DBG_PRINT_CACHE_TAG
|
||||
#+define+DBG_PRINT_CACHE_DATA
|
||||
#+define+DBG_PRINT_DRAM
|
||||
#+define+DBG_PRINT_PIPELINE
|
||||
#+define+DBG_PRINT_OPAE
|
||||
#+define+DBG_PRINT_AVS
|
||||
#+define+DBG_PRINT_SCOPE
|
||||
#+define+DBG_CACHE_REQ_INFO
|
||||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
+define+NUM_CORES=2
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
+define+NUM_CORES=8
|
||||
+define+NUM_CLUSTERS=4
|
||||
#+define+L3_ENABLE=1
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
+define+NUM_CORES=8
|
||||
+define+NUM_CLUSTERS=8
|
||||
#+define+L3_ENABLE=1
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
+define+NUM_CORES=4
|
||||
+define+NUM_CLUSTERS=2
|
||||
#+define+L3_ENABLE=1
|
||||
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
#+define+PERF_ENABLE
|
||||
|
||||
vortex_afu8.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
Loading…
Add table
Add a link
Reference in a new issue